CN116230702B - Packaging structure of GaN chip - Google Patents
Packaging structure of GaN chip Download PDFInfo
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- CN116230702B CN116230702B CN202310507410.4A CN202310507410A CN116230702B CN 116230702 B CN116230702 B CN 116230702B CN 202310507410 A CN202310507410 A CN 202310507410A CN 116230702 B CN116230702 B CN 116230702B
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- gan chip
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052802 copper Inorganic materials 0.000 claims abstract description 13
- 239000010949 copper Substances 0.000 claims abstract description 13
- 230000005669 field effect Effects 0.000 claims abstract description 5
- 239000000853 adhesive Substances 0.000 claims description 10
- 230000001070 adhesive effect Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000003754 machining Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 238000003466 welding Methods 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 238000003475 lamination Methods 0.000 claims description 2
- 238000004891 communication Methods 0.000 abstract description 3
- 229910002601 GaN Inorganic materials 0.000 description 90
- 230000002159 abnormal effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910001316 Ag alloy Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/16258—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Packaging Frangible Articles (AREA)
Abstract
The invention relates to a packaging structure of a GaN chip, which comprises a frame base island, frame pins, the GaN chip, a control chip and a plastic packaging body, wherein the GaN chip is a field effect tube, the GaN chip is positively fixed on the frame base island, the control pins on the control chip are led out in a copper column mode, the control chip is inversely arranged on the frame pins and the GaN chip, and a plurality of control pins on the control chip are respectively and directly welded and fixed with a G pole of the GaN chip, the frame base island and the frame pins. According to the invention, the innovative 3D stacking structure is used, the control pins on the control chip are led out in a copper column mode, then the control chip is arranged on the frame pins and the GaN chip in a flip-chip manner, the G pole communication distance between the control pins on the control chip and the GaN chip is greatly shortened, the conductive area of the copper column is large, the generated self-inductance is extremely small, and the influence on the switching speed of the GaN chip is greatly reduced, so that the GaN chip fully exerts the efficacy.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure of a GaN chip.
Background
The third generation semiconductor GaN chip (gallium nitride) is a field effect transistor widely used, and has the main advantages that the switching speed can be 7 nanoseconds, which is 10 times shorter than that of the traditional MOSFET, and the on and off of the third generation semiconductor GaN chip is controlled by a control chip. As shown in fig. 1, a conventional GaN chip includes a G electrode, an S electrode and a D electrode, wherein the G electrode is a control electrode, as shown in fig. 2, a package structure of a GaN chip in related art includes a frame base 1, a frame lead 2, a GaN chip 3, a control chip 4 and a plastic package (not shown), the GaN chip 3 and the control chip 4 are all fixed on the frame base 1 in a positive manner, the S electrodes of the GaN chip 3 are electrically connected with the frame base 1 through bonding wires 6 (typically gold wires or copper wires), the D electrode of the GaN chip 3 is connected with the frame lead 2 through bonding wires 6, the G electrode of the GaN chip 3 is connected with a control lead 41 of the control chip 4 through bonding wires 6, other control leads 41 of the control chip 4 are also connected with the frame base 1 and the frame lead 2 through bonding wires 6, the control chip 4 generates self-inductance in the bonding wire 6 in the switching process of the GaN chip 3, and the self-inductance can interfere with the switching speed, so that the shorter the bonding wire 6 between the control pin 41 of the control chip 4 and the G pole of the GaN chip 3 is, the better, as shown in fig. 2, the plane length L=0.737 mm of the bonding wire 6 between the G pole of the GaN chip 3 and the control pin 41 of the control chip 4, the total length of the bonding wire 6 after the wire is on the arc is about 1.032mm (1.4 times of the plane length), and the diameter of the bonding wire 6 is smaller, namely 38 mu m, 42 mu m or 50 mu m is mostly, the smaller the conductive area is, and the generated self-inductance is larger, so that the influence on the switching speed of the GaN chip 3 is larger; in addition, two rows of frame pins 2 are respectively arranged on two opposite sides of the package structure, and the whole package size is 6mm x 5mm, which needs to be further improved.
Disclosure of Invention
Aiming at the pain point, the invention provides a packaging structure of a GaN chip, which can greatly shorten the interval between a control pin of a control chip and a G pole of the GaN chip, reduce self-inductance, reduce the influence on the switching speed of the GaN chip and enable the GaN chip to fully exert the efficacy.
The invention is realized in the following way: the utility model provides a packaging structure of GaN chip, includes frame base island, frame pin, gaN chip, control chip and plastic envelope body, the plastic envelope body is used for plastic envelope frame base island, frame pin, gaN chip and control chip, the GaN chip is field effect transistor, including G utmost point, S utmost point and D utmost point, the positive dress of GaN chip is fixed on the frame base island, the S utmost point of GaN chip passes through the bonding wire and is connected with frame base island electricity, and the D utmost point of GaN chip passes through the bonding wire and is connected with the frame pin, control pin on the control chip draws forth with the mode of copper post, control chip flip-chip sets up on frame pin and GaN chip, a plurality of control pins on the control chip respectively with the G utmost point of GaN chip, frame base island and frame pin direct welded fastening.
The control chip and the GaN chip are arranged in a 3D lamination mode and are parallel to each other.
The GaN chip is fixedly arranged in the groove, the upper surface of the GaN chip is flush with the upper surfaces of the frame base island and the frame pins, and the heights of a plurality of control pins on the control chip are the same.
Wherein the grooves are made by removing material by machining, or by removing material by laser machining, or by etching.
The middle part of the frame base island is bent downwards to form a sinking table, the GaN chip is fixedly arranged in the sinking table, the upper surface of the GaN chip is flush with the upper surfaces of the frame base island and the frame pins, the outer side ends of the frame pins are also bent downwards, the lower surfaces of the frame pins are flush with the lower surface of the frame base island, and the heights of a plurality of control pins on the control chip are the same.
The upper surface of the frame base island is flush with the upper surface of the frame pin, the height of the control pin connected with the frame base island on the control chip is A, the height of the control pin connected with the frame pin on the control chip is B, and the height of the control pin connected with the G pole of the GaN chip on the control chip is C, wherein A=B > C.
The GaN chip is fixed on the frame base island through adhesive.
The bottom of the inner side end of the frame pin is also provided with a half etching groove.
Wherein the height of the control pins on the control chip is 30-200 mu m.
The frame pins connected with the D pole of the GaN chip and the frame pins connected with the control pins of the control chip are respectively positioned on two adjacent side surfaces of the packaging structure.
The beneficial effects of the invention are as follows: according to the packaging structure of the GaN chip, the novel 3D stacking structure is adopted, the control pins on the control chip are led out in a copper column mode, then the control chip is arranged on the frame pins and the GaN chip in a flip-chip mode, a plurality of control pins on the control chip are respectively and directly welded and fixed with the G pole of the GaN chip, the frame base island and the frame pins, and particularly the communication distance between the control pins on the control chip and the G pole of the GaN chip is greatly shortened, the conductive area of the copper column is large, the generated self-inductance is extremely small, and the influence on the switching speed of the GaN chip is greatly reduced, so that the GaN chip can fully exert the efficacy.
Drawings
FIG. 1 is a front view of a GaN chip according to the invention;
FIG. 2 is a top view of a GaN chip package structure of the related art;
FIG. 3 is a top view of a GaN chip package structure according to an embodiment of the invention;
FIG. 4 is a schematic step section view of section A-A of FIG. 3;
FIG. 5 is a schematic cross-sectional view of a GaN chip attached to a frame island by adhesive in accordance with a first embodiment of the invention;
FIG. 6 is a schematic cross-sectional view of a first embodiment of the present invention after bonding;
FIG. 7 is a schematic cross-sectional view of a control chip flip-chip bonded to a frame lead and a GaN chip in accordance with a first embodiment of the invention;
FIG. 8 is a schematic cross-sectional view of a first embodiment of the present invention after plastic encapsulation;
FIG. 9 is a schematic cross-sectional view of a GaN chip package structure according to a second embodiment of the invention;
Fig. 10 is a schematic cross-sectional view of a GaN chip package structure according to a third embodiment of the invention.
Wherein, 1, a frame base island; 11. a groove; 12. a sinking platform; 2. frame pins; 21. a half etching groove; 3. a GaN chip; 4. a control chip; 41. a control pin; 5. a plastic package body; 6. welding wires; 7. and (5) sticking glue.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
As shown in fig. 3 to 8, the first embodiment of the package structure of the GaN chip of the present invention includes a frame base 1, a frame lead 2, a GaN chip 3, a control chip 4, and a plastic package body 5, where the plastic package body 5 is used to plastic package the frame base 1, the frame lead 2, the GaN chip 3, and the control chip 4, the GaN chip 3 is a field effect transistor and includes a G pole, an S pole, and a D pole, the GaN chip 3 is being mounted and fixed on the frame base 1, the S pole of the GaN chip 3 is electrically connected with the frame base 1 through a bonding wire 6, the D pole of the GaN chip 3 is connected with the frame lead 2 through a bonding wire 6, the control lead 41 on the control chip 4 is led out in a copper pillar manner, the control chip 4 is flip-chip arranged on the frame lead 2 and the GaN chip 3, and the plurality of control leads 41 on the control chip 4 are respectively and directly welded and fixed with the G pole of the GaN chip 3, the frame base 1, and the frame lead 2.
In the first embodiment, the GaN chip 3 is fixed on the frame base 1 by the adhesive 7, and the adhesive 7 may be silver adhesive, or other fixing methods may be used.
In the first embodiment, the bottom of the inner side end of the frame pin 2 is further provided with a half etching groove 21. The half etching groove 21 and the plastic package body 5 form an embedded structure, so that the binding force between the frame pins 2 and the plastic package body 5 can be improved.
The packaging structure of the GaN chip adopts an innovative 3D stacking structure, firstly leads out the control pins 41 on the control chip 4 in a copper column mode, then inversely mounts the control chip 4 on the frame pins 2 and the GaN chip 3, and a plurality of control pins 41 on the control chip 4 are respectively and directly welded and fixed with the G pole of the GaN chip 3, the frame base island 1 and the frame pins 2, especially the communication distance between the control pins 41 on the control chip 4 and the G pole of the GaN chip 3 is greatly shortened, the conductive area of the copper column is large, the generated self-inductance is extremely small, and the influence on the switching speed of the GaN chip 3 is greatly reduced, so that the GaN chip 3 fully plays a role.
The packaging technology of the packaging structure of the GaN chip comprises the following steps:
s1, referring to FIG. 4, coating adhesive 7 on the frame base island 1;
s2, referring to FIG. 5, placing the GaN chip 3 on the adhesive 7, and fixing the GaN chip 3 on the frame base island 1;
s3, referring to FIG. 6, wire bonding is performed, wherein an S electrode of the GaN chip 3 is electrically connected with the frame base island 1 by using the bonding wires 6, and a D electrode of the GaN chip 3 is connected with the frame pin 2;
S4, referring to FIG. 7, the control chip 4 is arranged on the frame pin 2 and the GaN chip 3 in a flip-chip manner, and is welded by adopting tin-silver alloy;
S5, referring to FIG. 8, plastic packaging is performed, and the frame base island 1, the frame pins 2, the GaN chip 3 and the control chip 4 are wrapped by using a plastic packaging body 5 to form protection.
In the first embodiment, the height of the control pin 41 (copper pillar) on the control chip 4 is 30-200 μm, preferably 30-90 μm, which is 3% -9% of the length of the bonding wire in the background technical scheme, and the connection distance between the control pin 41 on the control chip 4 and the G pole of the GaN chip 3 is almost minimized.
In the first embodiment, the frame pins 2 connected to the D-pole of the GaN chip 3 and the frame pins 2 connected to the control pins 41 of the control chip 4 are located on two sides adjacent to the package structure, respectively. The scheme can reduce the size of the packaging structure, is beneficial to miniaturization of terminal equipment, reduces the packaging size from 6 x 5mm to 5.2 x 5mm in the background technology, and reduces the area by more than 10%.
In the first embodiment, the control chip 4 and the GaN chip 3 are arranged in a 3D stack and are parallel to each other. If the control chip 4 is inclined, the position is easy to move during welding, so that the circuit is abnormal, and when the control chip 4 and the GaN chip 3 are parallel to each other, the occurrence of the circuit abnormality can be reduced, and the yield is improved. Thus, in the first embodiment, the groove 11 is formed on the frame base island 1, the GaN chip 3 is fixedly arranged in the groove 11, the upper surface of the GaN chip 3 is flush with the upper surfaces of the frame base island 1 and the frame pins 2, and the heights of the plurality of control pins 41 on the control chip 4 are the same. Ideally, the depth of the groove 11=the thickness of the adhesive 7+the thickness of the GaN chip 3, and the allowable tolerance range is ±30 μm, so that the upper surface of the GaN chip 3, the upper surface of the frame base island 1 and the upper surface of the frame pin 2 can be well ensured to be in the same horizontal plane, the inclination of the control chip 4 is avoided, and the occurrence of abnormal circuit is reduced.
In the first embodiment, the groove 11 may be formed by removing a material by machining, or by removing a material by laser machining, or by etching.
As shown in fig. 9, the second embodiment of the package structure of the GaN chip of the present invention is different from the first embodiment in that the middle part of the frame base 1 is bent downward to form the sinking table 12, the GaN chip 3 is fixedly disposed in the sinking table 12, the upper surface of the GaN chip 3 is flush with the upper surfaces of the frame base 1 and the frame pins 2, the outer ends of the frame pins 2 are also bent downward, the lower surface of the frame pins 2 is flush with the lower surface of the frame base 1, and the heights of the plurality of control pins 41 on the control chip 4 are the same.
The purpose of processing the sinking table 12 in the second embodiment is to ensure that the upper surface of the GaN chip 3, the upper surface of the frame base 1 and the upper surface of the frame pins 2 are in the same horizontal plane, so as to avoid the inclination of the control chip 4 and reduce the occurrence of abnormal circuit. Ideally, the depth of the sinking table 12=the thickness of the glue 7+the thickness of the GaN chip 3, and the allowable tolerance range is ±30 μm, so that the tilting of the control chip 4 can be well avoided.
The outer side ends of the frame pins 2 are also bent downwards, so that the lower surfaces of the frame pins 2 are flush with the lower surface of the frame base island 1, and after plastic packaging, the plastic packaging body can be exposed at the same time, so that the electric connection with an external circuit is realized conveniently.
As shown in fig. 10, the third embodiment of the package structure of the GaN chip according to the present invention is different from the first embodiment in that neither the recess 11 nor the sink 12 is provided on the frame base 1. The upper surface of the frame base island 1 is flush with the upper surface of the frame pin 2, the height of the control pin 41 connected with the frame base island 1 on the control chip 4 is A, the height of the control pin 41 connected with the frame pin 2 on the control chip 4 is B, and the height of the control pin 41 connected with the G pole of the GaN chip 3 on the control chip 4 is C, wherein A=B > C. Adopt high low copper post complex technical scheme, through shortening the height of control pin 41 that is connected with the G utmost point of GaN chip 3 on the control chip 4 for control chip 4 is parallel to each other with GaN chip 3, avoids control chip 4 slope. Ideally, a-c=thickness of adhesive 7+thickness of GaN chip 3, with an allowable tolerance range of ±30 μm, to better avoid tilting control chip 4.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (9)
1. The utility model provides a packaging structure of GaN chip, includes frame base island, frame pin, gaN chip, control chip and plastic package body, the plastic package body is used for plastic package frame base island, frame pin, gaN chip and control chip, the GaN chip is field effect transistor, including G utmost point, S utmost point and D utmost point, the positive dress of GaN chip is fixed on frame base island, the S utmost point of GaN chip passes through the bonding wire and is connected with frame base island electricity, the D utmost point of GaN chip passes through the bonding wire and is connected with frame pin, its characterized in that, control pin on the control chip draws with the mode of copper post, control chip flip-chip sets up on frame pin and GaN chip, a plurality of control pins on the control chip are fixed with the G utmost point of GaN chip, frame base island and frame pin direct welding respectively; the control chip and the GaN chip are arranged in a 3D lamination mode and are parallel to each other, the upper position and the lower position of the control chip are partially overlapped and partially offset.
2. The package structure of the GaN chip of claim 1, wherein the frame base island is provided with a groove, the GaN chip is fixedly arranged in the groove, the upper surface of the GaN chip is flush with the upper surfaces of the frame base island and the frame pins, and the heights of the plurality of control pins on the control chip are the same.
3. The GaN chip packaging structure of claim 2, wherein said groove is made by removing material by machining, or by removing material by laser machining, or by etching.
4. The GaN chip packaging structure of claim 1, wherein the middle part of the frame base is bent downwards to form a sinking table, the GaN chip is fixedly arranged in the sinking table, the upper surface of the GaN chip is flush with the upper surfaces of the frame base and the frame pins, the outer ends of the frame pins are also bent downwards, the lower surfaces of the frame pins are flush with the lower surface of the frame base, and the heights of the plurality of control pins on the control chip are the same.
5. The GaN chip packaging structure of claim 1, wherein the upper surface of the frame base island is flush with the upper surface of the frame lead, the height of the control lead connected to the frame base island on the control chip is a, the height of the control lead connected to the frame lead on the control chip is B, and the height of the control lead connected to the G pole of the GaN chip on the control chip is C, wherein a=b > C.
6. The GaN chip package of claim 1, wherein said GaN chip is fixed to the frame base by adhesive.
7. The GaN chip of claim 1, wherein the bottom of the inner side of the frame pin is further provided with a half etching groove.
8. The GaN chip packaging structure of claim 1, wherein the height of the control pins on the control chip is 30-200 μm.
9. The GaN chip package structure of claim 1, wherein the frame pins connected to the D-pole of the GaN chip and the frame pins connected to the control pins of the control chip are located on two sides of the package structure, respectively, adjacent to each other.
Priority Applications (1)
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