CN216774744U - Control circuit - Google Patents
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- CN216774744U CN216774744U CN202220027872.7U CN202220027872U CN216774744U CN 216774744 U CN216774744 U CN 216774744U CN 202220027872 U CN202220027872 U CN 202220027872U CN 216774744 U CN216774744 U CN 216774744U
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Abstract
An embodiment of the present invention provides a control circuit, including: the control circuit of the main board and the control circuit of at least one slave board; the control circuit of the mainboard comprises a metal oxide semiconductor field effect transistor, a first bipolar transistor, a first micro-processing unit, a second micro-processing unit and a first power supply; the control circuit of the at least one slave board comprises at least one capacitor; wherein: the grid electrode of the metal oxide semiconductor field effect transistor is connected with the output end of the first microprocessing unit, and the source electrode and the drain electrode of the metal oxide semiconductor field effect transistor are connected between the first power supply and the output end of the control circuit of the mainboard; the base electrode of the first bipolar transistor is connected with the output end of the second microprocessing unit, and the emitter electrode and the collector electrode of the first bipolar transistor are connected between the first power supply and the output end of the control circuit of the mainboard; at least one capacitor is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit.
Description
Technical Field
The present invention relates to a control circuit.
Background
With the development of electronic technology, the current circuit design is generally a modular design, i.e. circuits with different functions are separated, so that the dependence on each other is reduced, and the independence and maintainability of each electric control board are improved. The master control board can be used for controlling the slave board, and when certain function needs to be realized, the master control board only needs to be controlled to supply power to the corresponding slave board, so that the power consumption in the circuit can be effectively reduced. At present, a relay is generally arranged in a main control board, and the power supply to a slave board is controlled by controlling the attraction of the relay, but the method is suitable for a circuit with larger current, and for a circuit with smaller current, the cost of the circuit is higher by adopting the relay; meanwhile, the relay is switched on and off based on the coil, namely, current needs to be applied to the relay, so that consumed electric quantity is large, and the size of the relay is large. In summary, in a circuit with a small control current, how to reduce power consumption and cost of the control circuit and miniaturize the control circuit is an urgent technical problem to be solved.
Disclosure of Invention
The utility model mainly provides a control circuit.
The utility model mainly provides a control circuit, which comprises a control circuit of a mainboard and a control circuit of at least one slave board; the control circuit of the mainboard comprises a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a first Bipolar Junction Transistor (BJT), a first micro-processing unit, a second micro-processing unit and a first power supply; the control circuit of the at least one slave board comprises at least one capacitor; wherein:
the grid electrode of the MOSFET is connected with the output end of the first microprocessing unit, and the source electrode and the drain electrode of the MOSFET are connected between the first power supply and the output end of the control circuit of the mainboard;
the base electrode of the first BJT is connected with the output end of the second micro-processing unit, and the emitter electrode and the collector electrode of the first BJT are connected between the first power supply and the output end of the control circuit of the mainboard;
the at least one capacitor is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit.
In one implementation, in the case where the MOSFET is of a P-channel type, a source of the MOSFET is connected to an output terminal of a control circuit of the motherboard, and a drain of the MOSFET is connected to the first power supply;
in the case where the MOSFET is of an N-channel type, a drain of the MOSFET is connected to an output terminal of a control circuit of the main board, and a source of the MOSFET is connected to the first power supply.
In one implementation, the control circuit of the motherboard further includes a first resistor; wherein:
in the case where the MOSFET is of a P-channel type, the first resistor is connected between a gate and a drain of the MOSFET;
in the case where the MOSFET is of an N-channel type, the first resistor is connected between a gate and a source of the MOSFET.
In one implementation, the control circuit of the motherboard further includes a second BJT; wherein:
the base electrode of the second BJT is connected with the output end of the first microprocessing unit, the emitter electrode of the second BJT is grounded, and the collector electrode of the second BJT is connected with the grid electrode of the MOSFET.
In one implementation, the control circuit of the main board further includes a second resistor in the case where the MOSFET is of a P-channel type; wherein:
the second resistor is connected between the collector of the second BJT and the gate of the MOSFET.
In one implementation manner, in a case that the first BJT is a PNP type, an emitter of the first BJT is connected to the first power supply, and a collector of the first BJT is connected to an output terminal of a control circuit of the main board;
and when the first BJT is of an NPN type, the collector of the first BJT is connected with the first power supply, and the emitter of the first BJT is connected with the output end of a control circuit of the mainboard.
In one implementation, the control circuit of the motherboard further includes a third resistor; wherein:
under the condition that the first BJT is of a PNP type, the third resistor is connected between the collector of the first BJT and the output end of the control circuit of the main control board;
and when the first BJT is of an NPN type, the third resistor is connected between an emitter of the first BJT and an output end of a control circuit of the main control board.
In one implementation, the control circuit of the motherboard further includes a third BJT; wherein:
the base electrode of the third BJT is connected with the output end of the second microprocessing unit, the emitter electrode of the third BJT is grounded, and the collector electrode of the third BJT is connected with the base electrode of the first BJT.
In one implementation, in a case that the first BJT is a PNP type, the control circuit of the main board further includes a fourth resistor; wherein:
the fourth resistor is connected between the collector of the third BJT and the base of the first BJT.
In one implementation, the control circuit further includes a Transient Voltage Suppressor (TVS); wherein:
the positive pole ground connection of TVS, the negative pole of TVS connects the output of the control circuit of main control board.
In the control circuit provided by the utility model, the control circuit comprises a control circuit of a mainboard and a control circuit of at least one slave board; the control circuit of the mainboard comprises a MOSFET, a first BJT, a first micro-processing unit, a second micro-processing unit and a first power supply; the control circuit of the at least one slave board comprises at least one capacitor; wherein: the grid electrode of the MOSFET is connected with the output end of the first microprocessing unit, and the source electrode and the drain electrode of the MOSFET are connected between the first power supply and the output end of the control circuit of the mainboard; the base electrode of the first BJT is connected with the output end of the second micro-processing unit, and the emitter electrode and the collector electrode of the first BJT are connected between the first power supply and the output end of the control circuit of the mainboard; the at least one capacitor is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit.
According to the utility model, the MOSFET and the first BJT are arranged on the control circuit of the mainboard, the control end of the MOSFET is connected with the output end of the first micro-processing unit, the control end of the first BJT is connected with the output end of the second micro-processing unit, and when the MOSFET and the first BJT receive driving signals, the control circuit of the mainboard is controlled to be switched on or switched off, so that the control circuit of at least one slave board is controlled to be powered. Therefore, the utility model realizes the on-off of the control circuit of the control mainboard by adopting the MOSFET and the first BJT, can effectively reduce the cost and the power consumption of the control circuit, and simultaneously, the first BJT can adopt the BJT with the patch, the BJT with the patch has smaller volume, can save a large space, and can miniaturize the control circuit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the utility model, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the utility model and, together with the description, serve to explain the principles of the utility model.
FIG. 1 is a schematic circuit diagram of a control circuit according to the related art;
fig. 2 is a schematic circuit diagram of a control circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a control circuit of a motherboard according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a working flow of a control circuit according to an embodiment of the present invention.
Detailed Description
In the related art, the current circuit design is generally in a modular design, when a plurality of electric control boards are jointly controlled, the master control board controls whether to supply power to the slave boards, and the control method can effectively reduce the power consumption in the circuit. In the related technical scheme, the power supply to the slave board is generally realized by controlling the pull-in of the relay, but the method is suitable for a circuit with larger current, and for a circuit for controlling small current, the cost of the control circuit is higher and the volume of the relay is larger by adopting the relay. In this case, how to reduce the power consumption and cost of the control circuit and miniaturize the control circuit is an urgent technical problem to be solved.
In the related art, a MOSFET may be used instead of the relay, and the power supply to the slave board is realized by controlling the on or off state of the MOSFET, as shown in fig. 1, the control circuit includes a control circuit of the host board and a control circuit of the slave board, where the control circuit of the host board includes: the first power supply VDD1 and the MOSFET Q1, the control circuit of the slave board comprises: a first capacitor E1, a second capacitor E2 and a third capacitor E3.
The source electrode of the MOSFET Q1 is connected with the output end of the control circuit of the mainboard, the drain electrode of the MOSFET Q1 is connected with the first power supply VDD1, and the grid electrode of the MOSFET Q1 can be connected with a driving device for controlling the on or off of the MOSFET; the first capacitor E1 is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit, the second capacitor E2 is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit, and the third capacitor E3 is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit.
When the MOSFET Q1 is turned on, the control circuit of the motherboard can supply power to the control circuit of the slave board, and it should be noted that, while the MOSFET Q1 is turned on, the control circuit of the motherboard charges the capacitor of the control circuit of the slave board, but when the number of capacitors connected in parallel in the control circuit of the slave board is large, the capacity of the whole capacitor is large, and a pulse with a large current flows through the MOSFET Q1 at the instant when the MOSFET Q1 is turned on, thereby damaging the MOSFET Q1.
In view of the above technical problems, the technical solutions of the embodiments of the present invention are provided. The embodiments of the present invention will be described in further detail below with reference to the drawings and the embodiments. It should be understood that the examples provided herein are merely illustrative of the present invention and are not intended to limit the present invention. In addition, the following embodiments are provided as partial embodiments for implementing the present invention, not all embodiments for implementing the present invention, and the technical solutions described in the embodiments of the present invention may be implemented in any combination without conflict.
It should be noted that, in the embodiments of the present invention, the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a method or apparatus including a series of elements includes not only the explicitly recited elements, but also other elements not explicitly listed, or includes inherent elements for implementing the method or apparatus. Without further limitation, the use of the phrase "including a. -. said." does not exclude the presence of other elements (e.g., steps in a method or elements in a device, such as portions of circuitry, processors, programs, software, etc.) in the method or device in which the element is included.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.
For example, although a control circuit provided in an embodiment of the present invention includes a series of circuits, the control circuit provided in an embodiment of the present invention is not limited to include explicitly described circuits, and may include circuits that are required to acquire related information or perform processing based on information.
The embodiment of the utility model provides a control circuit which controls the connection or disconnection of the control circuit.
The control circuit provided by the embodiment of the utility model can comprise: the control circuit of the main board and the control circuit of at least one slave board; the control circuit of the mainboard comprises a MOSFET, a first BJT, a first micro-processing unit, a second micro-processing unit and a first power supply; the control circuit of the at least one slave board comprises at least one capacitor; wherein:
the grid electrode of the MOSFET is connected with the output end of the first microprocessing unit, and the source electrode and the drain electrode of the MOSFET are connected between the first power supply and the output end of the control circuit of the mainboard;
the base electrode of the first BJT is connected with the output end of the second microprocessing unit, and the emitter electrode and the collector electrode of the first BJT are connected between the first power supply and the output end of the control circuit of the mainboard;
at least one capacitor is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit.
In an embodiment of the present invention, the motherboard control circuit is configured to control power supply to the control circuit of the at least one slave board, where the control circuit of the at least one slave board is configured to perform a certain function.
Illustratively, in one control circuit, the control circuit includes a control circuit of the main board, a control circuit of the first slave board, and a control circuit of the second slave board. When the mainboard is in a standby state, the control circuit of the mainboard stops supplying power to the control circuit of the first slave board and the control circuit of the second slave board; when the mainboard returns to the normal working state, the control circuit of the mainboard starts to supply power to the control circuit of the first slave board and the control circuit of the second slave board.
In the embodiment of the utility model, the MOSFET is a voltage control device, a semiconductor device for controlling the current of an output loop based on the electric field effect of a control input loop, has the characteristics of high switching speed, high input impedance, small driving power, small conduction loss, excellent stability and the like, and is commonly used as a switching device. The MOSFET has a Gate (Gate, G pole), a Source (Source, S pole), and a Drain (Drain, D pole), and thus, the current can be controlled according to the voltage of the Gate, thereby controlling the on or off state of the Source and the Drain.
In the embodiments of the present invention, P-channel MOSFETs and N-channel MOSFETs may be classified according to the type of carriers operating in the MOSFETs, where P denotes Positive (Positive) electrodes, i.e., Positive holes are carriers participating in conduction in the P-channel MOSFETs, and N denotes Negative (Negative) electrodes, i.e., Negative electrons are carriers participating in conduction in the N-channel MOSFETs.
In some embodiments, in the case of a MOSFET of the P-channel type, the source of the MOSFET is connected to the output of the control circuit of the motherboard and the drain of the MOSFET is connected to the first power supply;
in the case where the MOSFET is of an N-channel type, a drain of the MOSFET is connected to an output terminal of a control circuit of the main board, and a source of the MOSFET is connected to the first power supply.
In the embodiment of the present invention, the MOSFET may be a P-channel MOSFET or an N-channel MOSFET, and the embodiment of the present invention is not limited thereto. For an N-channel MOSFET, under the condition that the grid voltage is greater than the source voltage, the source and the drain are conducted, namely the MOSFET is in a conducting state; for a P-channel MOSFET, the source and drain are conducting, i.e. the MOSFET is in a conducting state, in case the gate voltage is smaller than the source voltage.
In the embodiment of the utility model, the BJT is a current control device, and compared with the MOSFET, the BJT has the advantages of small volume, light weight, low power consumption, long service life and high reliability, and is commonly used for amplifying signals and used as a switching device. The BJT has a Base (Base, B), an Emitter (Emitter, E), and a Collector (Collector, C), and can control the on/off of the Emitter and the Collector according to the current of the Base.
In the embodiment of the present invention, the BJT is a device that combines two PN junctions together through a certain process, and it should be noted that, by adopting different doping processes and based on diffusion, the P-type semiconductor and the N-type semiconductor are fabricated on the same semiconductor (usually silicon or germanium) substrate, and a space charge region is formed at an interface between them as a PN junction, so that electrons and holes in the BJT can participate in conduction at the same time. The semiconductor device can be divided into PNP and NPN combined structures according to different combination modes of the P-type semiconductor and the N-type semiconductor.
In some embodiments, in the case that the first BJT is a PNP type, an emitter of the first BJT is connected to a first power supply, and a collector of the first BJT is connected to an output terminal of a control circuit of the main board;
and under the condition that the first BJT is of an NPN type, the collector of the first BJT is connected with a first power supply, and the emitter of the first BJT is connected with the output end of a control circuit of the mainboard.
In the embodiment of the present invention, the first BJT may be an NPN type or a PNP type, and the embodiment of the present invention is not limited thereto, and for the NPN type BJT, when the base receives the high level signal, the BJT is in an on state, and when the base receives the low level signal, the BJT is in an off state; for a PNP type BJT, when the base receives a low level signal, the BJT is in a conducting state, and when the base receives a high level signal, the BJT is in a non-conducting state.
Illustratively, the MOSFET is a P-channel MOSFET, and the first BJT is a PNP type, as shown in fig. 2, the control circuit includes a control circuit of a host board and a control circuit of a slave board, wherein the control circuit of the host board includes: MOSFET Q1, first BJT Q2, third resistance R3 and first power VDD1, the control circuit of the slave board includes: a first capacitor E1, a second capacitor E2 and a third capacitor E3.
The source of the MOSFET Q1 is connected with the output end of the control circuit of the main board, the drain of the MOSFET Q1 is connected with the first power supply VDD1, the emitter of the first BJT Q2 is connected with the first power supply VDD1, the collector of the first BJT Q2 is connected with the output end of the control circuit of the main board, and the third resistor R3 is connected between the collector of the first BJT Q2 and the output end of the control circuit of the main control board.
The first capacitor E1 is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit, the second capacitor E2 is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit, and the third capacitor E3 is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit.
In the embodiment of the utility model, the first micro-processing unit is used for sending a driving signal to the grid electrode of the MOSFET so as to control the on or off of the MOSFET; the second micro-processing unit is used for sending a driving signal to the base of the BJT so as to control the BJT to be switched on or switched off, wherein the driving signal comprises a high-level signal and a low-level signal.
Illustratively, in the case where the MOSFET is a P-channel MOSFET and the first BJT is a PNP type, the MOSFET and the first BJT are in an on state when the first and second micro-processing units transmit a low level signal, and the MOSFET and the first BJT are in an off state when the first and second micro-processing units transmit a high level signal.
In an embodiment of the present invention, the capacitor is a component for storing electric energy and electric energy, and at least one capacitor may supply power to the load in the slave board during the conduction of the first BJT.
It can be seen that, in the embodiment of the present invention, the MOSFET and the first BJT are arranged in the control circuit of the motherboard, the control terminal of the MOSFET is connected to the output terminal of the first microprocessor unit, the control terminal of the first BJT is connected to the output terminal of the second microprocessor unit, the MOSFET can be controlled to be turned on or off according to the driving signal sent by the first microprocessor unit, the first BJT is controlled to be turned on or off according to the driving signal sent by the second microprocessor unit, so as to control the control circuit of the motherboard to be turned on or off, and thus, the power supply to the control circuit of at least one slave board is controlled. Therefore, the utility model realizes the on-off of the control circuit of the control mainboard by adopting the MOSFET and the first BJT, can effectively reduce the cost and the power consumption of the control circuit, and simultaneously, the first BJT can adopt the BJT with a patch, can effectively reduce the volume of electronic components in the circuit and miniaturize the control circuit.
In some embodiments, the control circuit of the motherboard further comprises a first resistor; wherein:
in the case where the MOSFET is of a P-channel type, the first resistor is connected between a gate and a drain of the MOSFET;
in the case where the MOSFET is of an N-channel type, the first resistor is connected between the gate and the source of the MOSFET.
In the embodiment of the utility model, the first resistor is used for stabilizing the level signal, and when the grid of the MOSFET does not receive the driving signal, the grid is in a stable level state, so that the MOSFET is ensured to be in a cut-off state.
In some embodiments, the control circuit of the main board further comprises a second BJT; wherein:
the base electrode of the second BJT is connected with the output end of the first microprocessing unit, the emitter electrode of the second BJT is grounded, and the collector electrode of the second BJT is connected with the grid electrode of the MOSFET.
In the embodiment of the utility model, the second BJT is used for amplifying the driving signal sent by the first micro-processing unit, so as to prevent the MOSFET from being turned on due to insufficient driving capability of the first micro-processing unit. It should be noted that the second BJT may be an NPN type or a PNP type, and the embodiment of the present invention is not limited thereto, and only the NPN type BJT is taken as an example for description.
In the embodiment of the utility model, the base of the second BJT receives the driving signal sent by the first microprocessing unit, and under the condition that the driving signal is a high-level signal, the second BJT is in a conducting state, and the collector of the second BJT sends the high-level signal to the grid of the MOSFET; and under the condition that the driving signal is a low-level signal, the second BJT is in an off state, and the driving signal sent by the first micro-processing unit cannot be sent to the MOSFET.
In some embodiments, in the case where the MOSFET is of a P-channel type, the control circuit of the main board further includes a second resistor; wherein:
the second resistor is connected between the collector of the second BJT and the gate of the MOSFET.
In the embodiment of the present invention, when the MOSFET is of a P-channel type, the MOSFET is in an on state when the gate of the MOSFET receives a low level signal, and therefore, the second resistor is used to limit the current of the circuit between the collector of the second BJT and the gate of the MOSFET. When the driving signal sent by the first microprocessing unit is a high-level signal, the base of the second BJT receives the high-level signal, the second BJT is in a conducting state, the collector of the second BJT sends out the high-level signal, the current is limited by the second resistor, the grid of the MOSFET receives the low-level signal, and the MOSFET is in a conducting state; when the driving signal sent by the first micro-processing unit is a low-level signal, the base of the second BJT receives the low-level signal, the second BJT is in an off state, the second BJT cannot send the driving signal to the MOSFET, and the MOSFET is in the off state.
In some embodiments, the control circuit of the motherboard further comprises a third resistor; wherein:
under the condition that the first BJT is of a PNP type, the third resistor is connected between the collector of the first BJT and the output end of the control circuit of the main control panel;
and when the first BJT is of an NPN type, the third resistor is connected between the emitter of the first BJT and the output end of the control circuit of the main control panel.
In the embodiment of the utility model, the third resistor is used for limiting the current of the circuit between the first BJT and the output end of the control circuit of the main control board, so as to prevent the current in the circuit from being too large. When the first BJT is in an on state, the control circuit of the master control board may charge the capacitor in the control circuit of the at least one slave board, and limit the current through the third resistor, that is, the capacitor in the control circuit of the at least one slave board is charged through a small current, so that the electric quantity in the capacitor is small, and the first BJT and the MOSFET can be prevented from being damaged.
In some embodiments, the control circuit of the main board further includes a third BJT; wherein:
and the base electrode of the third BJT is connected with the output end of the second microprocessing unit, the emitter electrode of the third BJT is grounded, and the collector electrode of the third BJT is connected with the base electrode of the first BJT.
In an embodiment of the utility model, the third BJT is used for amplifying the driving signal sent by the second micro-processing unit, so as to prevent the driving capability of the second micro-processing unit from being insufficient, and the first BJT cannot be turned on. It should be noted that the third BJT may be an NPN type or a PNP type, and the embodiment of the present invention is not limited thereto, and only the NPN type BJT is taken as an example for description.
In the embodiment of the utility model, the base of the third BJT receives the driving signal sent by the second microprocessor unit, and when the driving signal is a high-level signal, the third BJT is in a conducting state, and the collector of the second BJT sends the high-level signal to the base of the first BJT; and under the condition that the driving signal is a low-level signal, the third BJT is in an off state, and the driving signal sent by the second micro-processing unit cannot be sent to the first BJT.
In some embodiments, in the case that the first BJT is a PNP type, the control circuit of the main board further includes a fourth resistor; wherein:
the fourth resistor is connected between the collector of the third BJT and the base of the first BJT.
In an embodiment of the present invention, when the first BJT is a PNP type, the first BJT is turned on when the base of the first BJT receives a low level signal, and therefore the fourth resistor is used to limit a current flowing through a circuit between the collector of the third BJT and the base of the first BJT. When the driving signal sent by the second microprocessing unit is a high-level signal, the base of the third BJT receives the high-level signal, the third BJT is in a conducting state, the collector of the third BJT sends out the high-level signal, the current is limited by the fourth resistor, the base of the first BJT receives the low-level signal, and the first BJT is in the conducting state; when the driving signal sent by the second micro-processing unit is a low-level signal, the base of the third BJT receives the low-level signal, the third BJT is in an off state, the third BJT cannot send the driving signal to the first BJT, and the first BJT is in the off state.
In some embodiments, the control circuit further comprises a TVS; wherein:
the positive pole ground connection of TVS, the output of the control circuit of main control board is connected to the negative pole of TVS.
In the embodiment of the utility model, the TVS is a high-efficiency protection device realized based on a diode, and has the advantages of short response time, large transient power, low leakage current, breakdown voltage deviation, easier control of clamping voltage, no damage limit, small size and the like.
In the embodiment of the utility model, when the control circuit works normally, the TVS is in a cut-off state, the normal work of the control circuit is not influenced, when abnormal overvoltage exists in the control circuit, the TVS is rapidly changed from the cut-off state to a conducting state, a low-impedance conducting path is provided for instantaneous current in the control circuit, and meanwhile, the abnormal high voltage is clamped within a safety level, so that the control circuit is protected, and when the abnormal overvoltage disappears, the TVS is changed from the conducting state to the cut-off state, and the control circuit works normally.
Fig. 3 is a schematic circuit diagram of a control circuit of a motherboard according to an embodiment of the present invention, as shown in fig. 3, the control circuit of the motherboard includes a MOSFET Q1, a first BJT Q2, a second BJT Q3, a third BJT Q4, a first micro-processing unit MCU1, a second micro-processing unit MCU2, a first power VDD1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a TVS D1, where Q1 is a P-channel MOSFET, Q2 is a PNP-type BJT, Q3 is an NPN-type BJT, and Q4 is an NPN-type BJT.
In the embodiment of the utility model, one end of a fifth resistor R5 is connected with the output end of the first microprocessing unit MCU1, the base of a second BJT Q3 is connected with the other end of the fifth resistor R5, the emitter of the second BJT Q3 is grounded, the collector of the second BJT Q3 is connected with one end of the second resistor R2, the gate of a MOSFET Q1 is connected with the other end of the second resistor R2, the source of the MOSFET Q1 is connected with the output end of a control circuit of a motherboard, the drain of the MOSFET Q1 is connected with a first power supply VDD1, and the first resistor R1 is connected between the source and the drain of the MOSFET Q1.
In the embodiment of the present invention, one end of a sixth resistor R6 is connected to an output end of the second MCU2, a base of a third BJT Q4 is connected to the other end of the sixth resistor R6, an emitter of the third BJT Q4 is grounded, a collector of the third BJT Q4 is connected to one end of the fourth resistor R4, a base of the first BJT Q2 is connected to the other end of the fourth resistor R4, an emitter of the first BJT Q2 is connected to the first power VDD1, one end of the third resistor R3 is connected to a collector of the first BJT Q2, and one end of the third resistor R3 is connected to an output end of a control circuit of the motherboard.
In the embodiment of the utility model, one end of the seventh resistor R7 is connected to the common end of the bases of the sixth resistor R6 and the second BJT Q3, the other end of the seventh resistor R7 is connected to the anode of the TVS D1, and the cathode of the TVS D1 is connected to the output end of the control circuit of the motherboard.
In the embodiment of the present invention, when the second MCU2 sends a high level signal, the base of the third BJT Q4 receives the high level signal, the third BJT Q4 is in a conducting state, and is limited by the fourth resistor R4, the base of the second BJT Q2 receives a low level signal, the second BJT Q2 is in a conducting state, and is limited by the third resistor R3, the control circuit of the main board is in a conducting state, and at least one capacitor in the slave board can be charged; when the second MCU2 sends a low level signal, the base of the third BJT Q4 receives the low level signal, the third BJT Q4 is turned off, and the second BJT Q2 is turned off, that is, the control circuit of the main board is turned off, when the drive signal cannot be sent to the second BJT Q2.
In the embodiment of the utility model, when the first microprocessing unit MCU1 sends out a high level signal, the base of the second BJT Q3 receives the high level signal, the second BJT Q3 is in a conducting state, and the gate of the MOSFET Q1 receives a low level signal through the current limiting of the second resistor R2, so the MOSFET Q1 is in a conducting state, the control circuit of the motherboard is in a conducting state, and the power can be supplied to the slave board; when the first micro processing unit MCU1 sends a low level signal, the base of the second BJT Q3 receives the low level signal, the second BJT Q3 is turned off, and the driving signal cannot be sent to the MOSFET Q1, so the MOSFET Q1 is turned off, that is, the control circuit of the main board is turned off.
In the embodiment of the utility model, when the control circuit of the mainboard works normally, the TVS D1 is in a cut-off state; when abnormal overvoltage exists in the control circuit, the TVS D1 is switched from the off state to the on state, providing a low impedance conduction path for the instantaneous current in the control circuit of the motherboard while clamping the abnormal high voltage within a safe level, and when the abnormal overvoltage disappears, the TVS D1 is switched from the on state to the off state.
Based on the technical concept of the control circuit in fig. 3, an embodiment of the present invention further provides a work flow of the control circuit, and fig. 4 is a schematic view of the work flow of the control circuit provided in the embodiment of the present invention, where the work flow may include:
step 401: it is determined whether the motherboard is in a standby state, if yes, step 402 is executed, and if no, step 403 is executed.
In the embodiment of the present invention, when the operating state of the main board is the standby state, the operating state of the at least one slave board is also the standby state, that is, the control circuit of the main board does not need to supply power to the control circuit of the at least one slave board.
Step 402: the first micro-processing unit sends a low level signal to control the MOSFET to be in an off state, and the second micro-processing unit sends a low level signal to control the first BJT to be in an off state, and step 401 is executed.
In the embodiment of the utility model, the first microprocessing unit sends a low-level signal, the base of the second BJT receives the low-level signal, the second BJT is in a cut-off state, and the MOSFET is in the cut-off state if the second BJT cannot send a driving signal to the MOSFET.
In an embodiment of the present invention, the second micro processing unit sends a low level signal, and if the base of the third BJT receives the low level signal, the third BJT is turned off, and if the third BJT cannot send the driving signal to the first BJT, the first BJT is turned off.
Step 403: the second microprocessing unit sends a high level signal to control the first BJT to be in a conducting state.
In the embodiment of the utility model, the second microprocessing unit sends a high-level signal, the base of the third BJT receives the high-level signal, the third BJT is in a conducting state and is limited by the resistor, the base of the first BJT receives a low-level signal, the first BJT is in the conducting state, and the control circuit of the mainboard charges at least one capacitor in the control circuit of the slave board.
Step 404: tm delay is initiated.
In the embodiment of the utility model, the Tm starting delay represents Tm waiting time, and in the Tm time, the second micro-processing unit sends a high-level signal to control the first BJT to be in a conducting state.
In the embodiment of the utility model, the second microprocessing unit sends a high-level signal to control the first BJT to be in a conducting state and charge at least one capacitor in the control circuit of the slave board, so that the phenomenon that the MOSFET is damaged due to the fact that a pulse with large current is transmitted to the MOSFET at the moment when the MOSFET is conducted due to the fact that the electric quantity in the at least one capacitor is too large is prevented.
In an embodiment of the present invention, Tm is a turn-on time of the first BJT, and Tm can be obtained by solving an equation Tm ═ R × C × Ln [ (V)dd-Vset-V0)/(Vdd-Vset-Vt)]It is noted that R is the resistance of the third resistor, C is the capacitance of the slave plate capacitor, and VddVset is the saturation voltage drop of the first BJT, V0Is the initial voltage of the control circuit of the slave board, VtIs the voltage at time t from the board control circuit.
Step 405: and judging whether the Tm delay is finished, if so, executing step 406, and if not, executing step 405.
In the embodiment of the present invention, if the Tm delay is ended, it indicates that the control circuit of the motherboard has completed charging at least one capacitor in the control circuit of the slave board.
Step 406: the second micro-processing unit sends a low level signal to control the first BJT to be in an off state, the first micro-processing unit sends a high level signal to control the MOSFET to be in an on state, and step 401 is executed.
In the embodiment of the utility model, after the control circuit of the main board charges at least one capacitor in the control circuit of the slave board, the first micro-processing unit sends a high-level signal, the base of the second BJT receives the high-level signal, the second BJT is in a conducting state, the current is limited by the resistor, the grid of the MOSFET receives a low-level signal, the MOSFET is in the conducting state, the control circuit of the main board supplies power to the control circuit of the slave board, and the working state of the slave board is normal.
The foregoing description of the various embodiments is intended to highlight different sites among the various embodiments, and that the same or similar sites may be referred to one another, which are not repeated herein for brevity.
Features disclosed in various product embodiments provided by the application can be combined arbitrarily to obtain new product embodiments without conflict.
Features disclosed in the device embodiments provided in the present application may be combined arbitrarily without conflict to obtain new device embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. The above-described device embodiments are merely illustrative, and for example, the division of the unit is only one logical function division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication between the components shown or discussed may be through some interfaces, and the indirect coupling or communication between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of grid units; some or all of the units can be selected according to actual conditions to achieve the purpose of the scheme of the embodiment.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (10)
1. The control circuit is characterized by comprising a control circuit of a main board and a control circuit of at least one slave board; the control circuit of the mainboard comprises a metal oxide semiconductor field effect transistor, a first bipolar transistor, a first micro-processing unit, a second micro-processing unit and a first power supply; the control circuit of the at least one slave board comprises at least one capacitor; wherein:
the grid electrode of the metal oxide semiconductor field effect transistor is connected with the output end of the first microprocessing unit, and the source electrode and the drain electrode of the metal oxide semiconductor field effect transistor are connected between the first power supply and the output end of the control circuit of the mainboard;
the base electrode of the first bipolar transistor is connected with the output end of the second micro-processing unit, and the emitter electrode and the collector electrode of the first bipolar transistor are connected between the first power supply and the output end of the control circuit of the mainboard;
the at least one capacitor is connected between the output end of the mainboard control circuit and the grounding end of the mainboard control circuit.
2. The circuit of claim 1, wherein in the case of the mosfet being of the P-channel type, the source of the mosfet is connected to the output of the control circuit of the motherboard, and the drain of the mosfet is connected to the first power supply;
in the case where the mosfet is of an N-channel type, a drain of the mosfet is connected to an output terminal of a control circuit of the motherboard, and a source of the mosfet is connected to the first power supply.
3. The circuit of claim 2, wherein the control circuit of the motherboard further comprises a first resistor; wherein:
in the case where the metal oxide semiconductor field effect transistor is of a P-channel type, the first resistor is connected between a gate and a drain of the metal oxide semiconductor field effect transistor;
in a case where the metal oxide semiconductor field effect transistor is of an N-channel type, the first resistor is connected between a gate and a source of the metal oxide semiconductor field effect transistor.
4. The circuit of claim 2, wherein the control circuit of the motherboard further comprises a second bipolar transistor; wherein:
the base electrode of the second bipolar transistor is connected with the output end of the first microprocessing unit, the emitter electrode of the second bipolar transistor is grounded, and the collector electrode of the second bipolar transistor is connected with the grid electrode of the metal oxide semiconductor field effect transistor.
5. The circuit of claim 4, wherein in the case where the MOSFET is of a P-channel type, the control circuit of the motherboard further comprises a second resistor; wherein:
the second resistor is connected between the collector of the second bipolar transistor and the gate of the metal oxide semiconductor field effect transistor.
6. The circuit of claim 1, wherein in a case where the first bipolar transistor is a PNP type, an emitter of the first bipolar transistor is connected to the first power supply, and a collector of the first bipolar transistor is connected to an output terminal of a control circuit of the main board;
when the first bipolar transistor is an NPN transistor, a collector of the first bipolar transistor is connected to the first power supply, and an emitter of the first bipolar transistor is connected to an output terminal of a control circuit of the motherboard.
7. The circuit of claim 6, wherein the control circuit of the motherboard further comprises a third resistor; wherein:
under the condition that the first bipolar transistor is a PNP type, the third resistor is connected between the collector of the first bipolar transistor and the output end of the control circuit of the mainboard;
in a case where the first bipolar transistor is an NPN type, the third resistor is connected between an emitter of the first bipolar transistor and an output terminal of the control circuit of the main board.
8. The circuit of claim 6, wherein the control circuit of the motherboard further comprises a third bipolar transistor; wherein:
the base electrode of the third bipolar transistor is connected with the output end of the second micro-processing unit, the emitter electrode of the third bipolar transistor is grounded, and the collector electrode of the third bipolar transistor is connected with the base electrode of the first bipolar transistor.
9. The circuit of claim 8, wherein the control circuit of the main board further comprises a fourth resistor in case the first bipolar transistor is PNP type; wherein:
the fourth resistor is connected between the collector of the third bipolar transistor and the base of the first bipolar transistor.
10. The circuit of claim 1, wherein the control circuit further comprises a transient suppression diode; wherein:
the anode of the transient suppression diode is grounded, and the cathode of the transient suppression diode is connected with the output end of the control circuit of the mainboard.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220027872.7U CN216774744U (en) | 2022-01-04 | 2022-01-04 | Control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202220027872.7U CN216774744U (en) | 2022-01-04 | 2022-01-04 | Control circuit |
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| Publication Number | Publication Date |
|---|---|
| CN216774744U true CN216774744U (en) | 2022-06-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202220027872.7U Active CN216774744U (en) | 2022-01-04 | 2022-01-04 | Control circuit |
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| Country | Link |
|---|---|
| CN (1) | CN216774744U (en) |
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2022
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