CN216673023U

CN216673023U - High-reliability communication protocol module of MLVDS bus

Info

Publication number: CN216673023U
Application number: CN202123263108.4U
Authority: CN
Inventors: 杨庆; 宋浩; 许春福
Original assignee: Jiangsu Lingyue Electronic Technology Co ltd
Current assignee: Jiangsu Lingyue Electronic Technology Co ltd
Priority date: 2021-12-23
Filing date: 2021-12-23
Publication date: 2022-06-03
Anticipated expiration: 2031-12-23

Abstract

The utility model discloses a high-reliability communication protocol module of an MLVDS bus, which comprises an SPI interface module, a clock management module, a memory management module, a logic scheduling module, a frame copying module, a frame eliminating module, a coding and decoding module and an electrical interface module, wherein the SPI interface module provides a configuration interface of a protocol, and a user configures parameters of the protocol through the interface, and sends data to be communicated to the protocol and receives the data; the clock management module receives an external input clock, consists of a PLL (phase locked loop) and provides clock signals required by each module in a protocol; the memory management module provides a data caching function and a reading and writing function for the memory. The utility model adopts Manchester II coding, has the functions of double-channel redundancy, various data check, error processing, interruption generation and data caching, greatly improves the reliability of MLVDS communication, expands the application scene of MLVDS and has great market prospect.

Description

High-reliability communication protocol module of MLVDS bus

Technical Field

The utility model relates to the technical field of communication, in particular to a high-reliability communication protocol module of an MLVDS bus.

Background

The MLVDS (multi-point low voltage differential signaling) bus is a high-speed system bus oriented to multi-node application, and gradually replaces the RS485 bus due to the advantages of high communication rate, low power consumption, strong anti-interference capability, long transmission distance (the maximum distance can reach 40m), simple network topology structure (bus type topology structure) and the like, and is widely applied to the industrial field. In recent years, the application of MLVDS to construct a system-level bus for command and data transmission in the military field is increasing.

The military field requires the system-level communication bus to have very high reliability, including dual-channel redundancy, error handling mechanism, low bit error rate and the like. The MLVDS protocol only standardizes the network structure and the electrical characteristics, and when the MLVDS protocol is applied to the military field, the MLVDS protocol can ensure the high reliability only by matching with a communication protocol.

At present, many MLVDS users cannot meet requirements of dual-channel redundancy, an error handling mechanism, a low bit error rate and the like of a military system bus when the MLVDS bus is in communication due to lack of technical capability of customizing a high-reliability communication protocol, and other more complex communication buses are searched instead, so that higher use cost and longer research and development period are caused.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the problem that requirements of dual-channel redundancy, an error processing mechanism, a low bit error rate and the like of a military system bus cannot be met when a plurality of MLVDS users communicate with an MLVDS bus due to the lack of technical capability of customizing a high-reliability communication protocol in the prior art, and provides a high-reliability communication protocol module of an MLVDS bus.

In order to achieve the purpose, the utility model adopts the following technical scheme:

a high-reliability communication protocol module of an MLVDS bus comprises an SPI interface module, a clock management module, a memory management module, a logic scheduling module, a frame copying module, a frame eliminating module, a coding and decoding module and an electrical interface module, wherein the SPI interface module provides a configuration interface of a protocol, and a user configures parameters of the protocol through the interface, sends data to be communicated to the protocol and receives the data;

the clock management module receives an external input clock, consists of a PLL (phase locked loop) and provides clock signals required by each module in a protocol;

the memory management module provides a data caching function and a read-write function for the memory;

the logic scheduling module provides a unified scheduling function of each module, coordinates orderly operation of each module for a control core of the protocol, and generates interruption;

the frame copying module provides a redundancy function when the bus transmits data, and copies the data of one channel to another channel for transmission;

the frame elimination module provides a data inspection function and a fault processing function during data receiving, wherein the data inspection function is specifically to receive and inspect data of two channels simultaneously, and the inspection contents comprise verification, inspection and consistency inspection;

the coding and decoding module provides coding function and decoding function;

the electrical interface module implements electrical connections to the MLVDS signals, including TX, RX, and enable signals.

Preferably, the clock management module has an external input clock signal of 100MHz, a codec clock of 400MHz, and a clock of each of the other modules is 100 MHz.

Preferably, the memory management module provides a caching function of 1024 KB.

Preferably, the logic scheduling module adopts a state machine structure.

Preferably, the encoding function of the encoding and decoding module includes the contents of both data bit encoding and frame format.

Preferably, the check sum in the frame elimination module is a protocol for comparing the received data with the check sum byte in the data frame, if the received data is consistent with the check sum byte, the check sum is correct, and the correctness of the received data is ensured; the consistency check is to check A, B whether the data of the channel are consistent, and if so, keep the data in cache.

Preferably, the data bit encoding employs manchester type II encoding to encode the data bits, with the falling edge representing a high level 1 and the rising edge representing a low level 0.

Preferably, the protocol reads signals from the MLVDS transceiver and starts collecting data into the receiver when a sync header conforming to the definition is identified.

Has the beneficial effects that:

the utility model adopts Manchester II coding, has the functions of double-channel redundancy, various data check, error processing, interrupt generation and data caching, greatly improves the reliability of MLVDS communication, expands the application scene of MLVDS and has great market prospect.

Drawings

Fig. 1 is a schematic structural diagram of a high-reliability communication protocol module of an MLVDS bus according to the present invention;

fig. 2 is a schematic diagram of an implementation process of a high-reliability communication protocol module of an MLVDS bus according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.

Referring to fig. 1-2, a high-reliability communication protocol module of an MLVDS bus includes an SPI interface module, a clock management module, a memory management module, a logic scheduling module, a frame copying module, a frame eliminating module, a coding and decoding module, and an electrical interface module, where the SPI interface module provides a configuration interface of a protocol, and a user configures parameters of the protocol through the interface, and sends data to be communicated to the protocol and receives the data;

the clock management module receives an external input clock, consists of a PLL (phase locked loop) and provides clock signals required by each module in a protocol, the external input clock signal of the clock management module is 100MHz, the coding and decoding clock is 400MHz, and the clocks of other modules are 100 MHz;

the memory management module provides a data caching function and a reading and writing function for the memory, and the caching function provided by the memory management module is 1024 KB;

the logic scheduling module provides a unified scheduling function of each module, is a control core of the protocol, coordinates orderly operation of each module and generates interruption, and adopts a state machine structure;

the frame elimination module provides a data checking function and a fault processing function when data are received, the data checking function is specifically to receive and check the data of two channels simultaneously, the checking content comprises checking, checking and consistency checking, the checking and the checking in the frame elimination module are that a protocol compares the received data with the check sum byte in the data frame, if the check sum is consistent, the checking is correct, and the correctness of the received data is ensured; the consistency check is to check A, B whether the data in the channels are consistent, if so, the data is kept to be cached;

the encoding function of the encoding and decoding module comprises data bit encoding and frame format contents, the data bit encoding adopts Manchester II type encoding to encode the data bits, the falling edge represents high level 1, the rising edge represents low level 0, the protocol reads signals from the MLVDS transceiver, and when the synchronization head conforming to the definition is identified, data acquisition is started to enter the receiver;

the frame format is composed of a synchronous head, an address, a command word, a length, data and a check bit, wherein the synchronous head adopts a Type 2 MLVDS transceiver, a bus outputs low level in open circuit, short circuit and idle states, in order to avoid the phenomenon, a protocol adopts high level of two continuous bytes and low level of two continuous bytes as synchronous heads, similar to a 1553 frame format, and the longest transmission of 256 bytes in the protocol can be limited;

the address field is added with a destination address field (1 byte), FF is broadcast, FO-FE is a multicast command, A0-AF is 1-to-1 communication, unicast; optionally a CRC8/CRC16 check. The introduction of the check bit is beneficial to improving the reliability of bus communication and provides a basis for the criterion of error frames;

In this embodiment, the implementation method of the communication protocol includes: the protocol is implemented in a hardware description language and runs in an FPGA (including but not limited to this method, encapsulating the utility model into an IP or custom ASIC chip.

In the embodiment, the chip comprises a CPU, an FPGA and an MLVDS chip, wherein the CPU adopts STM32 series, the FPGA adopts XC4VLX100, and the MLVDS chip adopts DS91C 176. If the number of MLVDS chips is 2, a dual-channel redundant network is constructed, a communication protocol runs in the FPGA, and an external input clock is 100 MHz; the CPU and the FPGA adopt SPI communication, and the CPU is used as an upper computer of a protocol and used for processing communication data.

The embodiment can realize the communication function of the MLVDS bus, has the speed of 100M, has a dual-channel redundancy function and very high reliability, and can be applied to military weaponry.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and equivalent alternatives or modifications according to the technical solution of the present invention and the inventive concept thereof should be covered by the scope of the present invention.

Claims

1. A high-reliability communication protocol module of an MLVDS bus comprises an SPI interface module, a clock management module, a memory management module, a logic scheduling module, a frame copying module, a frame eliminating module, a coding and decoding module and an electrical interface module, and is characterized in that:

the SPI interface module provides a configuration interface of a protocol, and a user configures parameters of the protocol through the interface, and sends data to be communicated to the protocol and receives the data;

the coding and decoding module provides coding function and decoding function;

2. The high-reliability communication protocol module of the MLVDS bus of claim 1, wherein: the clock management module has 100MHz external input clock signal, 400MHz coding and decoding clock, and 100MHz clock of other modules.

3. The high-reliability communication protocol module of the MLVDS bus of claim 1, wherein: the memory management module provides a caching function of 1024 KB.

4. The high-reliability communication protocol module of the MLVDS bus of claim 1, wherein: the logic scheduling module adopts a state machine structure.

5. The high-reliability communication protocol module of the MLVDS bus of claim 1, wherein: the coding function of the coding and decoding module comprises the contents of two aspects of data bit coding and frame format.

6. The high-reliability communication protocol module of the MLVDS bus of claim 1, wherein: the check and check in the frame elimination module are that a protocol compares the received data with the check sum byte in the data frame, if the check and check are consistent, the check is correct, and the correctness of the received data is ensured; the consistency check is to check A, B whether the data of the channel are consistent, and if so, keep the data in cache.

7. The high-reliability communication protocol module of the MLVDS bus of claim 5, wherein: the data bit encoding employs manchester type II encoding to encode the data bit, with the falling edge representing a high level 1 and the rising edge representing a low level 0.

8. The high-reliability communication protocol module of the MLVDS bus of claim 5, wherein: the protocol reads signals from the MLVDS transceiver and when a sync header is identified that meets the definition, starts collecting data into the receiver.