CN216597594U - Fast recovery plane gate super junction power device - Google Patents
Fast recovery plane gate super junction power device Download PDFInfo
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- CN216597594U CN216597594U CN202123266352.6U CN202123266352U CN216597594U CN 216597594 U CN216597594 U CN 216597594U CN 202123266352 U CN202123266352 U CN 202123266352U CN 216597594 U CN216597594 U CN 216597594U
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Abstract
The utility model relates to a restore plane bars soon and surpass knot power device, including first conductive type substrate, epitaxial layer, source region, first, second conductive type post, second conductive type district, first, second oxidation layer, first, the conductive polycrystalline silicon of second, source electrode metal, insulating medium layer, second, first through-hole. In the longitudinal direction, the first through hole and the second through hole are arranged at intervals; in the transverse direction, the two sides of the first through hole are both provided with first conductive polysilicon, and the source metal is in ohmic contact with the second conductive type body region and the first conductive type source region through the first through hole; one side of the second through hole is provided with first conductive polycrystalline silicon, the other side of the second through hole is provided with second conductive polycrystalline silicon, or both sides of the second through hole are provided with second conductive polycrystalline silicon, and the source metal is in ohmic contact with the first conductive type source region, the second conductive type body region and the polycrystalline silicon through the second through hole. The utility model discloses reduced reverse recovery energy loss, reduced the technology degree of difficulty, saved manufacturing cost.
Description
Technical Field
The utility model relates to a power semiconductor structure, specifically speaking are fast resume plane bars and surpass knot power device.
Background
A super-junction metal oxide semiconductor field effect transistor (SJ MOSFET for short) has a parasitic diode connected in parallel with it, the anode of the parasitic diode is connected to the source of the SJ MOSFET, and the cathode is connected to the drain of the SJ MOSFET, so that the SJ MOSFET also serves to freewheel. The parasitic diode is conducted by minority carriers as a common diode, so that the parasitic diode has reverse recovery time and reverse recovery loss.
Because the schottky diode has the advantages of lower forward diode voltage drop and the like, the diode recovery time of the switching action of the device is often improved, and the power loss of a non-switching part of the device during operation can be restrained.
Disclosure of Invention
The utility model aims at overcoming the not enough of existence among the prior art, provide one kind can reduce chip cost and encapsulation cost, reduce reverse recovery energy loss and reduce the quick recovery plane bars of the technology degree of difficulty and surpass knot power device.
According to the technical scheme provided by the utility model, the fast recovery plane gate super junction power device comprises a first conductive type substrate, a first conductive type epitaxial layer is arranged above the first conductive type substrate, a first conductive type column and a second conductive type column which are arranged at intervals are arranged at the top of the first conductive type epitaxial layer, a second conductive type body area is arranged at the top of the second conductive type column, a first conductive type source area is arranged on the surface of the middle part of the second conductive type body area, a first oxide layer and a second oxide layer are arranged above the first conductive type column, the second conductive type body area and the first conductive type source area, a first conductive polycrystalline silicon is arranged above the first oxide layer, the first conductive polycrystalline silicon is connected with a grid electrode potential, a second conductive polycrystalline silicon is arranged above the second oxide layer, the second conductive polycrystalline silicon is connected with a source electrode potential, an insulating medium layer is arranged above the first conductive polycrystalline silicon and the second conductive polycrystalline silicon, the first conductive polysilicon and the second conductive polysilicon are insulated by an insulating medium layer, source metal is arranged above the insulating medium layer, and the source metal is in ohmic contact with the second conductive type body region, the first conductive type source region and the second conductive polysilicon through the first through hole and the second through hole;
overlooking the device, wherein the first through hole and the second through hole are arranged at intervals and connected in the direction parallel to the second conductive type column;
in a direction perpendicular to the length direction of the second conductive type column, both sides of the first through hole are made of first conductive polysilicon, and the source metal is in ohmic contact with the second conductive type body region and the first conductive type source region through the first through hole; one side of the second through hole is provided with first conductive polysilicon, and the other side of the second through hole is provided with second conductive polysilicon, or both sides of the second through hole are provided with the second conductive polysilicon, and the source metal is in ohmic contact with the second conductive type body region, the first conductive type source region and the second conductive polysilicon through the second through hole.
Preferably, the thickness of the second oxide layer is smaller than that of the first oxide layer.
Preferably, the second oxide layer has a thickness of 50A-500A.
Preferably, the first oxide layer has a thickness of 500A-2000A.
Preferably, the first oxide layer, the second oxide layer and the insulating medium layer are all made of silicon dioxide or silicon nitride.
Preferably, when the power device is an N-type power device, the first conductivity type is an N-type, and the second conductivity type is a P-type; or, when the power device is a P-type power device, the first conductivity type is a P-type, and the second conductivity type is an N-type.
The utility model discloses reduced reverse recovery energy loss, reduced the technology degree of difficulty, saved manufacturing cost.
Drawings
Fig. 1 is a schematic top view of a contact hole and a trench of a chip according to embodiment 1 of the present invention.
Fig. 2 is a schematic view of a top view structure of a contact hole and a trench of a chip provided in embodiment 2 of the present invention.
Fig. 3 is a schematic sectional view taken along a broken line AA' in fig. 1.
Fig. 4 is a schematic sectional view taken along a dashed line BB' in fig. 1.
Fig. 5 is a schematic cross-sectional view taken along a dotted line CC' in fig. 1.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings. In which like parts are designated by like reference numerals. It should be noted that the words "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings. The terms "inner" and "outer" are used to refer to directions toward and away from, respectively, the geometric center of a particular component.
The utility model discloses a following two kinds of embodiments all explain with N type power semiconductor device as an example, and wherein, first conductivity type substrate 1, first conductivity type epitaxial layer 2, first conductivity type post 3 and first conductivity type source region 6 are the N type, and second conductivity type post 4 and second conductivity type body region 5 are the P type.
Example 1
A fast recovery planar gate super junction power device is disclosed, as shown in FIG. 1, FIG. 3-FIG. 5, comprising a first conductive type substrate 1, a first conductive type epitaxial layer 2 is disposed above the first conductive type substrate 1, a first conductive type column 3 and a second conductive type column 4 are disposed at an interval on the top of the first conductive type epitaxial layer 2, a second conductive type body region 5 is disposed on the top of the second conductive type column 4, a first conductive type source region 6 is disposed on the surface of the middle portion of the second conductive type body region 5, a first oxide layer 8 and a second oxide layer 10 are disposed above the first conductive type column 3, the second conductive type body region 5 and the first conductive type source region 6, a first conductive polysilicon 7 is disposed above the first oxide layer 8, the first conductive polysilicon 7 is connected to a gate potential, a second conductive polysilicon 9 is disposed above the second oxide layer 10, the second conductive polysilicon 9 is connected with a source electrode potential, an insulating medium layer 12 is arranged above the first conductive polysilicon 7 and the second conductive polysilicon 9, the first conductive polysilicon 7 and the second conductive polysilicon 9 are insulated through the insulating medium layer 12, a source electrode metal 11 is arranged above the insulating medium layer 12, and the source electrode metal 11 is in ohmic contact with the second conductive type body region 5, the first conductive type source region 6 and the second conductive polysilicon 9 through a first through hole 14 and a second through hole 13;
looking down the device, the first through holes 14 and the second through holes 13 are arranged at intervals and connected in a direction parallel to the second conductive type pillars 4 (i.e., in the up-down direction of fig. 1);
looking down the device, in a direction perpendicular to the second conductive type pillar 4 (i.e., in the left-right direction of fig. 1), both sides of the first via hole 14 are the first conductive polysilicon 7, and the source metal 11 is in ohmic contact with the second conductive type body region 5 and the first conductive type source region 6 through the first via hole 14; the first conductive polysilicon 7 is disposed on one side of the second via 13, the second conductive polysilicon 9 is disposed on the other side, and the source metal 11 is in ohmic contact with the second conductive type body region 5, the first conductive type source region 6, and the second conductive polysilicon 9 through the second via 13.
The thickness of the second oxide layer 10 is smaller than that of the first oxide layer 8; the thickness of the second oxide layer 10 is 200 a; the first oxide layer 8 has a thickness of 800 a.
The first oxide layer 8, the second oxide layer 10 and the insulating medium layer 12 are all made of silicon dioxide or silicon nitride.
Example 2
A fast recovery planar gate super junction power device is disclosed, as shown in FIG. 2, comprising a first conductive type substrate 1, a first conductive type epitaxial layer 2 disposed on the first conductive type substrate 1, a first conductive type column 3 and a second conductive type column 4 disposed at an interval on top of the first conductive type epitaxial layer 2, a second conductive type body region 5 disposed on top of the second conductive type column 4, a first conductive type source region 6 disposed on the surface of the middle portion of the second conductive type body region 5, a first oxide layer 8 and a second oxide layer 10 disposed on the first conductive type column 3, the second conductive type body region 5 and the first conductive type source region 6, a first conductive polysilicon 7 disposed on the first oxide layer 8, the first conductive polysilicon 7 connected to a gate potential, a second conductive polysilicon 9 disposed on the second oxide layer 10, the second conductive polysilicon 9 connected to a source potential, an insulating medium layer 12 is arranged above the first conductive polysilicon 7 and the second conductive polysilicon 9, the first conductive polysilicon 7 and the second conductive polysilicon 9 are insulated through the insulating medium layer 12, a source metal 11 is arranged above the insulating medium layer 12, and the source metal 11 is in ohmic contact with the second conductive type body region 5, the first conductive type source region 6 and the second conductive polysilicon 9 through a first through hole 14 and a second through hole 13;
looking down the device, the first through holes 14 and the second through holes 13 are arranged at intervals in a direction parallel to the second conductive type pillars 4 (i.e., in the up-down direction of fig. 2);
looking down the device, in a direction perpendicular to the second conductive type pillar 4 (i.e., in the up-down direction of fig. 2), both sides of the first via hole 14 are the first conductive polysilicon 7, and the source metal 11 is in ohmic contact with the second conductive type body region 5 and the first conductive type source region 6 through the first via hole 14; both sides of the second via hole 13 are made of second conductive polysilicon 9, and the source metal 11 is in ohmic contact with the second conductive type body region 5, the first conductive type source region 6, and the second conductive polysilicon 9 through the second via hole 13.
The thickness of the second oxide layer 10 is smaller than that of the first oxide layer 8; the thickness of the second oxide layer 10 is 200 a; the first oxide layer 8 has a thickness of 800 a.
The first oxide layer 8, the second oxide layer 10 and the insulating medium layer 12 are all made of silicon dioxide or silicon nitride.
In the utility model, the source electrode metal 11, the first conductive type source region 6, the first oxide layer 8, the first conductive polysilicon 7, the second conductive type body region 5 and the first conductive type column 3 form a traditional MOSFET structure; the source electrode metal 11, the first conductive type source region 6, the second oxide layer 10, the second conductive polysilicon 9, the second conductive type body region 5 and the first conductive type column 3 in the utility model form a fast recovery diode structure; the utility model provides a source electrode metal 11, second conductivity type district 5, second conductivity type post 4 and first conductivity type post 3 have constituted traditional PN diode structure.
When the device is used as a freewheeling diode, the first conductive polysilicon 7 is connected with the source metal 11, when the freewheeling diode is in a voltage-resistant state, the source metal 11 is connected with a low potential, the first conductive type substrate 1 is connected with a high potential, and no current passes through the freewheeling diode;
when the freewheel diode is shifted from the withstand voltage state to the freewheel state, the first conductivity type substrate 1 is gradually changed from the high potential to the low potential, the source metal 11 is gradually shifted from the low potential to the high potential, since the second oxide layer 10 is much thinner than the first oxide layer 8, when the potential difference between the second conductive type body region 5 and the top region of the first conductive type pillar 3 reaches about 0.3V, an electron accumulation layer is formed in the second conductive type body region 5 under the second oxide layer 10 of the fast recovery diode structure, electrons enter the electron accumulation layer through the first conductive type column 3, the substrate 1 of the first conduction type is rapidly changed from high potential to low potential at the moment, the device enters a small current follow current state, and the generated reverse recovery energy loss is small because the current at the moment is small;
when the potential difference between the second conductive type body region 5 and the top region of the first conductive type column 3 reaches about 0.7V, the conventional PN diode structure described above is gradually turned on and the current reaches the maximum, and at this time, since the first conductive type substrate 1 is already at a low potential, even if the current is large, the energy loss generated is small.
If the utility model discloses do not have fast recovery diode structure, when the potential difference between second conductivity type district 5 and the 3 top regions of first conductivity type post reached about 0.7V, first conductivity type substrate 1 just can become the low potential from the high potential, and the electric current reaches the biggest rapidly, because the state of 1 high potential of first conductivity type substrate and heavy current afterflow that exists a period of time, the reverse recovery energy loss that produces this moment is great.
Those of ordinary skill in the art will understand that: the above description is only for the specific embodiments of the present invention, and is not intended to limit the present invention, and any modifications, equivalent replacements, improvements, etc. made within the spirit of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The utility model provides a fast recovery plane gate surpasses knot power device, includes first conductivity type substrate (1), be equipped with first conductivity type epitaxial layer (2) above first conductivity type substrate (1), be equipped with first conductivity type post (3) and second conductivity type post (4) that the interval set up at the top of first conductivity type epitaxial layer (2), be equipped with second conductivity type district (5) at the top of second conductivity type post (4), the surface at the middle part in second conductivity type district (5) is equipped with first conductivity type source region (6), characterized by:
a first oxide layer (8) and a second oxide layer (10) are arranged above the first conductive type column (3), the second conductive type body region (5) and the first conductive type source region (6), a first conductive polysilicon (7) is arranged above the first oxide layer (8), the first conductive polysilicon (7) is connected with a grid potential, a second conductive polysilicon (9) is arranged above the second oxide layer (10), the second conductive polysilicon (9) is connected with a source potential, an insulating medium layer (12) is arranged above the first conductive polysilicon (7) and the second conductive polysilicon (9), the first conductive polysilicon (7) and the second conductive polysilicon (9) are insulated through the insulating medium layer (12), a source metal (11) is arranged above the insulating medium layer (12), and the source metal (11) is connected with the second conductive type body region (5) through a first through hole (14), a second through hole (13), A first conductive type source region (6) and a second conductive polysilicon (9) are in ohmic contact;
the first through holes (14) and the second through holes (13) are arranged at intervals and connected in a direction parallel to the length direction of the second conductive type column (4);
looking down the device, in the direction vertical to the second conductive type column (4), both sides of the first through hole (14) are first conductive polysilicon (7), and the source metal (11) is in ohmic contact with the second conductive type body region (5) and the first conductive type source region (6) through the first through hole (14); one side of the second through hole (13) is provided with first conductive polysilicon (7), and the other side is provided with second conductive polysilicon (9), or both sides of the second through hole (13) are provided with the second conductive polysilicon (9), and the source metal (11) is in ohmic contact with the second conductive type body region (5), the first conductive type source region (6) and the second conductive polysilicon (9) through the second through hole (13).
2. The fast recovery planar gate superjunction power device of claim 1, wherein: the thickness of the second oxide layer (10) is smaller than that of the first oxide layer (8).
3. The fast recovery planar gate superjunction power device of claim 2, wherein: the thickness of the second oxide layer (10) is 50A-500A.
4. The fast recovery planar gate superjunction power device of claim 2, wherein: the thickness of the first oxide layer (8) is 500A-2000A.
5. The fast recovery planar gate superjunction power device of claim 1, wherein: the first oxide layer (8), the second oxide layer (10) and the insulating medium layer (12) are all made of silicon dioxide or silicon nitride.
6. The fast recovery planar gate superjunction power device of claim 1, wherein: when the power device is an N-type power device, the first conduction type is an N type, and the second conduction type is a P type; or, when the power device is a P-type power device, the first conductivity type is a P-type, and the second conductivity type is an N-type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123266352.6U CN216597594U (en) | 2021-12-23 | 2021-12-23 | Fast recovery plane gate super junction power device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123266352.6U CN216597594U (en) | 2021-12-23 | 2021-12-23 | Fast recovery plane gate super junction power device |
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| CN216597594U true CN216597594U (en) | 2022-05-24 |
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| CN202123266352.6U Active CN216597594U (en) | 2021-12-23 | 2021-12-23 | Fast recovery plane gate super junction power device |
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