CN216597578U

CN216597578U - ESD MOS tube layout structure

Info

Publication number: CN216597578U
Application number: CN202123180690.8U
Authority: CN
Inventors: 唐毓尚; 石力强; 刘健; 彭俊; 周文质; 尹国平; 曾信幸; 杨菲菲
Original assignee: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
Current assignee: GUIZHOU ZHENHUA FENGGUANG SEMICONDUCTOR CO Ltd
Priority date: 2021-12-17
Filing date: 2021-12-17
Publication date: 2022-05-24
Anticipated expiration: 2031-12-17

Abstract

An ESD MOS tube layout structure belongs to the field of integrated circuits. The structure comprises 2 or more than 2 ESD sub-devices, wherein the ESD sub-devices share one chip bonding pad, the chip bonding pad is taken as a layout center, the ESD sub-devices symmetrically surround the periphery of the chip bonding pad to form a ring-shaped layout, and the specific shape of the ring is symmetrically adjusted according to the shape of the chip bonding pad. The method avoids the situation that each bonding pad needs to adopt ESD protection, thereby reducing the area of a chip layout, improving the electrostatic protection performance, simultaneously improving the space occupancy rate between the ESD device and the total area of the bonding pads, and achieving the purposes of improving the antistatic capacity of the ESD device and reducing the cost. The problems that the area of a chip is greatly increased and the cost is greatly increased while the antistatic capability of the chip is improved in the conventional ESD device are solved. The method is widely applied to the technical field of ESD devices.

Description

ESD MOS tube layout structure

Technical Field

The utility model belongs to the field of integrated circuits, and further relates to the field of integrated circuit layout design, in particular to a layout structure of an ESD electrostatic protection device.

Background

Integrated circuit products can develop charge buildup during manufacturing, testing, packaging, storage, and shipping. When a pin of a product is grounded, the current generated by the discharge of charges from the pin reaches the ampere level, the breakdown failure of a device can be caused by high voltage generated instantly under the condition without an ESD protection structure, and meanwhile, a large amount of heat is generated to enable silicon materials and aluminum near PAD to reach melting point mutual solubility, so that lattice mismatch is caused, and a metal connecting wire is broken. Eventually rendering the product useless. Therefore, the design of the electrostatic protection module in the chip design is directly related to the functional stability of the chip, and is very important. As shown in fig. 1, the pads of the conventional chip are located at two ends of the peripheral region of the pad by using the ESD protection devices, which occupies a large area, and the chip cost of the whole integrated circuit is high, especially for a circuit with a large number of pads, the area cost is greatly increased. On the other hand, the doping concentration and area of the P region and the N region of the ESD device determine the ESD protection capability, so the area of the ESD device is usually increased to obtain a larger ESD capability, but the cost burden is also increased. As the feature size of the manufacturing process of semiconductor integrated circuits is smaller and smaller, the size of chip units is also smaller and smaller, and the antistatic capability of chips becomes more and more important. The utility model is provided for reducing the area of a chip and reducing the cost budget on the premise of ensuring the performance of the chip as much as possible while improving the electrostatic protection capability.

Disclosure of Invention

The purpose of the utility model is: the problems that the chip area is greatly increased and the cost is greatly increased while the antistatic capacity of the chip is improved in the conventional ESD device are solved.

Therefore, the utility model provides an ESD MOS transistor layout structure, as shown in fig. 2. The ESD protection structure comprises a plurality of ESD sub-devices (2 or more), wherein the ESD sub-device chips symmetrically surround the periphery of a bonding pad, the plurality of ESD sub-devices share one bonding pad, the shape of the bonding pad of the chip can be flexibly designed as required, the bonding pad of the chip is used as a layout center for the layout structure design of the ESD device, the area utilization rate and the electrostatic protection capacity are greatly improved by adopting an annular design, and the specific annular shape can be adjusted by depending on the shape of the bonding pad. The ESD protection is avoided being adopted for each bonding pad, so that the chip layout area is reduced, the electrostatic protection performance is improved, meanwhile, the space occupancy rate between the ESD device and the total bonding pad area is improved, and the purposes of improving the antistatic capacity of the ESD device and reducing the cost are achieved.

The plane layout of the ESD structure can be made into a square annular structure or a circular annular structure with round corners at the periphery according to the shape of the bonding pad, wherein the bonding pad is positioned in the center of the layout, and the periphery of the bonding pad is surrounded by the ESD device. The ESD layout structure is a vertically and horizontally symmetrical structure. The fillet design that the domain adopted can be fine improves the peak electric field, the heavy current that static produced that can be better leaks.

Compared with the prior art, the utility model has the following advantages:

firstly, the utility model provides a layout structure of an annular symmetrical ESD device, the process is simple and compatible with the existing standard process, the utilization rate of space is greatly improved, and the annular structure is more beneficial to the discharge of large current. Secondly, the annular structure can avoid a peak electric field generated on the ESD device during electrostatic discharge, and the voltage withstanding property is better improved. The layout shape and size of the ESD device can be further improved according to the size and shape of the bonding pad of the chip and the ESD capability. If the bonding pad is square, the ESD device can be changed into a layout structure with round corners and squares. Has good pad conformability.

The technical scheme provided by the utility model is widely applied to the technical field of ESD devices.

Drawings

Fig. 1 is a schematic diagram of an ESD layout structure of a conventional ESD device.

Fig. 2 is a schematic diagram of a planar layout structure of the ESD device of the present invention.

Fig. 3 is a schematic diagram of a longitudinal cross-sectional structure of a MOS ESD device according to the present invention.

Fig. 4 is a schematic diagram of a layout structure of a circular ring-shaped layout of the MOS ESD device of the present invention.

FIG. 5 is a schematic diagram of a layout structure of a rounded square ring-shaped layout of the MOS type ESD device of the present invention.

In the figure: the structure comprises a P-type substrate P + diffusion region outer boundary, a P-type substrate P + diffusion region inner boundary, a NMOS source region N + diffusion region outer boundary, a NMOS transistor source region N + diffusion region inner boundary and a grid polycrystalline silicon grid outer boundary, a NMOS transistor polycrystalline silicon grid inner boundary and a drain region N + diffusion region outer boundary, a NMOS drain region N + diffusion region inner boundary, a PMOS drain region P + diffusion region outer boundary, a PMOS transistor drain region P + diffusion region inner boundary and a polycrystalline silicon grid outer boundary, a PMOS transistor polycrystalline silicon grid inner boundary and a source region P + diffusion region outer boundary, a PMOS transistor source region P + diffusion region inner boundary, a PMOS transistor source region P + diffusion region outer boundary, a PMOS drain region P + diffusion region outer boundary, a PMOS transistor drain region P + diffusion region outer boundary, a PMOS drain region P + diffusion region inner boundary and a polycrystalline silicon grid outer boundary, a PMOS transistor drain region P + diffusion region inner boundary and a PMOS transistor drain region P + diffusion region outer boundary, a PMOS transistor drain region P + diffusion region outer boundary and a PMOS transistor drain region inner boundary, a PMOS transistor drain region outer boundary and a PMOS transistor drain region outer boundary, a PMOS transistor drain region P + diffusion region outer boundary and PMOS transistor diffusion region outer boundary, a PMOS transistor drain region outer boundary, a PMOS transistor diffusion region outer boundary and PMOS transistor diffusion region outer boundary, a PMOS transistor diffusion region outer boundary, PMOS and PMOS transistor diffusion region outer boundary, PMOS transistor diffusion region outer boundary, PMOS transistor outer boundary, PMOS and PMOS transistor outer boundary, PMOS transistor outer boundary.

Detailed Description

With reference to fig. 3-5, the embodiment of the present invention is as follows:

specifically, the utility model provides a layout structure of a MOS type ESD device. The layout design of circular or square with round corners is adopted, and the MOS tube is surrounded around the bonding pad through the structure. The width-length ratio of the MOS tube grid can be greatly improved, so that the current discharge capacity is improved. And the structural configuration can adjust the sizes of the grid electrode, the source electrode and the drain electrode of the ESD device according to the required electrostatic protection requirement. Therefore, the high-voltage ESD device with good current discharge capacity, high width-to-length ratio and high space utilization rate is manufactured, and the cost of the current chip is reduced.

According to utility model ESD device territory structure includes: the semiconductor device comprises a semiconductor substrate, an N-type drift region, a P + diffusion region and an N + diffusion region. Fig. 3 is a longitudinal cross-sectional view of the structure of the novel ESD device according to the present embodiment, which is a left-right symmetric structure as a whole. The NMOS and the PMOS are arranged from outside to inside in sequence, and the center is a bonding pad area. The substrate potential and the grid electrode and the source electrode of the NMOS are grounded, the grid electrode and the source electrode of the N-well potential PMOS are connected with a positive power supply, and the drain electrodes of the NMOS and the PMOS are connected to a bonding pad. The improved ESD MOS device layout design is illustrated by the schematic below. The layout structure and implementation of the present invention shown and described in the drawings constitute at least one embodiment of the present invention and do not limit the spirit and scope of the appended claims to modifications.

Fig. 4 is a structural plan view structure diagram of the novel ESD device of this embodiment, the layout structure of the MOS ESD device includes: p-type substrate P + diffusion zone outer boundary 1, P-type substrate P + diffusion zone inner boundary 2, NMOS source zone N + diffusion zone outer boundary 3, NMOS transistor source zone N + diffusion zone inner boundary and gate polysilicon gate outer boundary 4, NMOS transistor polysilicon gate inner boundary and drain zone N + diffusion zone outer boundary 5, NMOS drain zone N + diffusion zone inner boundary 6, N-WELL diffusion zone outer boundary 7, PMOS drain zone P + diffusion zone outer boundary 8, PMOS transistor drain zone P + diffusion zone inner boundary and polysilicon gate outer boundary 9, PMOS transistor polysilicon gate inner boundary and source zone P + diffusion zone outer boundary 10, PMOS transistor source zone P + diffusion zone inner boundary 11, N-WELL N + diffusion zone outer boundary 12, N-WELL N + diffusion zone inner boundary 13, N-WELL N + diffusion zone inner boundary and pad boundary 14. The source region and the grid electrode of the PMOS are connected with the highest potential, the source region and the grid electrode of the NMOS are connected with the lowest potential, and the drain electrodes of the PMOS and the NMOS are connected to the bonding pad.

The layout structure of the MOS type ESD device comprises a P + diffusion region of an NMOS substrate → a source region N + diffusion region of an NMOS field region → a polysilicon gate region of the NMOS region → a drain region N + diffusion region of the NMOS field region → an NWELL diffusion region of the PMOS field region → a P + diffusion region of a PMOS drain region → a polysilicon gate region of the PMOS → a P + diffusion region of a PMOS source region → an N + diffusion region of an NWELL region → an NWELL boundary → a pad region in sequence from outside to inside. And adopting a layout of an N well to form a symmetrical PMOS device, and adopting an impurity region as a P type or adopting a layout of a P well to form a symmetrical NMOS device.

The drain electrode and the source electrode are different from a conventional MOS in design, an inner ring and outer ring symmetrical and alternative mode is adopted, the collection capacity of electric charges is enhanced, a drain electrode region and a source electrode region can be separated by adjusting a polysilicon gate region, the width-to-length ratio of a channel can be changed by changing the inner diameter and the outer diameter of a PMOS or NMOS gate ring, and therefore the large-current discharge capacity is improved.

The utility model is an ESD device layout structure design applied to the most widely adopted MOS process at present, and the area utilization rate and the electrostatic protection capability are greatly improved by adopting an annular design. The layout structure of the ESD device can be adjusted depending on the shape of the bonding pad.

The advantages are that:

firstly, the utility model provides a layout structure of an annular symmetrical MOS type ESD device, the process is simple and compatible with the existing standard MOS process, the utilization rate of space is greatly improved, and the annular structure is more beneficial to the discharge of large current. Secondly, the annular structure can avoid a peak electric field generated on the ESD device during electrostatic discharge, and the voltage withstanding property is better improved. The layout shape and size of the ESD device can be further improved according to the size and shape of the bonding pad of the chip and the ESD capability. As shown in fig. 5, if the bonding pad has a square shape, the ESD device can be changed into a layout structure with a round corner square. Has good pad conformability.

It is to be understood that the above implementation of the novel ESD device is not limited to the layout structure of the ESD device being a circular structure or a square structure with rounded corners. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the utility model without departing from the scope of the utility model. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims

1. An ESD MOS tube layout structure is characterized by comprising 2 or more than 2 ESD sub-devices, wherein the ESD sub-devices share one chip bonding pad, the chip bonding pad is taken as a layout center, the ESD sub-devices symmetrically surround the periphery of the chip bonding pad to form a ring-shaped layout, and the specific shape of the ring is symmetrically adjusted according to the shape of the chip bonding pad.

2. The ESD MOS transistor layout structure of claim 1, wherein the shape of the chip pad is designed as required.

3. The layout structure of the ESD MOS transistor according to claim 1, wherein the planar layout of the ESD MOS transistor is formed into a circular ring structure or a square ring structure with rounded corners according to the shape of the bonding pad.

4. The ESD MOS transistor layout structure of claim 1, wherein the MOS device layout structure of the ESD MOS transistor is an annular circular layout design or a square layout design with rounded corners, and the MOS transistor is surrounded around the bonding pad.

5. The ESD MOS transistor layout structure of claim 4, wherein the internal structure of the MOS ESD device comprises: the semiconductor device comprises a semiconductor substrate, an N-type drift region, a P + diffusion region and an N + diffusion region.

6. The ESD MOS transistor layout structure according to claim 4, wherein the MOS type ESD device has a bilateral symmetry structure along a longitudinal section structure; the NMOS and the PMOS are arranged from outside to inside in sequence, and the center is a bonding pad area.

7. The ESD MOS transistor layout structure of claim 4, wherein the MOS ESD device layout structure comprises: the outer boundary of a P + diffusion region of a P-type substrate, the inner boundary of a P + diffusion region of the P-type substrate, the outer boundary of an N + diffusion region of an NMOS source region, the inner boundary of an N + diffusion region of an NMOS transistor, the outer boundary of a grid polysilicon grid of the NMOS transistor, the outer boundary of an N + diffusion region of an NMOS drain region, the inner boundary of an N + diffusion region of an NMOS drain region, the outer boundary of an N-WELL diffusion region, the outer boundary of a P + diffusion region of a PMOS drain region, the inner boundary of a P + diffusion region of a PMOS transistor, the outer boundary of a P + diffusion region of a source region, the inner boundary of a P + diffusion region of a PMOS transistor, the outer boundary of an N + diffusion region of an N trap, the inner boundary of an N + diffusion region, and the boundary of a pad;

the MOS type ESD device layout structure sequentially comprises a P + diffusion region of an NMOS substrate → a source region N + diffusion region of an NMOS field region → a polysilicon gate region of an NMOS region → a drain region N + diffusion region of the NMOS field region → an NWELL diffusion region of the PMOS field region → a P + diffusion region of a PMOS drain region → a polysilicon gate region of a PMOS → a P + diffusion region of a PMOS source region → an N + diffusion region of an NWELL region → an NWELL boundary → a pad region from outside to inside, a layout of an N well is adopted to form a symmetrical PMOS device, and an impurity region is P type or a layout of a P well is adopted to form a symmetrical NMOS device.

8. The ESD MOS transistor layout structure of claim 7, wherein the source and gate of the PMOS are connected to the highest potential, the source and gate of the NMOS are connected to the lowest potential, and the drains of the PMOS and NMOS are connected to the pad.

9. The ESD MOS transistor layout structure of claim 7, wherein the drain and source of the MOS ESD device are designed in an inner-outer ring symmetric alternating manner by adjusting a polysilicon gate region to separate a drain region and a source region.

10. The ESD MOS transistor layout structure according to claim 4, wherein the drain and source of the MOS type ESD device are designed in a manner of symmetric alternation of inner and outer rings, and the width-to-length ratio of the channel is changed by changing the inner diameter and the outer diameter of the PMOS or NMOS gate ring.