CN111987094B - High voltage ESD structure - Google Patents
High voltage ESD structure Download PDFInfo
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- CN111987094B CN111987094B CN202011049234.7A CN202011049234A CN111987094B CN 111987094 B CN111987094 B CN 111987094B CN 202011049234 A CN202011049234 A CN 202011049234A CN 111987094 B CN111987094 B CN 111987094B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Abstract
The invention discloses a high-voltage ESD structure, which is a MOS tube structure with a planar layout in a round rectangle, wherein a drain region of the MOS tube structure is positioned in the center region of the round rectangle; dividing the rounded rectangle into a top rounded corner and a bottom rounded corner on a top plane; the arc-shaped area of the top fillet is provided with a heavily doped N-type area and a heavily doped P-type area which are parallel to each other and are in abutting contact; dividing the drain region into a top drain region and a bottom drain region, wherein the top drain region comprises a contact region, and the boundary of the active region is outside the contact region and is separated from the contact region by a distance; the bottom drain region comprises a heavily doped N-type injection region, and the width of the heavily doped N-type injection region is smaller than that of the active region; the drain region at the bottommost end is not provided with a contact hole, and the drain region close to the central region is provided with two rows of contact holes; in the bottom rounded region, the heavily doped N-type region is in abutting contact with the heavily doped P-type region, and the heavily doped N-type region overlaps with the boundary of the active region. The device structure of the invention can improve ESD capability.
Description
Technical Field
The present invention relates to the field of semiconductor device design and fabrication, and more particularly, to a high voltage ESD structure.
Background
Static electricity is an objective natural phenomenon, and various modes are generated, such as contact, friction, induction between electric appliances and the like. Static electricity is characterized by long-time accumulation, high voltage, low electric quantity, small current and short action time. Static electricity poses serious hazards in a number of fields. Friction electrification and human static electricity are two major hazards in the electronic industry, and often cause unstable operation and even damage of electronic and electric products.
As feature sizes of manufacturing processes of semiconductor integrated circuits are smaller, chip units are smaller, and antistatic capability of chips is becoming important. The destructive effect of electrostatic discharge on the IC chip is more pronounced. Static electricity often causes permanent damage to semiconductor components, computer systems, etc., thus affecting the circuit function of the integrated circuit and making the electronic product work abnormally, so that some protection measures or functions must be designed to protect the chip from the electrostatic discharge phenomenon.
The design of an on-chip ESD protection device requires consideration of two issues: firstly, the ESD protection device can discharge large current; secondly, the ESD protection device should be able to clamp the chip pin terminal voltage at a safe low voltage level when the chip is impacted by ESD. The small-sized high-voltage square ESD structure shown in fig. 1 has an upper and lower length of 320 micrometers, is a traditional ESD device, has a layout structure which is approximately in a round-corner rectangular structure, is generally called a square for short, and has a bottom end divided into two round-corner rectangles which are close together and are completely symmetrical left and right. The drain region is positioned in the central region of the layout, and the device with the structure has weaker ESD resistance, only 500V, and cannot meet certain application occasions with higher ESD requirements.
Disclosure of Invention
The invention aims to solve the technical problem of providing a high-voltage ESD structure, which can improve the voltage-resistant capability of the structure to realize higher voltage-resistant performance.
In order to solve the problems, the plane layout of the high-voltage ESD structure is a rounded rectangle MOS tube structure, wherein the drain region of the MOS tube is positioned in the center region of the rounded rectangle, and the polysilicon gate surrounds a graph which surrounds the rounded rectangle; the high-voltage square ESD structure is a bilateral symmetry structure;
dividing the rounded rectangle into a top rounded corner and a bottom rounded corner on a top plane; the arc-shaped area of the top fillet is provided with a heavily doped N-type area and a heavily doped P-type area which are parallel to each other and are in abutting contact; the arc-shaped heavily doped P-type region is positioned at the outer side and is provided with a first arc-shaped long side close to the outer side and a second arc-shaped long side close to the inner side; the second arc long side is contacted with the heavily doped N-type region; the inner side of the heavily doped P-type region is also provided with a polycrystalline silicon layer which is also arc-shaped, and the second arc-shaped long side of the heavily doped P-type region extends inwards in the vertical projection direction and exceeds the first arc-shaped long side of the polycrystalline silicon layer;
the method comprises the steps that a drain region located in a center region of a round rectangle is divided into a top drain region and a bottom drain region, a contact region is included in an active region of the top drain region, and a boundary of the active region is located outside the contact region and is separated from the contact region by a distance;
the contact area is divided into a left group and a right group, each group is provided with a plurality of contact holes, and the contact holes of the left group and the right group have a certain distance from the boundary of the active area;
the bottom drain region comprises a heavily doped N-type injection region, and the boundary of the heavily doped N-type injection region is smaller than the active region;
in the bottom drain region, the drain region at the bottommost end is not provided with a contact hole, and the drain region close to the central region is provided with two rows of contact holes;
the bottom fillet area is provided with a heavily doped P-type area and a heavily doped N-type area; the heavily doped N-type region is in abutting contact with the heavily doped P-type region; the inner side of the heavily doped N-type region is also provided with a polysilicon layer; the heavily doped P-type region extends inward in the vertical projection direction beyond the outer boundary of the polysilicon layer.
A further improvement is that the distance between the active region boundary of the top drain region and the contact hole is not less than 20 microns.
The bottom drain region is further improved in that the boundary of the heavily doped N-type region is reduced to the inside, so that the distance between the bottom drain region and the boundary of the active region is enlarged.
A further improvement is that the boundary of the heavily doped N-type region of the bottom drain region is retracted by 1 micrometer into the bottom drain region.
The bottom of the high-voltage square ESD structure is formed by abutting and contacting two rounded rectangles, namely the whole high-voltage square ESD structure is in a horseshoe shape with an opening abutted.
Compared with the traditional structure, the high-voltage square ESD structure has four modifications, and the high-voltage square ESD structure has the advantages that the voltage withstanding capability of the device is improved under the combined action of the modification of the heavy-doped N-type region and the heavy-doped P-type region in the top region of the whole device layout, the modification of the positions of the contact hole region at the top of the drain region, the modification of the positions of the heavy-doped N-type region and the contact hole region at the bottom of the drain region and the modification of the heavy-doped N-type region and the heavy-doped P-type region in the bottom region.
Drawings
Fig. 1 is a schematic layout diagram of a conventional high-voltage ESD structure.
Fig. 2 is an enlarged partial view of the top rounded corner of a prior art high voltage ESD structure.
Fig. 3 is an enlarged partial view of the top rounded corner of the high voltage ESD structure provided by the present invention.
Fig. 4 is an enlarged partial view of a top drain structure of a prior art high voltage ESD structure.
Fig. 5 is an enlarged view of a portion of the top drain structure of the high voltage ESD structure provided by the present invention.
Fig. 6 is an enlarged view of a portion of the bottom drain structure of a conventional high voltage ESD structure.
Fig. 7 is an enlarged view of a portion of the bottom drain structure of the high voltage ESD structure provided by the present invention.
Fig. 8 is an enlarged partial view of a bottom rounded corner structure of a conventional high voltage ESD structure.
Fig. 9 is an enlarged view of a portion of the bottom rounded corner structure of the high voltage ESD structure provided by the present invention.
Detailed Description
The high-voltage ESD structure refers to a structure shown in figure 1, wherein the plane layout of the structure is a laterally symmetrical rounded rectangular MOS tube structure, the drain region of the MOS tube is positioned in the central region of the rounded rectangle, and the polysilicon gate surrounds and encloses a rounded rectangular graph. The present invention is tuned to the layout structure shown in fig. 1, mainly to the A, B, C, D four regions as shown in fig. 1.
On the top plane, the rounded rectangle is divided into a top rounded corner (zone A) and a bottom rounded corner (zone D). The arc-shaped area of the top fillet is provided with a heavily doped N-type area and a heavily doped P-type area which are parallel to each other and are in abutting contact. Referring to fig. 2 and the enlarged partial view of the a region of fig. 3, fig. 2 is a conventional structure, and fig. 3 is a structure of the present invention, the inner side of the heavily doped P-type region (the second arc long side, because the heavily doped N-type region is in abutting contact with the heavily doped P-type region, is the first arc long side of the left side of the heavily doped N-type region, and the heavily doped N-type region overlaps the polysilicon layer) of the peripheral arc is moved inward by a certain distance, so that the second arc long side inwards exceeds the left boundary of the polysilicon layer, and the transverse width of the arc heavily doped N-type region is enlarged. The heavily doped P-type region slightly overlaps the polysilicon layer in the vertical projection direction.
The drain region located in the center region of the rounded rectangle is divided into a top drain region (B region) and a bottom drain region (C region). And the B region of the top drain region comprises a contact region in an active region, wherein the contact region is a left contact hole and a right contact hole, each contact region is provided with a plurality of contact holes, and the boundary of the active region is outside the contact region and is separated from the active region by a distance d. In the conventional structure, the contact area of the B area is closer to the boundary of the active area, and the contact hole area is moved inwards by a distance so that d is not lower than 20 microns.
In the bottom drain region, namely the C region, the C region comprises left and right identical drain regions due to the horseshoe-shaped structure of the main layout. In the bottom drain region, as shown in fig. 7, a heavily doped N-type implant region is included, the heavily doped N-type implant region having a smaller width than the active region and having an inner side that is not aligned with the active region, the heavily doped N-type implant region of the bottom drain region being recessed inward by a distance of at least 1 micron as compared to conventional structures, as shown by distance d1 at "1" in fig. 7.
In addition, in the C region, compared with the conventional structure, the contact hole near the bottom end of the original bottom drain region is deleted, namely, the contact hole is not reserved any more as shown at the position of "2" in the figure, and the contact hole near the central region is modified from a plurality of columns of the conventional structure to 2 columns, as shown at the position of "3" in fig. 7, 6 columns of contact holes are arranged at the position of the conventional structure, and the invention is adjusted to 2 columns and is arranged at the central position of the region.
In the bottom rounded region D, as shown in fig. 8 and 9, the heavily doped N-type region is in contact with the heavily doped P-type region, and the heavily doped P-type region located outside overlaps the boundary of the active region, i.e., the outer boundary of the heavily doped N-type region is adducted as shown at "1" in fig. 9.
The structure states that the high-voltage square ESD structure disclosed by the invention is structurally modified with a traditional device, the layout structure is modified again, and the voltage-withstanding capability of the device is improved by the combined action of the shape modification of a heavily doped N-type region and a heavily doped P-type region in the top region of the whole device layout, the position modification of a contact hole region at the top of a drain region, the position modification of the heavily doped N-type region and the contact hole region at the bottom of the drain region, the shape modification of the heavily doped N-type region and the heavily doped P-type region in the bottom region and the like. By further expanding the range of the heavily doped P-type region inward until the coverage of the polysilicon layer is exceeded, the heavily doped P-type region slightly overlaps the polysilicon layer (whether in the prior art or in the invention, the heavily doped N-type region always contacts the heavily doped P-type region in an abutting manner, and the second arc-shaped long side of the heavily doped P-type region moves inward by an amount equal to the width of the arc of the heavily doped P-type region), the source region at the point of the top rounded region disappears without current.
The same modification is maintained in the bottom rounded region, i.e., region D in fig. 1, as in the top rounded region, i.e., the arcuate segment of region a. After a certain distance is moved in the heavily doped P-type region, the source region also disappears without current, and after the current path is cut off, damage is not easy to generate, so that the ESD capability is improved. After the contact hole area is moved inwards, the distance from the contact hole to the drain area is increased, the resistance of the drain area is increased, and the ESD capacity can be improved by partial pressure. Through the modification of the structure, through simulation test, the device can improve the ESD capacity from the traditional 500V to 3KV, and the antistatic capacity is greatly improved.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A high voltage ESD structure characterized by: the high-voltage ESD structure is a MOS tube structure with a planar layout in a round rectangle, wherein a drain region of the MOS tube is positioned in the central region of the round rectangle, and the polysilicon gate surrounds a graph which encloses the round rectangle; the high-voltage ESD structure is a bilateral symmetry structure;
dividing the rounded rectangle into a top rounded corner and a bottom rounded corner on a top plane; the arc-shaped area of the top fillet is provided with a heavily doped N-type area and a heavily doped P-type area which are arc-shaped and are parallel to each other and are in abutting contact; the arc-shaped heavily doped P-type region is positioned at the outer side and is provided with a first arc-shaped long side close to the outer side and a second arc-shaped long side close to the inner side; the second arc long side is contacted with the heavily doped N-type region; the inner side of the heavily doped P-type region is also provided with a polycrystalline silicon layer which is also arc-shaped, and the second arc-shaped long side of the heavily doped P-type region extends inwards in the vertical projection direction and exceeds the first arc-shaped long side of the polycrystalline silicon layer;
the method comprises the steps that a drain region located in a center region of a round rectangle is divided into a top drain region and a bottom drain region, a contact region is included in an active region of the top drain region, and a boundary of the active region is located outside the contact region and is separated from the contact region by a distance;
the contact area is divided into a left group and a right group, each group is provided with a plurality of contact holes, and the contact holes of the left group and the right group have a certain distance from the boundary of the active area;
the bottom drain region comprises a heavily doped N-type injection region, and the boundary of the heavily doped N-type injection region is smaller than the active region;
in the bottom drain region, the drain region at the bottommost end is not provided with a contact hole, and the drain region close to the central region is provided with two rows of contact holes;
the bottom fillet area is provided with a heavily doped P-type area and a heavily doped N-type area; the heavily doped N-type region is in abutting contact with the heavily doped P-type region, and a polysilicon layer is arranged on the inner side of the heavily doped N-type region; the heavily doped P-type region extends inward in the vertical projection direction beyond the outer boundary of the polysilicon layer.
2. The high voltage ESD structure of claim 1, wherein: and the distance between the boundary of the active region of the top drain region and the contact hole is not less than 20 micrometers.
3. The high voltage ESD structure of claim 1, wherein: and the boundary of the bottom drain region, which is heavily doped with the N-type region, is reduced to the inside of the bottom drain region, so that the distance between the bottom drain region and the boundary of the active region is enlarged.
4. A high voltage ESD structure as claimed in claim 3 wherein: the boundary of the heavily doped N-type region of the bottom drain region is retracted into the bottom drain region by 1 micrometer.
5. The high voltage ESD structure of claim 1, wherein: the bottom of the high-voltage ESD structure is formed by abutting and contacting two rounded rectangle, namely the whole high-voltage ESD structure is U-shaped with an opening abutting.
6. The high voltage ESD structure of claim 5, wherein: and the two rounded rectangles at the bottom form two bottom drain regions with identical structures in the bottom region of the high-voltage ESD structure.
7. The high voltage ESD structure of claim 1, wherein: the second arc long side of the heavily doped P-type region of the top fillet region is moved inwards to remove the source end of the top region without current.
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| CN202011049234.7A CN111987094B (en) | 2020-09-29 | 2020-09-29 | High voltage ESD structure |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050532A (en) * | 2012-08-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | RF LDMOS (ratio frequency laterally diffused metal oxide semiconductor) device and manufacture method of RF LDMOS device |
| CN103681839A (en) * | 2012-09-10 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacture method |
| CN105514040A (en) * | 2015-12-22 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | LDMOS device integrated with JFET and technical method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8354714B2 (en) * | 2010-07-13 | 2013-01-15 | Shanghai Institute Of Microsystem And Information Technology, Chinese Academy Of Sciences | SOI MOS device having BTS structure and manufacturing method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103050532A (en) * | 2012-08-13 | 2013-04-17 | 上海华虹Nec电子有限公司 | RF LDMOS (ratio frequency laterally diffused metal oxide semiconductor) device and manufacture method of RF LDMOS device |
| CN103681839A (en) * | 2012-09-10 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacture method |
| CN105514040A (en) * | 2015-12-22 | 2016-04-20 | 上海华虹宏力半导体制造有限公司 | LDMOS device integrated with JFET and technical method |
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