CN112018105B - High-voltage electrostatic protection structure - Google Patents
High-voltage electrostatic protection structure Download PDFInfo
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- CN112018105B CN112018105B CN202011039757.3A CN202011039757A CN112018105B CN 112018105 B CN112018105 B CN 112018105B CN 202011039757 A CN202011039757 A CN 202011039757A CN 112018105 B CN112018105 B CN 112018105B
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- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 22
- 239000001301 oxygen Substances 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 9
- 230000002146 bilateral effect Effects 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims description 25
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 17
- 229920005591 polysilicon Polymers 0.000 claims description 17
- 230000003068 static effect Effects 0.000 claims description 11
- 230000000694 effects Effects 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 12
- 238000002347 injection Methods 0.000 abstract description 5
- 239000007924 injection Substances 0.000 abstract description 5
- 230000006872 improvement Effects 0.000 description 19
- 230000005611 electricity Effects 0.000 description 7
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7817—Lateral DMOS transistors, i.e. LDMOS transistors structurally associated with at least one other device
Abstract
The invention discloses a high-voltage electrostatic protection structure, which is positioned on a buried layer; on the section, the high-voltage electrostatic protection is of a bilateral symmetry structure and comprises a first high-voltage well I with a first conductivity type, a second high-voltage well II with a second conductivity type and a third high-voltage well III with a second conductivity type, wherein the first high-voltage well I is positioned in a central area; in the first high-voltage well, a first heavily doped region of a second conductivity type is arranged in a central region of the first high-voltage well, and a first field oxide, a second heavily doped region of the first conductivity type and a second field oxide are symmetrically and sequentially arranged on two sides of the first heavily doped region; in the second high-voltage well, a source region and a third heavy doping region of the LDMOS device are arranged, and a third field oxygen is arranged between the source region and the third heavy doping region at intervals. The invention increases the number and diffusion radius adjustable polygon or circular injection area in the high-voltage well area where the original drain area is located, so as to flexibly control the current distribution of the parasitic SCR structure, achieve the purpose of adjusting the proportion of the current flowing out path and improve the antistatic capability of the device.
Description
Technical Field
The invention relates to the field of semiconductor device design and manufacture, in particular to a high-voltage electrostatic protection structure.
Background
Static electricity is an objective natural phenomenon, and various modes are generated, such as contact, friction, induction between electric appliances and the like. Static electricity is characterized by long-time accumulation, high voltage, low electric quantity, small current and short action time. Static electricity poses serious hazards in a number of fields. Friction electrification and human static electricity are two major hazards in the electronic industry, and often cause unstable operation and even damage of electronic and electric products.
As feature sizes of manufacturing processes of semiconductor integrated circuits are smaller, chip units are smaller, and antistatic capability of chips is becoming important. Static electricity often causes permanent damage to semiconductor components, computer systems, etc., thus affecting the circuit function of the integrated circuit and making the electronic product work abnormally, so that some protection measures or functions must be designed to protect the chip from the electrostatic discharge phenomenon.
In order to improve ESD capability and design flexibility, some modifications are generally made to the LDMOS device, as shown in fig. 1, which is a cross-sectional view of a typical PLDMOS device, where the drain region is located in a high voltage P-well (HVPW), the source region is located in a high voltage N-well (HVNW), and the gate is shorted to the source region and the high voltage N-well terminal through a small resistor to form an electrostatic input terminal. The single-direction controllable silicon is a controllable rectifying electronic element, can be changed from off to on under the action of an external control signal, but once the SCR is turned on, the external signal cannot turn off the SCR, and can only be turned off by removing a load or reducing the voltage at two ends of the SCR, so that the ESD capability can be greatly improved, but the voltage Vh is maintained to be not more than 10V after the Snap-back occurs in the pure SCR structure, and the voltage Vh is generally maintained to be higher than 10V after the Snap-back occurs.
Disclosure of Invention
The invention aims to solve the technical problem of providing a high-voltage electrostatic protection structure which improves the electrostatic protection capability of a device on the premise of not increasing the area of the device.
To solve the above-described problems, the high-voltage electrostatic protection structure of the present invention is located above a buried layer of a second conductivity type in a substrate having the first conductivity type;
on the section, the high-voltage electrostatic protection is of a bilateral symmetry structure and comprises a first high-voltage well I with a first conductivity type, a second high-voltage well II with a second conductivity type and a third high-voltage well III with a second conductivity type, wherein the first high-voltage well I is positioned in a central area;
in the first high-voltage well, a first heavily doped region of a second conductivity type is arranged in a central region of the first high-voltage well, and a first field oxide, a second heavily doped region of the first conductivity type and a second field oxide are symmetrically and sequentially arranged on two sides of the first heavily doped region;
in the second high-voltage well, a source region of the LDMOS device and a third heavily doped region of a second conductivity type led out of the second high-voltage well are arranged, and third field oxygen is arranged between the source region and the third heavily doped region at intervals;
the surface of the substrate between the second high-voltage well and the first high-voltage well is provided with a gate structure of the LDMOS device, and the gate structure comprises a gate dielectric layer positioned on the surface of the substrate and contacted with the substrate and a polysilicon gate positioned above the gate dielectric layer;
the polysilicon gate also covers part of the second field oxide close to the gate structure;
the structures of the second high-voltage well, the third high-voltage well and the upper part of the substrate which are positioned on two sides of the first high-voltage well are identical, and the center of the whole device is bilaterally symmetrical.
The further improvement is that the plane layout of the heavily doped region I of the central region in the high-voltage trap I is circular, and a contact hole is led out above the heavily doped region I.
The further improvement is that the heavily doped region is grounded after being led out.
In a further improvement, the first heavily doped regions of the second conductivity type are arranged in a plurality of lines in a top plane.
The further improvement is that the contact holes of the second heavily doped region are arranged at two sides of the first heavily doped region.
The further improvement is that the first high-voltage trap and the second high-voltage trap are in contact with each other or are not in contact with each other at intervals in section; the form of the third high-voltage trap and the first high-voltage trap is symmetrical to the form of the second high-voltage trap.
The further improvement is that the first heavy doping area and the second heavy doping area in the first high-voltage trap are led out and then are short-circuited to the ground.
The polysilicon gate is led out and then connected with a resistor, and is short-circuited with the leading-out ends of the source region and the heavy doping region III in the high-voltage trap II to form an electrostatic input end of the high-voltage electrostatic protection structure; the form of the third high-voltage trap and the first high-voltage trap is symmetrical to the form of the second high-voltage trap.
In a further improvement, the first heavily doped region is polygonal in shape, and the number of sides of the first heavily doped region is three to ten or more.
The further improvement is that the Snap-back maintaining voltage is improved by adjusting the diffusion radius and the number of the round heavily doped regions I, so that the purpose of preventing the Latch-up effect is achieved.
A further improvement is that the first conductivity type is P-type and the second conductivity type is N-type; alternatively, the first conductivity type is N-type and the second conductivity type is P-type.
To solve the above-mentioned problems, the present invention provides another high-voltage electrostatic protection structure based on an LDMOS device, which is located above a buried layer of a second conductivity type in a substrate of a first conductivity type;
on the section, the high-voltage electrostatic protection is of a bilateral symmetry structure and comprises a high-voltage trap IV of a first conductivity type positioned in a central area, a high-voltage trap V of a second conductivity type positioned on two sides of the high-voltage trap IV and a high-voltage trap VI;
in the fourth high-voltage well, the center of the structure is provided with a fourth heavy doping region of the first conductivity type, and the two sides of the fourth heavy doping region are symmetrically and sequentially provided with a fourth field oxygen, a fifth heavy doping region of the second conductivity type, a fifth field oxygen, a sixth heavy doping region of the first conductivity type and a sixth field oxygen;
in the fifth high-voltage well, a source region of the LDMOS device and a heavy doping region seven of a second conduction type led out of the fifth high-voltage well are arranged, and field oxygen seven is arranged between the source region and the heavy doping region seven at intervals;
the surface of the substrate between the fifth high-voltage well and the fourth high-voltage well is provided with a grid structure of the LDMOS device, and the grid structure comprises a grid dielectric layer positioned on the surface of the substrate and contacted with the substrate and a polysilicon grid positioned above the grid dielectric layer;
the polysilicon gate also covers part of the sixth field oxide close to the gate structure;
the structures of the high-voltage trap five and the high-voltage trap six which are positioned on the two sides of the high-voltage trap four and above the substrate are completely the same, and the center of the whole device is bilaterally symmetrical.
The further improvement is that the plane layout of the heavy doping region five positioned in the high-voltage trap four is round, and a contact hole is led out above the heavy doping region five.
The further improvement is that the fifth heavily doped region is led out and then grounded.
In a further improvement, the center region has a plurality of heavily doped regions of the second conductivity type arranged in a straight line in a top plan view.
The further improvement is that the contact holes of the heavy doping region IV and the heavy doping region VI are arranged at the two sides of the heavy doping region V.
The further improvement is that the high-voltage trap IV and the high-voltage trap V are in contact with each other or are in interval without being in contact with each other in section; the form of the high-voltage trap six and the high-voltage trap four are symmetrical to the high-voltage trap two.
The further improvement is that the fifth heavy doping area and the fourth heavy doping area in the fourth high-voltage well are led out and then are short-circuited to the ground.
The polysilicon gate is led out and then connected with a resistor, and is short-circuited with the leading-out ends of the source region and the heavy doping region seven in the high-voltage trap five to form an electrostatic input end of the high-voltage electrostatic protection structure; the form of the high-voltage trap six and the high-voltage trap four is kept symmetrical with the high-voltage trap five.
In a further improvement, the shape of the heavily doped region five is polygonal, and the number of sides of the heavily doped region is three to ten or more.
The further improvement is that the diffusion radius and the number of the round heavy doped regions five are adjusted to improve the Snap-back maintaining voltage, so that the purpose of preventing the Latch-up effect from occurring is achieved.
A further improvement is that the first conductivity type is P-type and the second conductivity type is N-type; alternatively, the first conductivity type is N-type and the second conductivity type is P-type.
The high-voltage electrostatic protection structure designs the device into a symmetrical structure, adds polygonal or circular injection regions which are opposite to the drain region in the high-voltage well region where the original drain region is located, and can flexibly control the current distribution of the parasitic SCR structure by adjusting the quantity and the diffusion radius of the injection regions, thereby achieving the purpose of adjusting the Snap-back maintaining voltage by adjusting the proportion of the current flowing-out path and improving the antistatic capability of the device.
Drawings
Fig. 1 is a schematic view of an electrostatic protection structure formed by a conventional PLDMOS.
Fig. 2 is an equivalent circuit diagram of the structure shown in fig. 1.
Fig. 3 is a schematic view of an electrostatic protection structure according to a first embodiment of the present invention;
fig. 4 is a plan view of the electrostatic protection structure shown in fig. 3.
Fig. 5 is a schematic view of an electrostatic protection structure according to a second embodiment of the present invention;
fig. 6 is a plan view of the electrostatic protection structure shown in fig. 5.
Description of the reference numerals
1 is high voltage well one (HVPW), 2 is high voltage well two (HVNW), 3 is high voltage well three (HVNW), 4 is heavily doped region one (n+), 5 is heavily doped region two (p+), 6 is first field oxygen, 7 is second field oxygen, 8 is third field oxygen, 9 is source region (p+), 10 is heavily doped region three (n+);
21 is high voltage well four (HVPW), 22 is high voltage well five (HVNW), 23 is high voltage well six (HVNW), 24 is heavily doped region four (p+), 25 is fourth field oxygen, 26 is heavily doped region five (n+), 27 is fifth field oxygen, 28 is heavily doped region six (p+), 29 is sixth field oxygen, 30 is source region, 31 is seventh field oxygen, 32 is heavily doped region seven (n+).
Detailed Description
The high-voltage electrostatic protection structure of the invention, taking PLDMOS devices as an example, is illustrated by two examples as follows:
example 1
As shown in fig. 3, the structure is located above a buried layer NBL of N type in a substrate having P type.
On the section, the high-voltage electrostatic protection is of a bilateral symmetry structure and comprises a P-type high-voltage well I positioned in a central area, an N-type high-voltage well II and a high-voltage well III positioned at two sides of the high-voltage well I.
In the first high-voltage well, an N-type heavily doped region I is arranged in a central region of the first high-voltage well, and a first field oxide, a P-type heavily doped region II and a second field oxide are symmetrically and sequentially arranged on two sides of the heavily doped region I.
In the second high-voltage well, a source region of an LDMOS device and an N-type heavily doped region III led out of the second high-voltage well are arranged, and third field oxygen is arranged between the source region and the heavily doped region III at intervals;
the surface of the substrate between the second high-voltage well and the first high-voltage well is provided with a gate structure of the LDMOS device, and the gate structure comprises a gate dielectric layer positioned on the surface of the substrate and contacted with the substrate and a polysilicon gate positioned above the gate dielectric layer.
The polysilicon gate also covers a portion of the second field oxide proximate the gate structure.
The first high-voltage well and the second high-voltage well can be contacted and abutted on the section plane, or can be separated by a certain distance, and the third high-voltage well is the same.
The structures of the second high-voltage well, the third high-voltage well and the upper part of the substrate which are positioned on two sides of the first high-voltage well are identical, and the center of the whole device is bilaterally symmetrical.
The planar layout of the structure of fig. 3 is shown in conjunction with fig. 4, the planar layout of the heavily doped region one located in the central region of the first high-voltage well is polygonal or circular, and the upper part of the planar layout is provided with a plurality of contact holes which are led out and then grounded, and meanwhile, the surrounding heavily doped region two of the P type is grounded.
The number of the first heavily doped regions is a plurality, the first heavily doped regions are arranged in a straight line, and the contact holes of the second heavily doped regions are arranged on two sides of the first heavily doped regions.
The polysilicon gate is led out and then connected with a resistor, and is short-circuited with the leading-out ends of the source region and the heavy doping region III in the high-voltage trap II to form an electrostatic input end of the high-voltage electrostatic protection structure; also, the shapes of the third high-voltage well and the first high-voltage well are symmetrical to the second high-voltage well.
The first heavy doping region is provided with a contact hole of the second heavy doping region at two sides, the second high voltage well and the third high voltage well are symmetrically arranged at the far ends of the two sides, and the source region and the contact hole of the PLDMOS device are contained in the second heavy doping region and the third high voltage well. Two elongated polysilicon strips are the gates of the device.
Example two
The second embodiment provides another high voltage electrostatic protection structure, which is to increase the number of heavily doped regions in the drain-side high voltage well based on the first embodiment. As shown in fig. 5, the main difference is the arrangement of the heavily doped regions in the high-voltage well four, that is, the arrangement of the heavily doped regions in the drain-side high-voltage well four in fig. 5, the heavily doped regions in the central region in the drain-side high-voltage P-well high-voltage well four are P-type, and the fourth field oxygen, the heavily doped regions five (n+), the fifth field oxygen, the heavily doped regions six (p+) and the sixth field oxygen are symmetrically arranged in sequence on two sides of the center.
On the section, the high-voltage electrostatic protection is of a bilateral symmetry structure and comprises a high-voltage trap IV of a first conductivity type, a high-voltage trap V and a high-voltage trap V, wherein the high-voltage trap IV is positioned in a central area, and the high-voltage trap V are positioned on two sides of the high-voltage trap IV and are of a second conductivity type.
In the fourth high-voltage well, the fourth heavy doping region and the fifth heavy doping region are led out through the contact hole and are connected to the ground.
On the plane layout shown in fig. 6, the fifth heavily doped regions are arranged in two columns, the number of the fifth heavily doped regions is a plurality of, the patterns of the fifth heavily doped regions are polygonal or circular, and the first heavily doped regions and the fifth heavily doped regions in two embodiments of the invention are both circular.
The fifth side of the heavy doping region is provided with contact holes of the fourth heavy doping region and the sixth heavy doping region, the fifth high voltage well and the sixth high voltage well are symmetrically arranged at the far end, and the source region and the contact holes of the PLDMOS device are contained in the fifth heavy doping region and the sixth heavy doping region. Two elongated polysilicon strips are the gates of the device.
The structural features of the other parts of the second embodiment and the connection manner of the terminals are consistent with those of the second embodiment.
According to the structure of the two embodiments, the Snap-back Snap-back maintaining voltage can be improved by adjusting the diffusion radius and the number of the first or the fifth round heavily doped regions, so that the purpose of preventing the Latch-up effect is achieved. Taking the first embodiment (second embodiment) as an example, when static electricity enters the static electricity protection structure of the invention from the drain electrode, the PN junction formed by the first high-voltage trap and the second and third high-voltage traps of the high-voltage PLDMOS tube breaks down, so that the parasitic SCR structure formed by the second source region/the second high-voltage trap, the third high-voltage trap and the first heavy doping region is triggered to be opened; because the first N+ heavy doped region at the drain end is surrounded by the second P+ heavy doped region, the first N+ heavy doped region is circular, the current distribution of the SCR structure can be flexibly adjusted by adjusting the number and the radius of the first N+ heavy doped region, most of current flows out of the second P+ heavy doped region surrounding the first circular N+ heavy doped region, and a small part of current still flows out of the first circular N+ heavy doped region, the smaller the number of the first circular N+ heavy doped region, the smaller the radius, the less current flows through the first circular N+ heavy doped region, the purpose of adjusting snapback voltage can be achieved by adjusting the proportion of a current flowing out path, and only the smaller current flows out of the circular diffusion region, so that the snapback voltage of the structure can be higher.
Referring specifically to FIG. 3, parameters W1, S1, W2, S2, W3, etc. are included as shown. Wherein W1 represents the width of the P-type heavily doped region at the left side of the drain region in the figure, S1 is the distance between the P-type heavily doped region at the left side of the corresponding drain region and the middle N-type heavily doped region in the figure (also the width of the first field oxide 6), W2 is the width of the middle N-type heavily doped region I of the corresponding drain region in the figure, S2 is the distance between the middle N-type heavily doped region and the P-type heavily doped region at the right side of the corresponding drain region in the figure, and W3 is the width of the P-type heavily doped region at the right side of the corresponding drain region in the figure. Different technical effects can be achieved by carrying out different adjustment on the parameters: the increase of W1/S1 increases the base width of the parasitic PNP triode at the left side, so that the amplification factor of the parasitic PNP is reduced, and the maintenance voltage is increased; the increase of W2 increases the emitter width of the parasitic NPN triode, so that the amplification factor of the parasitic NPN is increased, and the maintenance voltage is reduced; s2, increasing the base width of the parasitic NPN triode on the right side, so that the amplification factor of the parasitic NPN is reduced, and the maintaining voltage is increased; the increase of W3 increases the collector width of the right parasitic PNP transistor, resulting in a decrease of the amplification factor of the parasitic PNP and an increase of the sustain voltage.
The high-voltage electrostatic protection structure designs the device into a symmetrical structure, adds polygonal or circular injection regions which are opposite to the drain region in the high-voltage well region where the original drain region is located, and can flexibly control the current distribution of the parasitic SCR structure by adjusting the quantity and the diffusion radius of the injection regions, thereby achieving the purpose of adjusting the Snap-back snapback maintaining voltage by adjusting the proportion of the current flowing-out path and improving the antistatic capability of the device.
The above are only preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. The utility model provides a high-voltage static protection structure, high-voltage static protection structure is based on LDMOS device, its characterized in that: the structure is located over a buried layer of a second conductivity type in a substrate having the first conductivity type;
on the section, the high-voltage electrostatic protection is of a bilateral symmetry structure and comprises a first high-voltage well I with a first conductivity type, a second high-voltage well II with a second conductivity type and a third high-voltage well III with a second conductivity type, wherein the first high-voltage well I is positioned in a central area;
in the first high-voltage well, a first heavily doped region of a second conductivity type is arranged in a central region of the first high-voltage well, and a first field oxide, a second heavily doped region of the first conductivity type and a second field oxide are symmetrically and sequentially arranged on two sides of the first heavily doped region;
in the second high-voltage well, a source region of the LDMOS device and a third heavily doped region of a second conductivity type led out of the second high-voltage well are arranged, and third field oxygen is arranged between the source region and the third heavily doped region at intervals;
the surface of the substrate between the second high-voltage well and the first high-voltage well is provided with a gate structure of the LDMOS device, and the gate structure comprises a gate dielectric layer positioned on the surface of the substrate and contacted with the substrate and a polysilicon gate positioned above the gate dielectric layer;
the polysilicon gate also covers part of the second field oxide close to the gate structure;
the structures of the second high-voltage well, the third high-voltage well and the upper part of the substrate which are positioned at two sides of the first high-voltage well are completely the same, and the center of the whole device is bilaterally symmetrical;
and the plane layout of the heavily doped region I positioned in the central region in the high-voltage trap I is circular, and a contact hole is led out above the heavily doped region I.
2. The high voltage electrostatic protection structure according to claim 1, wherein: and the first heavily doped region is led out and then grounded.
3. The high voltage electrostatic protection structure according to claim 1, wherein: the first heavily doped regions of the second conductivity type in the central region are a plurality of and are arranged in a straight line on a top plane.
4. The high voltage electrostatic protection structure according to claim 1, wherein: the contact holes of the second heavily doped region are arranged on two sides of the first heavily doped region.
5. The high voltage electrostatic protection structure according to claim 1, wherein: the first high-voltage well and the second high-voltage well are in contact with each other and are abutted against each other or are separated from each other and are not abutted against each other in section; the form of the third high-voltage trap and the first high-voltage trap is symmetrical to the form of the second high-voltage trap.
6. The high voltage electrostatic protection structure according to claim 1, wherein: and the first heavily doped region and the second heavily doped region in the first high-voltage well are led out and then are short-circuited to the ground.
7. The high voltage electrostatic protection structure according to claim 1, wherein: the polysilicon gate is led out and then connected with a resistor, and is short-circuited with the leading-out ends of the source region and the heavy doping region III in the high-voltage trap II to form an electrostatic input end of the high-voltage electrostatic protection structure; the form of the third high-voltage trap and the first high-voltage trap is symmetrical to the form of the second high-voltage trap.
8. The high voltage electrostatic protection structure according to claim 1, wherein: the first heavily doped region is polygonal in shape, and the number of sides of the first heavily doped region is three to ten or more.
9. The high voltage electrostatic protection structure according to claim 1, wherein: the diffusion radius and the number of the round heavily doped regions I are adjusted, so that the Snap-back maintaining voltage is improved, and the purpose of preventing the Latch-up effect is achieved.
10. The high voltage electrostatic protection structure according to claim 1, wherein: the first conductivity type is P type, and the second conductivity type is N type; alternatively, the first conductivity type is N-type and the second conductivity type is P-type.
11. The utility model provides a high-voltage static protection structure, high-voltage static protection structure is based on LDMOS device, its characterized in that: the structure is located over a buried layer of a second conductivity type in a substrate having the first conductivity type;
on the section, the high-voltage electrostatic protection is of a bilateral symmetry structure and comprises a high-voltage trap IV of a first conductivity type positioned in a central area, a high-voltage trap V of a second conductivity type positioned on two sides of the high-voltage trap IV and a high-voltage trap VI;
in the fourth high-voltage well, the center of the structure is provided with a fourth heavy doping region of the first conductivity type, and the two sides of the fourth heavy doping region are symmetrically and sequentially provided with a fourth field oxygen, a fifth heavy doping region of the second conductivity type, a fifth field oxygen, a sixth heavy doping region of the first conductivity type and a sixth field oxygen;
in the fifth high-voltage well, a source region of the LDMOS device and a heavy doping region seven of a second conduction type led out of the fifth high-voltage well are arranged, and field oxygen seven is arranged between the source region and the heavy doping region seven at intervals;
the surface of the substrate between the fifth high-voltage well and the fourth high-voltage well is provided with a grid structure of the LDMOS device, and the grid structure comprises a grid dielectric layer positioned on the surface of the substrate and contacted with the substrate and a polysilicon grid positioned above the grid dielectric layer;
the polysilicon gate also covers part of the sixth field oxide close to the gate structure;
the structures of the high-voltage trap five, the high-voltage trap six and the upper part of the substrate which are positioned on the two sides of the high-voltage trap four are completely the same, and the center of the whole device is bilaterally symmetrical;
and the plane layout of the heavy doping region five positioned in the high-voltage trap four is circular, and a contact hole is led out above the heavy doping region five.
12. The high voltage electrostatic protection structure according to claim 11, wherein: and the fifth heavily doped region is led out and then grounded.
13. The high voltage electrostatic protection structure according to claim 11, wherein: and the center region is provided with a plurality of heavily doped regions of the second conductivity type, which are arranged in a straight line on a top plane.
14. The high voltage electrostatic protection structure according to claim 11, wherein: the contact holes of the heavy doping region IV and the heavy doping region VI are arranged on the two sides of the heavy doping region V.
15. The high voltage electrostatic protection structure according to claim 11, wherein: the high-voltage trap IV and the high-voltage trap V are in contact with each other and are abutted against each other or are separated from each other and are not abutted against each other on the section; the form of the high-voltage trap six and the high-voltage trap four are symmetrical to the high-voltage trap two.
16. The high voltage electrostatic protection structure according to claim 11, wherein: and the fifth heavy doped region and the fourth heavy doped region in the fourth high-voltage well are led out and then are short-circuited to the ground.
17. The high voltage electrostatic protection structure according to claim 11, wherein: the polysilicon gate is led out and then connected with a resistor, and is short-circuited with the source region in the high-voltage trap V and the leading-out end of the heavy doping region V to form an electrostatic input end of the high-voltage electrostatic protection structure; the form of the high-voltage trap six and the high-voltage trap four is kept symmetrical with the high-voltage trap five.
18. The high voltage electrostatic protection structure according to claim 11, wherein: the shape of the heavy doping region five is polygonal, and the number of sides of the heavy doping region five is three to ten or more.
19. The high voltage electrostatic protection structure according to claim 11, wherein: the diffusion radius and the number of the round heavily doped regions are adjusted, so that the Snap-back maintaining voltage is improved, and the purpose of preventing the Latch-up effect is achieved.
20. The high voltage electrostatic protection structure according to claim 11, wherein: the first conductivity type is P type, and the second conductivity type is N type; alternatively, the first conductivity type is N-type and the second conductivity type is P-type.
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| US9583603B2 (en) * | 2013-02-11 | 2017-02-28 | Nxp Usa, Inc. | ESD protection with integrated LDMOS triggering junction |
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| CN102110686A (en) * | 2010-12-17 | 2011-06-29 | 无锡华润上华半导体有限公司 | SCR (silicon controlled rectifier)-based electrostatic protection device of integrated circuit |
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