CN113675189B - Electrostatic protection device and chip - Google Patents
Electrostatic protection device and chip Download PDFInfo
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- CN113675189B CN113675189B CN202111231410.3A CN202111231410A CN113675189B CN 113675189 B CN113675189 B CN 113675189B CN 202111231410 A CN202111231410 A CN 202111231410A CN 113675189 B CN113675189 B CN 113675189B
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- 229910052710 silicon Inorganic materials 0.000 claims abstract description 55
- 239000010703 silicon Substances 0.000 claims abstract description 55
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 54
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims description 35
- 229910044991 metal oxide Inorganic materials 0.000 claims description 30
- 150000004706 metal oxides Chemical class 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 26
- 239000002019 doping agent Substances 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 230000003068 static effect Effects 0.000 abstract description 18
- 238000010586 diagram Methods 0.000 description 7
- 230000005611 electricity Effects 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/044—Physical layout, materials not provided for elsewhere
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- Computer Hardware Design (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses an electrostatic protection device and a chip, which comprise a silicon controlled rectifier group, wherein the silicon controlled rectifier group comprises a first silicon controlled rectifier and a second silicon controlled rectifier. The first silicon controlled rectifier comprises a first anode, a first cathode, a first control electrode and a common control electrode which are positioned in the substrate, and the second silicon controlled rectifier comprises a second anode, a second cathode, a second control electrode and the common control electrode which are positioned in the substrate. The substrate includes a first well and a second well within the first well, wherein a common control electrode, a first anode and a second anode are located in the second well, a first cathode and a first control electrode, and a second cathode and a second control electrode are located in the first well. Therefore, the silicon controlled rectifier group can bear higher static pressure, and the voltage resistance of the static protection device can be further improved. In addition, the silicon controlled rectifier group has reasonable structural layout, smooth wiring and small occupied area.
Description
Technical Field
The invention generally relates to the technical field of semiconductor electrostatic protection, in particular to an electrostatic protection device and a chip.
Background
Static electricity is usually generated artificially or even accumulated in the components themselves, and processes such as production, assembly, testing, storage, transportation and the like may form or accumulate static electricity in human bodies, instruments or chips, once a static electricity leakage path is formed, the instantaneous voltage and/or current thereof is high, and destructive and permanent damage is easily caused to the instruments or chips.
Therefore, most chips or devices need to be protected from Static Electricity (ESD), and the robustness of the chips or devices under severe transient environments can be guaranteed by ESD.
However, the electrostatic protection in the conventional technical solution is liable to exceed the limit that the electrostatic protection can withstand when the electrostatic protection is subjected to the electrostatic impact of higher voltage and/or higher current.
Disclosure of Invention
The invention aims to provide an electrostatic protection device and a chip, and aims to improve the voltage resistance of the electrostatic protection device.
In one aspect, the present invention provides an electrostatic discharge protection device, including a silicon controlled rectifier set, the silicon controlled rectifier set including: the silicon controlled rectifier comprises a first silicon controlled rectifier and a second silicon controlled rectifier, wherein the first silicon controlled rectifier comprises a first anode, a first cathode, a first control electrode and a common control electrode which are positioned in a substrate, and the second silicon controlled rectifier comprises a second anode, a second cathode, a second control electrode and the common control electrode which are positioned in the substrate;
wherein the substrate comprises a first well and a second well within the first well;
the first anode and the second anode, the first cathode and the second cathode, the first control electrode and the second control electrode, and the common control electrode are juxtaposed in a first direction and extend in a second direction;
the common control electrode, the first anode, and the second anode are located in the second well, and the common control electrode is located between the first anode and the second anode;
the first cathode and the first control electrode, and the second cathode and the second control electrode are located in the first trap and located on two sides of the first trap in the first direction respectively.
Further preferably, the first control electrode and the second control electrode are respectively located outside the first cathode and the second cathode.
Further preferably, the first trap has a third cathode and a fourth cathode, the third cathode and the fourth cathode are respectively parallel to the first control electrode and the second control electrode and are located at the outer sides of the first control electrode and the second control electrode relative to the common control electrode, and the third cathode and the fourth cathode and the first cathode and the second cathode are commonly connected to a cathode metal wire.
Further preferably, the substrate still includes second type buried layer, first type well is in the orthographic projection scope of second type buried layer, second type buried layer has the third anode, the third anode is the annular setting, just the third anode with first anode with the second anode meets the positive pole metal wire altogether.
Further preferably, the first anode and the second anode, the first cathode and the second cathode, the first control electrode and the second control electrode, the common control electrode, the third cathode and the fourth cathode are within an annular range of the third anode.
Further preferably, the first gate and the second gate are commonly connected to a first metal line, and the common gate is connected to a second metal line.
Further preferably, the anode metal line and the cathode metal line extend in the first direction and are respectively located between the first metal line and the second metal line.
Further preferably, the substrate has an external electrode, the external electrode is disposed around the third anode, and the external electrode is grounded.
Further preferably, the first well is a P-type well, and the second well is an N-type well; the common control electrode, the first cathode and the second cathode have N-type dopant ions, and the first anode, the second anode, the first control electrode and the second control electrode have P-type dopant ions.
Further preferably, the first cathode, the second well and the first control electrode form a first transistor, the first anode, the second well and the first well form a second transistor, and the second cathode, the first well and the second well form a third transistor; the first transistor and the second transistor constitute the first silicon controlled rectifier, and the second transistor and the third transistor constitute the second silicon controlled rectifier.
Preferably, the electrostatic protection device further comprises a resistor-capacitor clamp tube and at least one diode, the thyristor group is arranged between the at least one diode and the resistor-capacitor clamp tube, and the resistor-capacitor clamp tube and the at least one diode are electrically connected with the thyristor group through a metal wire.
Further preferably, each of the diodes includes:
the cathode and the first electrode are rectangular in plan view;
a positive electrode and a second electrode and a third electrode positioned on the positive electrode, the positive electrode surrounding the negative electrode;
the negative electrode and the positive electrode are arranged at a long edge interval and a short edge interval, and the ratio of the long edge interval to the short edge interval is 1: 1.5-1: 2.
More preferably, the second electrode and the third electrode are located on both sides of the first electrode, and are rectangular in plan view;
wherein short sides of the second and third electrodes are aligned with short sides of the first electrode.
Further preferably, the rc-clamp includes a first metal oxide semiconductor electrically connected to the scr set, and the first metal oxide semiconductor includes:
the planar light source comprises a second type doping area and a first type doping area surrounding the second type doping area, wherein the overlooking shape of the second type doping area is rectangular;
the second type doping area and the first type doping area are arranged between the first type doping area and the second type doping area, a short edge distance and a long edge distance are arranged between the second type doping area and the first type doping area, and the ratio range of the short edge distance to the long edge distance is 1: 1.5-1: 2.
Preferably, the second type doping area is formed with a plurality of source electrodes and drain electrodes alternately arranged along a long side of the second type doping area, the number of the source electrodes is even, and two source electrodes are respectively located at two ends of the second type doping area.
Further preferably, the first metal oxide semiconductor further includes:
a plurality of gates located on said second type doped region, each said gate located between one said source and one said drain;
and the two gate lines are positioned between the second type doping area and the first type doping area and extend along the long edge of the second type doping area, and two ends of each gate are respectively connected with the two gate lines.
Further preferably, the electrostatic protection device further includes a second metal oxide semiconductor and a resistor electrically connected to the at least one diode, and the second metal oxide semiconductor, the resistor and the at least one diode are located on the same side of the silicon controlled rectifier group.
In another aspect, the invention provides a chip comprising a silicon controlled rectifier set including a first silicon controlled rectifier and a second silicon controlled rectifier. The first silicon controlled rectifier comprises a first anode, a first cathode, a first control electrode and a common control electrode which are positioned in the substrate, and the second silicon controlled rectifier comprises a second anode, a second cathode, a second control electrode and the common control electrode which are positioned in the substrate. The substrate includes a first well and a second well within the first well, wherein a common control electrode, a first anode and a second anode are located in the second well, a first cathode and a first control electrode, and a second cathode and a second control electrode are located in the first well. Therefore, the silicon controlled rectifier group can bear higher static pressure, and the voltage resistance of the static protection device can be further improved. In addition, the silicon controlled rectifier group has reasonable structural layout, smooth wiring and small occupied area.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic top view of a silicon controlled rectifier set in an electrostatic protection device according to an embodiment of the present invention;
FIG. 2 is a schematic cross-sectional view of the SCR group of FIG. 1 taken along line A-A1;
FIG. 3 is a schematic layout diagram of a device structure in an electrostatic protection device according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of an ESD protection device according to an embodiment of the present invention;
fig. 5 is a schematic circuit diagram of a thyristor rectifier group according to an embodiment of the invention;
fig. 6 is a schematic top view of a diode according to an embodiment of the present invention;
fig. 7 is a schematic top view of a first metal oxide semiconductor according to an embodiment of the present invention.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.
It will be understood that when an element is referred to as being "on," "connected to" another element, it can be directly on or connected to the other element or intervening elements may also be present. Other words used to describe the relationship between components should be interpreted in a similar manner.
It should be noted that the drawings provided in the embodiments of the present invention are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in the actual implementation, the type, quantity and proportion of the components in the actual implementation can be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic top view of a silicon controlled rectifier assembly in an electrostatic discharge protection device according to an embodiment of the present invention, and fig. 2 is a schematic cross-sectional view of the silicon controlled rectifier assembly along a line a-a1 in fig. 1.
The set 10 of thyristors comprises a first thyristor comprising a first anode 101, a first cathode 102, a first control electrode 103 and a common control electrode 104 in the substrate 11 and a second thyristor comprising a second anode 105, a second cathode 106, a second control electrode 107 and a common control electrode 104 in the substrate 11. The first anode 101 and the second anode 105, the first cathode 102 and the second cathode 106, the first control electrode 103 and the second control electrode 107, and the common control electrode 104 are juxtaposed along a first direction and extend along a second direction, and a Shallow Trench Isolation (STI) structure 110 is disposed therebetween.
In one implementation, substrate 11 may include a second type buried layer 12, a first well 13 within an orthographic projection of second type buried layer 12, and a second well 14 within first well 13. Further, the substrate 11 may be a semiconductor substrate 11, and may be, for example, a Silicon (Si), Germanium (Ge), SiGe substrate 11, Silicon On Insulator (SOI), Germanium On Insulator (GOI), or the like. A second type buried layer 12 may be formed in the substrate 11, a first type well 13 may be formed in the second type buried layer 12, and a second type well 14 may be formed in the first type well 13 by ion implantation in the substrate 11.
The common control electrode 104, the first anode 101, and the second anode 105 are located in the second well 14, and the common control electrode 104 is located between the first anode 101 and the second anode 105. The first cathode 102 and the first control electrode 103, and the second cathode 106 and the second control electrode 107 are located in the first well 13, and are respectively located on both sides of the first well 13 in the first direction. Specifically, the first control electrode 103 is located outside the first cathode 102, and the second control electrode 107 is located outside the second cathode 106. These electrodes may be formed by ion implantation in the first well 13 and the second well 14.
The first well 13 has a third cathode 131 and a fourth cathode 132, the third cathode 131 and the fourth cathode 132 being juxtaposed with the first control electrode 103 and the second control electrode 107, respectively. The third cathode 131 is located outside the first control electrode 103 with respect to the common control electrode 104, and the fourth cathode 132 is located outside the second control electrode 107 with respect to the common control electrode 104. Wherein the third cathode 131 and the fourth cathode 132 are connected to the cathode wire 15 in common with the first cathode 102 and the second cathode 106.
The second type buried layer 12 has a third anode 121, the third anode 121 is disposed in a ring shape, and the third anode 121 is connected to the anode line 16 in common with the first anode 101 and the second anode 105. In the present embodiment, the first anode 101 and the second anode 105, the first cathode 102 and the second cathode 106, the first control electrode 103 and the second control electrode 107, the common control electrode 104, the third cathode 131 and the fourth cathode 132 are within the annular range of the third anode 121.
It can be understood that, since the third anode 121 leading out of the second type buried layer 12 is connected to the internal potential, the latch-up effect can be effectively avoided and the parasitic capacitance can be reduced.
The first control electrode 103 and the second control electrode 107 are connected to the first metal line 17 in common, the common control electrode 104 is connected to the second metal line 18, and the first metal line 17 and the second metal line 18 are respectively located at two sides of the common control electrode 104 in the second direction and respectively extend along the first direction. The anode wire 16 and the cathode wire 15 extend in the first direction and are located between the first wire 17 and the second wire 18.
The substrate 11 has an external electrode 111, the external electrode 111 is disposed around the third anode 121, and the external electrode 111 is grounded.
In this embodiment, the first type well 13 is a P-type well, and the second type well 14 is an N-type well; the common control electrode 104, the first cathode 102 and the second cathode 106 have N-type dopant ions, and the first anode 101, the second anode 105, the first control electrode 103 and the second control electrode 107 have P-type dopant ions.
Wherein the first cathode 102, the second well 14 and the first control electrode 103 form a first transistor Q1, the first anode 101, the second anode 105, the second well 14 and the first well 13 form a second transistor Q2, and the second cathode 106, the first well 13 and the second well 14 form a third transistor Q3; the first transistor Q1 and the second transistor Q2 may constitute a first silicon controlled rectifier, and the third transistor Q3 and the second transistor Q2 may constitute a second silicon controlled rectifier. A third resistor R3 is formed between the third cathode 131 and the first well 13, a fifth resistor R5 is formed between the fourth cathode 132 and the first well 13, and a fourth resistor R4 is formed between the first anode 101 or the second anode 105 and the anode metal line 16.
It should be noted that the first anode 101, the second well 14 and the first well 13 may form a second transistor Q2, and the second anode 105, the second well 14 and the first well 13 may form a second transistor Q2. Since the first anode 101 and the second anode 105 are both connected to the anode metal line 16, and the second well 14 and the first well 13 are also shared, the circuit formed by the first anode 101, the second anode 105, the second well 14, and the first well 13 can be represented by one second transistor Q2 in fig. 5 below, from the viewpoint of the formed circuit.
Referring to fig. 3, fig. 3 is a schematic layout diagram of a device structure in an electrostatic protection device according to an embodiment of the present invention.
The esd protection device 100 includes a silicon controlled rectifier (scr) group 10, a resistor-capacitor clamp 20, a second mos 30, a resistor 40, and at least one diode (such as a first diode D1, a second diode D2, and a third diode D3), which are arranged as shown in fig. 1. The resistor 40, the second metal oxide semiconductor 30 and the at least one diode are located on one side of the thyristor group 10, and the rc clamp 20 is located on the other side of the thyristor group 10.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of an electrostatic protection device according to an embodiment of the invention.
The rc clamp 20 includes a first mos 21 electrically connected to the scr set 10. The resistor 40 may include a first resistor R1 electrically connected to the diode and a second resistor R2 electrically connected to the second mos 30. The electrostatic protection circuit may further include a capacitor C electrically connected to the first resistor R1. The first Metal Oxide Semiconductor 21 may be a low voltage device, and the second Metal Oxide Semiconductor 30 may be a Laterally Diffused Metal Oxide Semiconductor (LDMOS) which is a high voltage device.
Taking three diodes (the first diode D1, the second diode D2, and the third diode D3) as an example, the three diodes constitute the electrostatic input module D, and the operation principle of the electrostatic protection circuit formed by the electrostatic protection device will be described with reference to the schematic diagram of the circuit.
The static input module D can simultaneously receive and process static released by one or more static release nodes, and the multiple static release nodes can share the same static protection circuit, so that the static release efficiency of the static protection circuit is improved; meanwhile, the occupied space or area of the electrostatic protection circuit of the equipment or the chip can be reduced.
A Silicon-Controlled Rectifier (SCR) group 10 is a semiconductor structure formed by a PNPN four-layer triple junction, and is one of ESD devices with extremely strong current capability. Therefore, the area of the electrostatic protection circuit provided by the application can be smaller under the condition of the same conductive current.
It should be noted that the silicon controlled rectifier group 10 and the first metal oxide semiconductor 21 can bear a larger voltage resistance when they are not triggered to conduct, and can be comparable to the high voltage resistance of an LDMOS or a Bipolar Junction Transistor (BJT).
It should be noted that, because the scr group 10 can bear a higher electrostatic voltage, and can bear a higher electrostatic voltage after being connected in series with the first metal oxide semiconductor 21, and the first metal oxide semiconductor 21 only needs to bear a lower electrostatic voltage, the voltage difference between the drain and the source of the first metal oxide semiconductor 21 is smaller during the electrostatic discharge. Therefore, the requirement on the pressure resistance of the first metal oxide semiconductor 21 is low, the normal low-voltage tube can meet the requirement on electrostatic discharge, and the occupied space or the occupied area of the low-voltage tube is smaller than that of the high-voltage tube, so that the occupied area of an electrostatic protection circuit or an electrostatic protection device can be reduced, and the area of a chip is further reduced.
In this embodiment, since the voltage resistance requirement of the first metal oxide semiconductor 21 is lower and the space area is smaller, the turn-on voltage required by the first metal oxide semiconductor 21 is lower, so that the response speed or the start-up speed of the electrostatic protection circuit provided by the present application can be improved. The characteristics of high voltage resistance of the silicon controlled rectifier group 10 and the characteristics of quick start of the resistance-capacitance clamping tube 20 are combined, so that the first metal oxide semiconductor 21 can adopt a low-voltage tube to replace a high-voltage tube.
As shown in fig. 4, when an ESD event occurs at least one anode of the first diode D1, the second diode D2, and the third diode D3, since the time constant of the first resistor R1 and the capacitor C is greater than the pulse time of the static electricity, the potential of the node N1 cannot change correspondingly with the potential of the node M1 in time, and at this time, the node M1 is at a high voltage level, and the node N1 is at a low voltage level, the second MOS 30 is turned on, further, the voltage level at the node N2 is pulled high, the first metal oxide semiconductor 21 is also conducted, and the voltage level at the node N1 and the voltage level at the node N2 trigger the SCR 10 to conduct, thus, a leakage path of static electricity is formed, the static electricity flows through the node M1, the node N3, the node N4 and the first metal oxide semiconductor 21 in sequence to introduce the ground line or the ground, thereby protecting the internal circuitry of the device or chip from over-voltage and/or over-current effects or damage.
As can be seen from fig. 3 and 4, in the electrostatic protection device provided by the embodiment of the present invention, the structural layout of each device is reasonable, and the current routing is smooth. In addition, since the scr set 10 can bear a higher electrostatic voltage, the first metal oxide semiconductor 21 only needs to bear a lower electrostatic voltage, that is, the first metal oxide semiconductor 21 can adopt a low voltage tube, thereby saving the area.
Referring to fig. 5, fig. 5 is a schematic circuit diagram of the scr group 10 according to the embodiment of the present invention.
The scr rectifier group 10 includes a third resistor R3, a first transistor Q1, a fourth resistor R4, a second transistor Q2, a fifth resistor R5, and a third transistor Q3. It should be noted that the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are all parasitic resistors.
The first transistor Q1 is an NPN bipolar junction transistor, the second transistor Q2 is a PNP bipolar junction transistor, and the third transistor Q3 is an NPN bipolar junction transistor. The collector of the first transistor Q1, the base of the second transistor Q2, and the collector of the third transistor Q3 are commonly connected to a node N1. The emitter of the first transistor Q1 and the emitter of the third transistor Q3 are both connected to the node N4. The base of the first transistor Q1, the collector of the second transistor Q2, and the base of the third transistor Q3 are commonly connected to a node N2. One end of the third resistor R3 is connected to the node N4, the other end is connected to the node N2, one end of the fifth resistor R5 is connected to the node N4, the other end is connected to the node N2, one end of the fourth resistor R4 is connected to the emitter of the second transistor Q2, and the other end is connected to the node N3.
As can be seen from fig. 1, 2 and 5, the node N4 is connected to the cathode line 15, and the node N3 is connected to the anode line 16. Node N1 is connected to second metal line 18 and node N2 is connected to first metal line 17.
The operation of the thyristor rectifier group 10 in the embodiment shown in fig. 5 is as follows:
normally, the node N1 is connected to the high potential of the node M1 through the first resistor R1, and the second transistor Q2 is in an off state; the node N2 is grounded through the third resistor R3 and the fifth resistor R5, and the first transistor Q1 and the third transistor Q3 are both in an off state.
When the node N3 receives the electrostatic pulse, the PN junction of the second transistor Q2 is broken down in reverse direction, and the third resistor R3 and the fifth resistor R5 flow through, so that the potential of the node N2 is raised, and finally the first transistor Q1 and the third transistor Q3 are turned on, the first transistor Q1 and the third transistor Q3 are turned on to reduce the potential of the node N1, the second transistor Q2 is gradually turned on, and the second transistor Q2 is turned on to further raise the potential of the node N2, and by this loop, the turning on process of the first transistor Q1, the second transistor Q2 and the third transistor Q3 is a positive feedback process, and the turning on degree of the two gradually approaches a saturated turning on state until finally, the first transistor Q1, the second transistor Q2 and the third transistor Q3 are all turned on completely to drain the electrostatic charge to the node N4.
Therefore, during the operation of the scr group 10 shown in fig. 5, the rising process of the potential at the node N2 to turn on the first transistor Q1 and the third transistor Q3 is a slow accumulation process. However, in the esd protection circuit provided in the present application, in response to the electrostatic pulse, the potential of the node N1 may be directly pulled down and the potential of the node N2 may be pulled up, so as to increase the on-speeds of the first transistor Q1, the second transistor Q2, and the third transistor Q3, and further improve the timeliness of discharging the electrostatic charge.
In this embodiment, the silicon controlled rectifier group 10 shown in fig. 5 forms a first silicon controlled rectifier and a second silicon controlled rectifier equivalent to a parallel connection by multiplexing the second transistor Q2, and thus, the current conducting capacity of the silicon controlled rectifier group 10 shown in fig. 5 is twice that of the first silicon controlled rectifier or the second silicon controlled rectifier. Meanwhile, under the condition of the same current conducting capacity, compared with the first silicon controlled rectifier or the second silicon controlled rectifier, the silicon controlled rectifier group 10 has a smaller area, and further the area of a chip can be further reduced under the condition of higher current conducting capacity. Therefore, in the electrostatic protection device provided by the embodiment of the invention, the silicon controlled rectifier group 10 has a special layout structure, a small area and a high voltage withstanding value.
Referring to fig. 6, fig. 6 is a schematic top view of a diode according to an embodiment of the invention.
The first diode D1, the second diode D2, and the third diode D3 are the same structure, and fig. 6 shows a structure of one of the diodes, each of which includes: a negative electrode 41 and a first electrode 42 positioned on the negative electrode 41, the negative electrode 41 and the first electrode 42 having a rectangular shape in plan view; a positive electrode 43, and a second electrode 441 and a third electrode 442 located on the positive electrode 43, the positive electrode 43 surrounding the negative electrode 41. The cathode 41 may be an N-type doped region, and the anode 43 may be a P-type doped region.
In the embodiment, the negative electrode 41 and the positive electrode 43 have a long-side pitch and a short-side pitch, and the ratio of the long-side pitch S1 to the short-side pitch S2 is 1: 1.5-1: 2. Because the long edge distance S1 is smaller, the current can preferentially run on the long edge, the resistance is smaller, and the current bearing capacity of the diode is improved.
The second electrode 441 and the third electrode 442 are located on both sides of the first electrode 42, and have rectangular shapes in plan view. The first electrode 42, the second electrode 441 and the third electrode 442 are led out through the contact 45 to be connected to an external circuit.
In the present embodiment, the short sides of the second electrode 441 and the third electrode 442 are aligned with the short sides of the first electrode 42, so that the number of the contacts 45 on the second electrode 441 or the third electrode 442 and the first electrode 42 can be the same, and thus the current flowing from the second electrode 441 or the third electrode 442 to the first electrode 42 can be relatively uniform, thereby improving the current-carrying capacity and stability of the diode.
Referring to fig. 7, fig. 7 is a schematic top view of the first metal oxide semiconductor 21 according to the embodiment of the present invention.
The first Metal-Oxide-Semiconductor 21 includes a plurality of MOS (Metal-Oxide-Semiconductor) transistors connected in parallel, and the specific structure thereof is shown in fig. 7. The first metal oxide semiconductor 21 includes: a second type doping region 211 and a first type doping region 212 surrounding the second type doping region 211, wherein the second type doping region 211 has a rectangular shape in a plan view. The second-type doped region 211 may be an N-type doped region, and the first-type doped region 212 may be a P-type doped region.
The second-type doped region 211 and the first-type doped region 212 have a short-side distance S1 and a long-side distance S2, and the ratio of the short-side distance S1 to the long-side distance S2 is 1: 1.5-1: 2.
The second type doping region 211 has a plurality of source S and drain D formed therein and alternately arranged along the long side of the second type doping region 211, the number of the plurality of source S is even, and two source S are respectively located at two ends of the second type doping region 211, i.e. the source S is close to the first type doping region 212, so as to reduce the parasitic capacitance C.
The first metal oxide semiconductor 21 further includes: a plurality of gates 213 disposed on the second type doping region 211, each gate 213 being disposed between a source S and a drain D; two gate lines 214 located between the second type doping region 211 and the first type doping region 212 and extending along the long side of the second type doping region 211, wherein two ends of each gate 213 are respectively connected to the two gate lines 214. The line width of the gate line 214 is greater than or equal to 1 micron, and both ends of the gate 213 are connected to the gate line 214, so that the turn-on time of the MOS transistors can be as consistent as possible.
The embodiment of the invention provides an electrostatic protection device, wherein the layout structure of a silicon controlled rectifier group 10 in the electrostatic protection device has the characteristics of small area, special structure, high voltage withstanding value and the like, and the voltage withstanding capability of the electrostatic protection device is improved.
An embodiment of the present invention provides a chip, including the electrostatic protection device in the above embodiments, where the chip has the same beneficial effects as the electrostatic protection device, and details are not repeated here.
The above description of the embodiments is only for helping understanding the technical solution of the present invention and its core idea; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (18)
1. An electrostatic discharge protection device, comprising a silicon controlled rectifier set, the silicon controlled rectifier set comprising: the silicon controlled rectifier comprises a first silicon controlled rectifier and a second silicon controlled rectifier, wherein the first silicon controlled rectifier comprises a first anode, a first cathode, a first control electrode and a common control electrode which are positioned in a substrate, and the second silicon controlled rectifier comprises a second anode, a second cathode, a second control electrode and the common control electrode which are positioned in the substrate;
wherein the substrate comprises a first well and a second well within the first well;
the common control electrode, the first anode and the second anode are located in the second type well;
the first cathode and the first gate, and the second cathode and the second gate are located in the first well.
2. The ESD device of claim 1 wherein the first control electrode, the first cathode, the first anode, the common control electrode, the second anode, the second cathode, and the second control electrode are arranged in series along a first direction.
3. The ESD device of claim 2 wherein the first well has a third cathode and a fourth cathode juxtaposed with the first and second gates, respectively, and outside the first and second gates relative to the common gate; the third cathode and the fourth cathode and the first cathode and the second cathode are connected with a cathode metal wire in common.
4. The ESD device of claim 3 wherein the substrate further comprises a second type buried layer, the first type well is in an orthographic projection of the second type buried layer, the second type buried layer has a third anode, the third anode is disposed in a ring shape, and the third anode is connected to the anode metal line in common with the first anode and the second anode.
5. The ESD device of claim 4 wherein the first and second anodes, the first and second cathodes, the first and second gates, the common gate, the third cathode, and the fourth cathode are within an annular extent of the third anode.
6. The electrostatic protection device of claim 4, wherein the first gate and the second gate are commonly connected to a first metal line, and the common gate is connected to a second metal line.
7. The ESD device of claim 6 wherein the anode metal line and the cathode metal line extend along the first direction and are respectively located between the first metal line and the second metal line.
8. The ESD device of claim 4 wherein the substrate has an external electrode disposed around the third anode and the external electrode is grounded.
9. The electrostatic protection device of claim 1, wherein the first well is a P-type well and the second well is an N-type well; the common control electrode, the first cathode and the second cathode have N-type dopant ions, and the first anode, the second anode, the first control electrode and the second control electrode have P-type dopant ions.
10. The ESD device of claim 9 wherein the first cathode, the second well, and the first control electrode comprise a first transistor, the first anode, the second well, and the first well comprise a second transistor, and the second cathode, the first well, and the second well comprise a third transistor; the first transistor and the second transistor constitute the first silicon controlled rectifier, and the second transistor and the third transistor constitute the second silicon controlled rectifier.
11. The ESD device of claim 1 further comprising a RC clamp and at least one diode, wherein the SCR set is arranged between the at least one diode and the RC clamp, and the RC clamp and the at least one diode are electrically connected to the SCR set via a metal wire.
12. The electrostatic protection device of claim 11, wherein each of said diodes comprises:
the cathode and the first electrode are rectangular in plan view;
a positive electrode and a second electrode and a third electrode positioned on the positive electrode, the positive electrode surrounding the negative electrode;
the negative electrode and the positive electrode are arranged at a long edge interval and a short edge interval, and the ratio of the long edge interval to the short edge interval is 1: 1.5-1: 2.
13. The electrostatic protection device according to claim 12, wherein the second electrode and the third electrode are located on both sides of the first electrode and are rectangular in plan view;
wherein short sides of the second and third electrodes are aligned with short sides of the first electrode.
14. The esd protection device of claim 11, wherein the rc clamp comprises a first metal oxide semiconductor electrically connected to the scr set, the first metal oxide semiconductor comprising:
the planar light source comprises a second type doping area and a first type doping area surrounding the second type doping area, wherein the overlooking shape of the second type doping area is rectangular;
the second type doping area and the first type doping area are arranged between the first type doping area and the second type doping area, a short edge distance and a long edge distance are arranged between the second type doping area and the first type doping area, and the ratio range of the short edge distance to the long edge distance is 1: 1.5-1: 2.
15. The ESD device of claim 14 wherein the second-type doped region has a plurality of source and drain electrodes formed therein and arranged alternately along a long side of the second-type doped region, the number of the source electrodes is even, and two source electrodes are respectively disposed at two ends of the second-type doped region.
16. The electrostatic protection device of claim 15, wherein the first metal oxide semiconductor further comprises:
a plurality of gates located on said second type doped region, each said gate located between one said source and one said drain;
and the two gate lines are positioned between the second type doping area and the first type doping area and extend along the long edge of the second type doping area, and two ends of each gate are respectively connected with the two gate lines.
17. The esd protection device of claim 11, further comprising a second metal oxide semiconductor and a resistor electrically connected to the at least one diode, the second metal oxide semiconductor, the resistor, and the at least one diode being located on a same side of the scr group.
18. A chip comprising an electrostatic protection device as claimed in any one of claims 1 to 17.
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| CN100550368C (en) * | 2007-03-01 | 2009-10-14 | 和舰科技(苏州)有限公司 | A kind of thyristor of protecting static discharge |
| CN103606548B (en) * | 2013-12-09 | 2016-07-20 | 江南大学 | A kind of high-voltage ESD protective device of little time stagnant SCR structure of Zener breakdown |
| CN103681660B (en) * | 2013-12-13 | 2015-12-30 | 江南大学 | A kind of high-voltage ESD protective device of annular LDMOS-SCR structure of dual latch-up |
| CN105556667B (en) * | 2015-09-08 | 2018-09-18 | 香港应用科技研究院有限公司 | Transverse diode for high HBM ESD protective capabilities and vertical SCR mixed structures |
| CN105633074B (en) * | 2016-03-10 | 2019-01-22 | 湖南静芯微电子技术有限公司 | A kind of bidirectional triode thyristor device triggered by back biased diode |
| US10249609B2 (en) * | 2017-08-10 | 2019-04-02 | Analog Devices, Inc. | Apparatuses for communication systems transceiver interfaces |
| CN108807371B (en) * | 2018-06-07 | 2019-07-09 | 湘潭大学 | A kind of high-protection level bidirectional thyristor electrostatic protection device and preparation method thereof |
| CN111725201B (en) * | 2019-03-20 | 2023-03-24 | 中芯国际集成电路制造(上海)有限公司 | SCR electrostatic protection structure and forming method thereof |
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