CN216595483U - DC Doppler radar calibrating device - Google Patents
DC Doppler radar calibrating device Download PDFInfo
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- CN216595483U CN216595483U CN202122889285.7U CN202122889285U CN216595483U CN 216595483 U CN216595483 U CN 216595483U CN 202122889285 U CN202122889285 U CN 202122889285U CN 216595483 U CN216595483 U CN 216595483U
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- 239000003990 capacitor Substances 0.000 claims description 15
- 238000005070 sampling Methods 0.000 claims description 13
- 101150042711 adc2 gene Proteins 0.000 claims description 12
- 101100434411 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ADH1 gene Proteins 0.000 claims description 7
- 101150102866 adc1 gene Proteins 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000012935 Averaging Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
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Abstract
The utility model discloses a direct current Doppler radar calibration device which limits Doppler intermediate frequency signals within an input range and comprises a filter circuit, a voltage follower circuit, an amplifying circuit and a processor, wherein the Doppler intermediate frequency signals are input into the input end of the filter circuit, and the output end of the filter circuit is electrically connected with the input end of the voltage follower circuit. Compared with an alternating current amplifying circuit, the direct current amplifying circuit can measure signals with lower frequency, and the amplified intermediate frequency is limited within the input range of an ADC (analog to digital converter) through direct current calibration.
Description
Technical Field
The utility model belongs to the technical field of radar calibration, and particularly relates to a direct current Doppler radar calibration device.
Background
Due to the receiving and transmitting isolation characteristic, the Doppler radar can generate direct current output at intermediate frequency output, and the output is the superposition of direct current and Doppler frequency shift. The radar intermediate frequency processing needs to amplify the Doppler frequency and send the Doppler frequency to ADC sampling processing. The doppler shift is usually amplified by ac coupling while isolating the dc output from the radar. But ac amplification also suppresses the doppler signal near the dc portion. According to the characteristic of the Doppler signal, the higher the moving speed of the target is, the higher the frequency is. However, if an ultra-low speed moving target needs to be detected, the radar is required to be incapable of suppressing the ultra-low frequency doppler shift, and a direct current coupling amplifying circuit needs to be adopted. However, the dc-coupled amplifier circuit will also amplify the dc current, and the output voltage will far exceed the input range of the ADC.
Therefore, the above problems are further improved.
SUMMERY OF THE UTILITY MODEL
The utility model mainly aims to provide a direct current Doppler radar calibration device, compared with an alternating current amplification circuit, the direct current amplification circuit can measure signals with lower frequency, and the amplified intermediate frequency is limited within the input range of an ADC (analog to digital converter) through direct current calibration.
Another objective of the present invention is to provide a calibration apparatus for dc doppler radar, wherein the processor also periodically collects signals from the ADC2, and if the average value of the ADC2 exceeds the set bias voltage range, the output of the DAC is adjusted to maintain the intermediate frequency dc.
In order to achieve the above object, the present invention provides a calibration apparatus for a direct current doppler radar, which limits a doppler intermediate frequency signal within an input range, and includes a filter circuit, a voltage follower circuit, an amplifier circuit, and a processor, wherein:
the input end of the filter circuit inputs a Doppler intermediate frequency signal, and the output end of the filter circuit is electrically connected with the input end of the voltage follower circuit;
the first output end of the voltage follower circuit is electrically connected with the sampling end ADC1 of the processor, and the second output end of the voltage follower circuit is electrically connected with the first input end of the amplifying circuit;
the output end of the amplifying circuit is electrically connected with the sampling end ADC2 of the processor, and the transmission end DAC of the processor is electrically connected with the second input end of the amplifying circuit.
As a further preferable technical solution of the above technical solution, the filter circuit includes a resistor R10 and a capacitor C5, and the voltage follower circuit includes a voltage follower U1A, wherein:
one end of the resistor R10 is connected with a Doppler intermediate frequency signal, the other end of the resistor R10 is electrically connected with the positive input end of the voltage follower U1A, and the positive input end of the voltage follower U1A is also grounded through a capacitor C5;
a resistor R8 is connected between the negative electrode input end and the output end of the voltage follower U1A, and the output end of the voltage follower U1A is connected with a sampling end ADC1 of the processor through a resistor R5.
As a further preferable technical solution of the above technical solution, the amplifying circuit includes an operational amplifier U1B, wherein:
the output end of the voltage follower U1A is electrically connected with the positive input end of the operational amplifier U1B through a resistor R11 and a resistor R12 in sequence;
a capacitor C2 is connected between the negative input end and the output end of the operational amplifier U1B, two ends of the capacitor C2 are connected with a resistor R7 in parallel, and the output end of the operational amplifier U1B is connected with a sampling end ADC2 of the processor through a resistor R31;
the negative electrode input end of the operational amplifier U1B is electrically connected with the transmission end DAC of the processor sequentially through a resistor R9 and a resistor R6, the common connection end of the resistor R6 and the resistor R9 is grounded through a capacitor C1 and grounded through a resistor R34, and the resistor R6 and the resistor R34 form a voltage division circuit (voltage division is performed on DAC output voltage so that the accuracy of the DAC output voltage is improved).
As a further preferable technical solution of the above technical solution, the positive input terminal of the operational amplifier U1B is connected to a direct current bias (VREF) through a resistor R13, and the direct current bias (VREF) is a voltage dividing circuit composed of a resistor R14 and a resistor R15.
Drawings
Fig. 1 is a schematic structural diagram of a dc doppler radar calibration apparatus according to the present invention.
Fig. 2 is a circuit diagram of the dc doppler radar calibration apparatus of the present invention.
Detailed Description
The following description is presented to disclose the utility model so as to enable any person skilled in the art to practice the utility model. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the utility model, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the utility model.
The utility model discloses a direct current Doppler radar calibration device, and the specific embodiment of the utility model is further described below by combining the preferred embodiment.
In the embodiments of the present invention, those skilled in the art note that the doppler intermediate frequency signal and radar, etc. related to the present invention can be regarded as the prior art.
Preferred embodiments.
The utility model discloses a direct current Doppler radar calibration device, which limits Doppler intermediate frequency signals within an input range and comprises a filter circuit, a voltage follower circuit, an amplifying circuit and a processor, wherein:
the input end of the filter circuit inputs a Doppler intermediate frequency signal, and the output end of the filter circuit is electrically connected with the input end of the voltage follower circuit;
the first output end of the voltage follower circuit is electrically connected with the sampling end ADC1 of the processor, and the second output end of the voltage follower circuit is electrically connected with the first input end of the amplifying circuit;
the output end of the amplifying circuit is electrically connected with the sampling end ADC2 of the processor, and the transmission end DAC of the processor is electrically connected with the second input end of the amplifying circuit.
Specifically, the filter circuit comprises a resistor R10 and a capacitor C5, and the voltage follower circuit comprises a voltage follower U1A, wherein:
one end of the resistor R10 is connected with a Doppler intermediate frequency signal, the other end of the resistor R10 is electrically connected with the positive input end of the voltage follower U1A, and the positive input end of the voltage follower U1A is also grounded through a capacitor C5;
a resistor R8 is connected between the negative electrode input end and the output end of the voltage follower U1A, and the output end of the voltage follower U1A is connected with a sampling end ADC1 of the processor through a resistor R5.
More specifically, the amplifying circuit includes an op amp U1B, wherein:
the output end of the voltage follower U1A is electrically connected with the positive input end of the operational amplifier U1B through a resistor R11 and a resistor R12 in sequence;
a capacitor C2 is connected between the negative input end and the output end of the operational amplifier U1B, two ends of the capacitor C2 are connected with a resistor R7 in parallel, and the output end of the operational amplifier U1B is connected with a sampling end ADC2 of the processor through a resistor R31;
the negative electrode input end of the operational amplifier U1B is electrically connected with the transmission end DAC of the processor sequentially through a resistor R9 and a resistor R6, the common connection end of the resistor R6 and the resistor R9 is grounded through a capacitor C1 and grounded through a resistor R34, and the resistor R6 and the resistor R34 form a voltage division circuit (voltage division is performed on DAC output voltage so that the accuracy of the DAC output voltage is improved).
Further, the positive input terminal of the operational amplifier U1B is connected to a dc bias (VREF) through a resistor R13, and the dc bias (VREF) is a voltage dividing circuit formed by a resistor R14 and a resistor R15 and is set to be half of the supply voltage (output terminal VCC33_ OUT).
Preferably, the principle of the utility model is as follows:
the circuit comprises 4 parts, radar Doppler output enters a voltage following circuit through a filter circuit, the voltage following output is sampled through an ADC2 on an MCU (micro controller unit) after passing through a direct current amplifying circuit, and the frequency of Doppler intermediate frequency is calculated.
After the radar is powered on, the ADC1 of the MCU firstly samples the voltage on the follower circuit, obtains the direct current voltage of Doppler intermediate frequency after averaging, and outputs the voltage to the amplifying circuit through the DAC on the MCU. Because the following amplifier can generate voltage error, the output of the amplifying circuit can not ensure that the direct current bias is near VREF at the moment, but the circuit is in a normal working state at the moment. So we need further calibration. At this time, the ADC2 is turned on, the dc offset voltage output by the amplifying circuit is calculated by averaging, and the adjustment voltage value of the DAC is calculated to achieve the purpose of offset calibration.
DAC adjustment formula:
Vdacnew＝2*(Vadc2-Vref)/A+Vdacold；
wherein, a is the gain of the amplifying circuit, Vadc2 is the current intermediate frequency direct current voltage, Vref is the target bias voltage, Vdacold is the current DAC voltage, and Vdacnew is the adjustment voltage.
The dc offset of the doppler intermediate frequency varies slightly with temperature and environment. Even this slight variation causes the amplification circuit to enter a saturation state. The MCU also periodically collects the signal from the ADC2, and if the average value of the ADC2 exceeds the set offset voltage range, the output of the DAC is adjusted to maintain the intermediate frequency dc.
It should be noted that the technical features of the doppler intermediate frequency signal and the radar, etc. related to the present patent application should be regarded as the prior art, and the specific structure, the operation principle, the control mode and the spatial arrangement mode of the technical features may be selected conventionally in the field, and should not be regarded as the utility model point of the present patent, and the present patent is not further specifically described in detail.
It will be apparent to those skilled in the art that modifications and equivalents may be made in the embodiments and/or portions thereof without departing from the spirit and scope of the present invention.
Claims (4)
1. A direct current Doppler radar calibration device limits Doppler intermediate frequency signals within an input range, and is characterized by comprising a filter circuit, a voltage follower circuit, an amplifying circuit and a processor, wherein:
the input end of the filter circuit inputs a Doppler intermediate frequency signal, and the output end of the filter circuit is electrically connected with the input end of the voltage follower circuit;
the first output end of the voltage follower circuit is electrically connected with the sampling end ADC1 of the processor, and the second output end of the voltage follower circuit is electrically connected with the first input end of the amplifying circuit;
the output end of the amplifying circuit is electrically connected with the sampling end ADC2 of the processor, and the transmission end DAC of the processor is electrically connected with the second input end of the amplifying circuit.
2. The calibration apparatus according to claim 1, wherein the filter circuit comprises a resistor R10 and a capacitor C5, and the voltage follower circuit comprises a voltage follower U1A, wherein:
one end of the resistor R10 is connected with a Doppler intermediate frequency signal, the other end of the resistor R10 is electrically connected with the positive input end of the voltage follower U1A, and the positive input end of the voltage follower U1A is also grounded through a capacitor C5;
a resistor R8 is connected between the negative electrode input end and the output end of the voltage follower U1A, and the output end of the voltage follower U1A is connected with a sampling end ADC1 of the processor through a resistor R5.
3. The apparatus of claim 2, wherein the amplifying circuit comprises an op amp U1B, wherein:
the output end of the voltage follower U1A is electrically connected with the positive input end of the operational amplifier U1B through a resistor R11 and a resistor R12 in sequence;
a capacitor C2 is connected between the negative input end and the output end of the operational amplifier U1B, two ends of the capacitor C2 are connected with a resistor R7 in parallel, and the output end of the operational amplifier U1B is connected with a sampling end ADC2 of the processor through a resistor R31;
the negative electrode input end of the operational amplifier U1B is electrically connected with the transmission end DAC of the processor sequentially through a resistor R9 and a resistor R6, the common connection end of the resistor R6 and the resistor R9 is grounded through a capacitor C1 and is grounded through a resistor R34, and the resistor R6 and the resistor R34 form a voltage division circuit.
4. The calibration device for the direct current Doppler radar according to claim 3, wherein a positive input end of the operational amplifier U1B is connected with a direct current bias through a resistor R13, and the direct current bias is composed of a resistor R14 and a resistor R15 to form a voltage division circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122889285.7U CN216595483U (en) | 2021-11-23 | 2021-11-23 | DC Doppler radar calibrating device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122889285.7U CN216595483U (en) | 2021-11-23 | 2021-11-23 | DC Doppler radar calibrating device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216595483U true CN216595483U (en) | 2022-05-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122889285.7U Active CN216595483U (en) | 2021-11-23 | 2021-11-23 | DC Doppler radar calibrating device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216595483U (en) |
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2021
- 2021-11-23 CN CN202122889285.7U patent/CN216595483U/en active Active
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: No. 0459, Unit 209, No. 62 Chengyi North Street, Software Park Phase III, Torch High tech Zone, Xiamen City, Fujian Province, 361000 Patentee after: Sijie Microelectronics (Xiamen) Co.,Ltd. Address before: 201800 room j461, building 6, 1288 Yecheng Road, Jiading District, Shanghai Patentee before: SHANGHAI SILICON MICROELECTRONICS Co.,Ltd. |
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| CP03 | Change of name, title or address |