CN210745091U

CN210745091U - Signal acquisition circuit

Info

Publication number: CN210745091U
Application number: CN202020014520.9U
Authority: CN
Inventors: 李涛
Original assignee: Individual
Current assignee: Individual
Priority date: 2020-01-06
Filing date: 2020-01-06
Publication date: 2020-06-12
Anticipated expiration: 2030-01-06

Abstract

The utility model discloses a signal acquisition circuit, including sensor interface, input channel conditioning circuit, ADC converter, FPGA and industrial computer, the sensor is connected to sensor interface's input to loop through the signal that the sensor was gathered input channel conditioning circuit, ADC converter send for FPGA, FPGA pass through the PCIE interface with the industrial computer communication, FPGA adjusts input channel conditioning circuit carries out corresponding processing through input channel conditioning circuit to the dynamic signal that the sensor was gathered, thereby has improved measurement accuracy.

Description

Signal acquisition circuit

Technical Field

The utility model relates to a signal acquisition circuit.

Background

The dynamic signal analyzer is always a main testing instrument for noise and vibration analysis, modal analysis and acoustic testing, and is widely applied to the fields of aerospace, machinery, environment, biomedical treatment and the like. The dynamic signal analyzer well integrates multiple functions of signal generation, signal acquisition, signal analysis and processing and the like, and can analyze physical quantity characteristics represented by the detected electric signal in a time domain, a frequency domain and an amplitude domain. However, the current dynamic signal acquisition circuit generally only acquires signals through the sensor and then transmits the signals to the processor through analog-to-digital conversion, and the signals acquired by the sensor are not processed, so that the technical problem that the signals received by the processor are inaccurate and data errors exist.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome the technical problem who exists more than, provide a signal acquisition circuit.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

a signal acquisition circuit comprises a sensor interface, an input channel conditioning circuit, an ADC (analog to digital converter), an FPGA (field programmable gate array) and an industrial personal computer, wherein the input end of the sensor interface is connected with a sensor, and signals acquired by the sensor are sent to the FPGA through the input channel conditioning circuit and the ADC in sequence, the FPGA communicates with the industrial personal computer through a PCIE (peripheral component interface express) interface, and the FPGA adjusts the input channel conditioning circuit.

Furthermore, the input channel conditioning circuit comprises a gain/attenuation adjusting circuit, a direct current bias circuit, a trap circuit and an overload detection circuit, wherein the gain/attenuation adjusting circuit is used for carrying out elastic amplitude stabilization processing on the amplitude of the signal input by the sensor interface so as to enable the amplitude of the input signal to reach the optimal range of conversion before the input signal enters the ADC converter, and sending the signal to the direct current bias circuit; the direct current bias circuit is used for compensating the direct current bias of an input signal and sending the signal to the trap circuit; the trap circuit is used for effectively inhibiting power frequency interference and sending the signal to the ADC; the ADC converts the received signals into digital signals and then sends the digital signals to the FPGA; the overload detection circuit is used for monitoring the amplitude of an input signal, if the input signal exceeds the range specified by the analog input channel, the overload detection circuit transmits information to the FPGA, and the FPGA adjusts the gain/attenuation adjusting circuit to enable the amplitude of the input signal to meet the input requirement.

Further, the direct current bias circuit comprises a reference voltage source used for driving a reference input, a DAC, a first operational amplifier and a second operational amplifier, wherein an output pin of the reference voltage source is connected with 2 pins of the DAC, 8 pins of the DAC are connected with 2 pins of the first operational amplifier, and 1 pin of the first operational amplifier is connected with 6 pins of the second operational amplifier.

Further, the model of the reference voltage source is ADR 02.

Further, the model of the DAC is AD 5452.

Further, the model of the first operational amplifier and the second operational amplifier is AD 8066.

The utility model discloses an input channel conditioning circuit carries out corresponding processing to the dynamic signal that the sensor gathered to measurement accuracy has been improved.

Drawings

FIG. 1: the utility model relates to a circuit structure block diagram of signal acquisition circuit.

FIG. 2: a circuit block diagram of an input channel conditioning circuit.

FIG. 3: a circuit schematic of a dc bias circuit.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings and examples.

Example one

As shown in fig. 1, a signal acquisition circuit is applied to a dynamic signal analyzer device, and is used for acquiring a signal to the dynamic signal analyzer device for processing and analysis, and specifically includes a sensor interface, an input channel conditioning circuit, an ADC converter, an FPGA, and an industrial personal computer.

The input end of the sensor interface is connected with a sensor, signals (such as noise signals, vibration signals and the like) collected by the sensor are input to the sensor interface, and the input signals are transmitted to the input channel conditioning circuit by the sensor interface.

The input channel conditioning circuit is mainly used for processing an input signal, and as shown in fig. 2, the input channel conditioning circuit includes a gain/attenuation adjusting circuit, a dc bias circuit, a trap circuit, and an overload detecting circuit.

The adjusting gain/attenuation adjusting circuit is mainly used for carrying out elastic amplitude stabilization processing on the amplitude of the signal input by the sensor interface so that the amplitude of the input signal reaches the optimal range of conversion before entering the ADC converter, and the signal is sent to the direct current bias circuit.

The direct current bias circuit is mainly used for compensating the direct current bias of an input signal and sending the signal to the trap circuit;

the trap circuit has the main functions that when the dynamic signal analyzer equipment uses AC200V for power supply, the trap circuit can effectively suppress 50Hz power frequency interference and send the signal to the ADC;

the ADC converts the received signals into digital signals and then sends the digital signals to the FPGA;

the overload detection circuit is mainly used for monitoring the amplitude of an input signal, if the input signal exceeds the range specified by the analog input channel, the overload detection circuit transmits information to the FPGA, and the FPGA adjusts the gain/attenuation adjusting circuit to enable the amplitude of the input signal to meet the input requirement.

The FPGA communicates with the industrial personal computer through a PCIE interface,

as shown in fig. 3, the dc bias circuit mainly includes a reference voltage source for driving a reference input, a DAC, a first operational amplifier, and a second operational amplifier, wherein an output pin of the reference voltage source is connected to 2 pins of the DAC, 8 pins of the DAC are connected to 2 pins of the first operational amplifier, and 1 pin of the first operational amplifier is connected to 6 pins of the second operational amplifier.

The DAC in the direct current bias circuit is a core component, a signal is AD5453, the direct current bias circuit is a 14-bit current output type multiplying DAC, a 5V COMS process design is adopted, and the direct current bias circuit has the main advantages that the input range of the AD5453 is as high as 10V and can exceed 5V power supply voltage.

The model of the reference voltage source is ADR02, and ADR02 is a high-precision and high-stability voltage source which can provide a reference voltage of 5V.

The DC bias circuit adopts two stages of operational amplifiers, wherein the first operational amplifier realizes the conversion from the output current of the DAC to the voltage, and the second operational amplifier provides twice gain for the output signal. The model of the first operational amplifier and the second operational amplifier is AD 8066.

Finally, it should be noted that: the above embodiments are only used for illustrating the present invention and do not limit the technical solution described in the present invention; thus, while the present invention has been described in detail with reference to the various embodiments thereof, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted; all such modifications and variations are intended to be included herein within the scope of this disclosure and the present invention and within the scope and spirit of the following claims.

Claims

1. A signal acquisition circuit, characterized by: the input end of the sensor interface is connected with the sensor, signals collected by the sensor are sequentially sent to the FPGA through the input channel conditioning circuit and the ADC, the FPGA communicates with the industrial personal computer through the PCIE interface, and the FPGA adjusts the input channel conditioning circuit.

2. The signal acquisition circuit of claim 1, wherein: the input channel conditioning circuit comprises a gain/attenuation adjusting circuit, a direct current bias circuit, a trap circuit and an overload detection circuit, wherein the gain/attenuation adjusting circuit is used for carrying out elastic amplitude stabilization processing on the amplitude of a signal input by the sensor interface so as to enable the amplitude of the input signal to reach the optimal range of the conversion before the input signal enters the ADC converter, and sending the signal to the direct current bias circuit; the direct current bias circuit is used for compensating the direct current bias of an input signal and sending the signal to the trap circuit; the trap circuit is used for effectively inhibiting power frequency interference and sending the signal to the ADC; the ADC converts the received signals into digital signals and then sends the digital signals to the FPGA; the overload detection circuit is used for monitoring the amplitude of an input signal, if the input signal exceeds the range specified by the analog input channel, the overload detection circuit transmits information to the FPGA, and the FPGA adjusts the gain/attenuation adjusting circuit to enable the amplitude of the input signal to meet the input requirement.

3. The signal acquisition circuit of claim 2, wherein: the direct current bias circuit comprises a reference voltage source used for driving reference input, a DAC, a first operational amplifier and a second operational amplifier, wherein the output pin of the reference voltage source is connected with the pin 2 of the DAC, the pin 8 of the DAC is connected with the pin 2 of the first operational amplifier, and the pin 1 of the first operational amplifier is connected with the pin 6 of the second operational amplifier.

4. The signal acquisition circuit of claim 3, wherein: the model of the reference voltage source is ADR 02.

5. The signal acquisition circuit of claim 3, wherein: the DAC is AD5452 in model.

6. The signal acquisition circuit of claim 3, wherein: the model of the first operational amplifier and the second operational amplifier is AD 8066.