CN212258938U - Signal acquisition circuit - Google Patents
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- CN212258938U CN212258938U CN202021534049.2U CN202021534049U CN212258938U CN 212258938 U CN212258938 U CN 212258938U CN 202021534049 U CN202021534049 U CN 202021534049U CN 212258938 U CN212258938 U CN 212258938U
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Abstract
The utility model discloses a signal acquisition circuit relates to sensing technical field, and it includes sensor, constant current or constant voltage circuit, multistage voltage stabilizing circuit and gain amplifier circuit and filter circuit, wherein, multistage voltage stabilizing circuit's output is connected to constant current or constant voltage circuit's input, constant current or constant voltage circuit do the sensor power supply, the output of sensor is connected to outside signal receiver through gain amplifier circuit and filter circuit. The utility model discloses a programme-controlled gain amplifier circuit of high input impedance can match with the output impedance of prevailing most sensor to can pass through program control gain factor, for the signal source that the back stage circuit provided suitable amplitude, multistage voltage stabilizing circuit and filter circuit can improve the job stabilization nature suppression interference of sensor, further improve the signal acquisition precision.
Description
Technical Field
The utility model relates to a sensor technical field, concretely relates to signal acquisition circuit based on sensor.
Background
In a common detection device or detection system, the performance of the signal processing circuit itself has an important influence on the detection capability of the sensor. For example, when the sensor outputs a weak electrical signal, the sensor is easily interfered by other noises; when the output impedance of the sensor is relatively large, the sensor signal can generate relatively large signal attenuation when being input into the measurement conversion circuit; in addition, the stability of the power supply circuit of the entire signal processing circuit also has a large influence on the detection signal conversion accuracy.
SUMMERY OF THE UTILITY MODEL
In order to overcome the deficiency of the prior art, the utility model aims to provide a signal acquisition circuit, its programme-controlled gain amplifier circuit through high input impedance can match with the output impedance of current most sensor to can be through the program control gain factor, for the signal source that the back stage circuit provided suitable amplitude, multistage voltage stabilizing circuit and filter circuit can improve the job stabilization nature suppression interference of sensor, further improve the signal acquisition precision.
The purpose of the utility model is realized by adopting the following technical scheme:
a signal acquisition circuit comprises a sensor, a constant-current or constant-voltage circuit, a multi-stage voltage stabilizing circuit, a gain amplifying circuit and a filter circuit, wherein the output end of the multi-stage voltage stabilizing circuit is connected to the input end of the constant-current or constant-voltage circuit, the constant-current or constant-voltage circuit supplies power to the sensor, and the output end of the sensor is connected to an external signal receiver through the gain amplifying circuit and the filter circuit.
As a preferred embodiment, the constant current or constant voltage circuit comprises a chip U6, a resistor R12, a resistor R7, a PNP triode Q2, a PMOS transistor Q10, and a resistor R13, wherein the chip U6 is an XTR111, and an input terminal of the chip U6 is connected to an output terminal of the multi-stage voltage stabilizing circuit through the resistor R12; the output end of the chip U6 is connected to an emitter of a PNP triode Q2, the base of the PNP triode Q2 is connected to the source of a PMOS tube Q10, the gate driving pole of the chip U6 is connected to the gate of a PMOS tube Q10, the collector of the PNP triode Q2 is connected between the gate of the PMOS tube Q10 and the gate driving pole of the chip U6, two ends of the resistor R7 are respectively connected to the emitter and the base of the PNP triode Q2, and the drain of the PMOS tube Q10 is connected to the power supply end of the sensor through the resistor R13.
As a preferred embodiment, the gain amplifying circuit includes a chip U25 and a common mode inductor, the chip U25 is a PGA280, two input terminals of the common mode inductor are respectively connected to the positive output terminal and the negative output terminal of the sensor, two output terminals of the common mode inductor are respectively connected to the positive input terminal and the negative input terminal of a chip U25, and an output terminal of the chip U25 is connected to the filter circuit.
As a preferred embodiment, the filtering circuit comprises a filtering sub-circuit and an impedance transformation sub-circuit, an input terminal of the filtering sub-circuit is connected to an output terminal of the chip U25, and an output terminal of the filtering sub-circuit is connected to the signal receiver via the impedance transformation sub-circuit.
As a preferred embodiment, the filtering sub-circuit includes a resistor R49, a resistor R50, and one or more parallel filtering capacitors, one end of the resistor R49 and one end of the resistor R50 are respectively connected to the positive output end and the negative output end of the chip U25, and the other end of the resistor R49 and the other end of the resistor R50 are respectively connected to two ends of the one or more parallel filtering capacitors.
As a preferred embodiment, the impedance transformation sub-circuit includes a resistor R46, a resistor R58, a capacitor C113, a capacitor C102 and a capacitor C124, one end of the capacitor C102 and the resistor R46 connected in parallel is grounded, and one end of the capacitor C124 and the resistor R58 connected in parallel is grounded; the capacitor C113 is connected in parallel with the one or more parallel filter capacitors, the other end of the capacitor C102 connected in parallel with the resistor R46 and the other end of the capacitor C124 connected in parallel with the resistor R58 are respectively connected to two ends of the capacitor C113, and two ends of the capacitor C113 are further connected to an input end of a signal receiver.
As a preferred embodiment, the signal receiver comprises an analog-to-digital conversion circuit and a microprocessor, wherein an input end of the analog-to-digital conversion circuit is connected to an output end of the filter circuit, and an output end of the analog-to-digital conversion circuit is connected to an input end of the microprocessor.
As a preferred embodiment, the analog-to-digital conversion circuit includes a chip U28, the chip U28 is an ADS1255, two input terminals of the chip U28 are respectively connected to two output terminals of the filter circuit, and an output terminal of the chip U28 is connected to an input terminal of the microprocessor.
As a preferred embodiment, the multi-stage voltage stabilizing circuit comprises a chip U15, a chip U13, a chip U16 and a chip U9, wherein the chip U15, the chip U13, the chip U16 and the chip U9 are respectively MC78M09, REF195GZ, ADR421 and AMS1117-3.3, an input terminal of the chip U15 is connected to an external direct current source, an input terminal of the chip U13 is connected to an output terminal of the chip U15, an input terminal of the chip U16 is connected to an output terminal of the chip U13, and an input terminal of the chip U9 is connected to an output terminal of the chip U13; the output end of the chip U16 is connected to the input end of a constant current or constant voltage circuit, and the output end of the chip U9 supplies power to the gain amplification circuit.
As a preferred embodiment, the multi-stage voltage stabilizing circuit further comprises a first input filter circuit, a second input filter circuit, a third input filter circuit, a first output filter circuit and a second output filter circuit; one end of the first input filter capacitor is connected between the input end of the chip U15 and an external direct current source, and the other end of the first input filter capacitor is grounded; one end of the second input filter capacitor is connected between the output end of the chip U15 and the input end of the chip U13, and the other end of the second input filter capacitor is grounded; one end of the third input filter capacitor is connected between the input end of the chip U16 or/and the chip U9 and the output end of the chip U13, and the other end of the third input filter capacitor is grounded; and one ends of the first output filter circuit and the second output filter circuit are respectively connected to the output ends of the chip U16 and the chip U9, and the other ends of the first output filter circuit and the second output filter circuit are both grounded.
Compared with the prior art, the beneficial effects of the utility model reside in that:
1. the sensor adopts a high-stability, low-temperature-drift and low-noise constant current source or constant voltage source circuit, so that the influence of circuit noise on the sensor signal is reduced.
2. The gain amplification circuit is used for reducing signal attenuation generated by the output impedance of the sensor to the post-stage detection circuit, the amplification factor can be configured to improve the analog-to-digital conversion precision, the fully differential input can improve the anti-noise capability of signal input, the even harmonic can be eliminated, the full differential input can be matched with the output impedance of most of the existing sensors, and the gain coefficient can be controlled by a program to provide a signal source with a proper amplitude for the post-stage detection circuit.
3. An anti-aliasing filter circuit is designed at the front end of the analog-to-digital conversion circuit, so that noise outside an effective signal bandwidth is prevented, the working stability of the sensor can be improved, interference can be inhibited, and the signal acquisition precision is further improved when sampling frequency is aliased into the effective signal bandwidth in the sampling process of the analog-to-digital conversion circuit.
Drawings
Fig. 1 is a block diagram of the signal acquisition circuit of the present invention;
FIG. 2 is a schematic circuit diagram of the constant current or constant voltage circuit of the present invention;
fig. 3 is a schematic circuit diagram of the gain amplifying circuit and the filter circuit of the present invention;
fig. 4 is a circuit schematic diagram of the analog-to-digital conversion circuit of the present invention;
FIG. 5 is a first schematic circuit diagram of the multi-stage voltage stabilizing circuit of the present invention;
fig. 6 is a circuit schematic diagram of the multi-stage voltage stabilizing circuit of the present invention.
Detailed description of the preferred embodiments
The present invention will be further described with reference to the accompanying drawings and specific embodiments, and it should be noted that the embodiments or technical features described below can be arbitrarily combined to form a new embodiment without conflict. Except as specifically noted, the materials and equipment used in this example are commercially available. Examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present application and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. In the description of the present application, "a plurality" means two or more unless specifically stated otherwise.
In the description of the present application, it should be noted that unless otherwise specifically stated or limited, the terms "connected," "communicating," and "connected" are to be construed broadly, e.g., as meaning a fixed connection, a connection through an intervening medium, a connection between two elements, or an interaction between two elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The terms "first," "second," and the like in the description and in the claims of the present application and in the above-described drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Examples
Referring to fig. 1, a signal acquisition circuit includes a sensor 10, a constant current or constant voltage circuit 70, a multi-stage voltage stabilizing circuit 60, a gain amplifying circuit 20 and a filter circuit 30, wherein an output terminal of the multi-stage voltage stabilizing circuit is connected to an input terminal of the constant current or constant voltage circuit, the constant current or constant voltage circuit supplies power to the sensor, and an output terminal of the sensor is connected to an external signal receiver through the gain amplifying circuit and the filter circuit.
The sensor is an active sensor and is used for collecting signals of the mechanism to be detected, converting the signals of the mechanism to be detected into electric signals and transmitting the electric signals to the signal receiver. The sensor may be a pressure sensor for detecting a pressure value, a temperature sensor for detecting a temperature, a humidity sensor for detecting a humidity, a displacement sensor for detecting a displacement, etc., and is not limited herein.
In the preferred embodiment of the present invention, the signal receiver is an analog-to-digital conversion circuit 40 and a Microprocessor (MCU)50, wherein the analog-to-digital conversion circuit is used to convert the analog signal outputted from the filter circuit into a digital signal, and transmit the digital signal to the microprocessor. The microprocessor can be any cheap singlechip digital-to-analog conversion circuit, can be integrated in the microprocessor, and can also be a separate component. The digital signal received by the microprocessor is used for display or other control operations, and is not limited herein.
Specifically, the method comprises the following steps:
the circuit for supplying power to the sensor adopts a constant current source or a constant voltage source circuit with high stability, low temperature drift and low noise, so that the influence of circuit noise on the signal of the sensor is reduced.
Referring to fig. 2, the constant current or constant voltage circuit is a constant current source, and includes a chip U6, a resistor R12, a resistor R7, a PNP transistor Q2, a PMOS transistor Q10, and a resistor R13, wherein the chip U6 is a high-precision voltage-to-current converter XTR111, and an input terminal of the chip U6 is connected to an output terminal of the multi-stage voltage regulator circuit through the resistor R12; the output end of the chip U6 is connected to the emitter of the PNP triode Q2, the base of the PNP triode Q2 is connected to the source of the PMOS tube Q10, the gate driving pole of the chip U6 is connected to the gate of the PMOS tube Q10, the collector of the PNP triode Q2 is connected between the gate of the PMOS tube Q10 and the gate driving pole of the chip U6, two ends of the resistor R7 are respectively connected to the emitter and the base of the PNP triode Q2, and the drain of the PMOS tube Q10 is connected to the power supply end of the sensor through the resistor R13.
The input voltage of the input end of the chip U6 is 2.5V, and the input voltage is output by the output end of the chip U16 in the multi-stage voltage stabilizing circuit. XTR111 is a precision voltage-current converter for outputting 0-20 mA or 4-20 mA analog signal, and the maximum source current can be increased to 36 mA. The conversion ratio between the input voltage and the output current is set by a resistor R11, a PNP triode Q2 plays an amplifying role, and a PMOS transistor Q10 is a switching tube and is used for ensuring high output impedance and wide-range voltage output and good voltage stability.
The input end of the chip U6 is further connected with a filter capacitor C27 and a diode D6, wherein the anode of the diode D6 and one end of the filter capacitor C27 are both grounded, the cathode of the diode D6 and the other end of the filter capacitor C27 are both connected between the input end of the chip U6 and the resistor R12, the diode D6 is used for limiting the input voltage, and the filter capacitor C27 can bypass high-frequency components in the input voltage. The output end of the chip U6 is further connected with a filter capacitor C28, one end of the filter capacitor C28 is connected between the resistor R13 and the drain electrode of the PMOS tube Q10, the other end of the filter capacitor C28 is grounded, and the filter capacitor C28 is used for filtering signals input to the sensor.
The gain amplification circuit adopts a high-impedance input programmable fully differential instrument amplifier, reduces signal attenuation generated by a sensor output impedance to a post-stage detection circuit, can improve analog-to-digital conversion precision by configuring amplification times, and can improve the anti-noise capability of signal input and eliminate even harmonics by fully differential input. And the filter circuit is designed at the front end of the analog-to-digital conversion circuit, so that noise outside the effective signal bandwidth is prevented from aliasing into the effective signal bandwidth in the sampling process and the sampling frequency of the analog-to-digital conversion circuit.
Referring to fig. 3, the gain amplifier circuit includes a chip U25 and a common mode inductor, the chip U25 is a PGA280, the common mode inductor adopts an ACM3225, two input terminals of the common mode inductor are respectively connected to a positive output terminal and a negative output terminal of the sensor, two output terminals of the common mode inductor are respectively connected to a positive input terminal and a negative input terminal of a chip U25, and an output terminal of a chip U25 is connected to the filter circuit.
The filter circuit comprises a filter sub-circuit and an impedance transformation sub-circuit, wherein the input end of the filter sub-circuit is connected to the output end of the chip U25, and the output end of the filter sub-circuit is connected to the signal receiver through the impedance transformation sub-circuit.
Referring to fig. 3, the filter sub-circuit includes a resistor R49, a resistor R50, and one or more parallel filter capacitors (i.e., a filter capacitor or a plurality of parallel filter capacitors), one end of the resistor R49 and one end of the resistor R50 are respectively connected to the positive output terminal and the negative output terminal of the chip U25, and the other end of the resistor R49 and the other end of the resistor R50 are respectively connected to two ends of the one or more parallel filter capacitors. The filter capacitor here adopts a parallel structure of capacitors C114 and C115, that is, two ends of the capacitors C114 and C115 after being connected in parallel are respectively connected to the positive output end and the negative output end of the chip U25 through one end of a resistor R49 and one end of a resistor R50.
Referring to fig. 3, the impedance transformation sub-circuit adopts a capacitive divider impedance circuit, and includes a resistor R46, a resistor R58, a capacitor C113, a capacitor C102 and a capacitor C124, one end of the capacitor C102 connected in parallel with the resistor R46 is grounded, and one end of the capacitor C124 connected in parallel with the resistor R58 is grounded; the capacitor C113 is connected in parallel with two ends of the capacitors C114 and C115, the other end of the capacitor C102 connected in parallel with the resistor R46 and the other end of the capacitor C124 connected in parallel with the resistor R58 are respectively connected to two ends of the capacitor C113, and two ends of the capacitor C113 are also connected to the input end of the signal receiver.
The analog-to-digital conversion circuit adopts high-precision 24-bit ADC sampling and adopts a low-temperature-drift and low-noise voltage reference chip as reference voltage. Referring to fig. 4, the analog-to-digital conversion circuit includes a chip U28, a chip U28 is an ADS1255, the chip ADS1255 has a programmable gain amplifier therein, two input terminals of the chip U28 are respectively connected to two output terminals of the filter circuit, and an output terminal of the chip U28 is connected to an input terminal of the microprocessor. By combining the amplification factors of the gain amplification circuit and the programmable gain amplification circuit in the analog-to-digital conversion circuit, the technical problem that the system cannot exert the optimal resolution to perform self-adaptive optimal acquisition on signals with a large dynamic range and weak signals due to the curability acquisition sensitivity set by the signal maximum value in the prior art, so that the sensitivity and the accuracy of the whole system are reduced can be solved.
A multi-stage voltage stabilizing circuit adopts more than two levels of LDOs (low dropout regulator) to supply power for analog parts such as a constant current or constant voltage circuit, a gain amplifying circuit, an analog-to-digital conversion circuit and the like, and improves the influence of the whole circuit on switching noise and other interference, thereby improving the precision of signal processing.
Referring to fig. 5 and 6, the multi-stage voltage regulator includes a chip U15, a chip U13, a chip U16, and a chip U9, where the chip U15, the chip U13, the chip U16, and the chip U9 are MC78M09, REF195GZ, ADR421, AMS1117-3.3, respectively, an input terminal of the chip U15 is connected to an external dc source, an input terminal of the chip U13 is connected to an output terminal of the chip U15, an input terminal of the chip U16 is connected to an output terminal of the chip U13, and an input terminal of the chip U9 is connected to an output terminal of the chip U13; the output end of the chip U16 is connected to the input end of the constant current or constant voltage circuit, and the output end of the chip U9 supplies power for the gain amplification circuit.
The output voltages of the chip U15, the chip U13, the chip U16 and the chip U9 are 9V, 5V, 2.5V and 3.3V, respectively, and the external dc source may be 15V, which may be obtained by a rectifier circuit from the mains supply.
In addition, the multi-stage voltage stabilizing circuit further comprises a first input filter circuit, a second input filter circuit, a third input filter circuit, a first output filter circuit and a second output filter circuit.
The first input filter capacitor adopts an LC filter circuit and is used for filtering a voltage signal input into the chip U15. The inductor L16 and the capacitor C57 are included, wherein two ends of the inductor L16 are respectively connected between the input end of the chip U15 and an external direct current source, one end of the capacitor C57 is grounded, and the other end of the capacitor C57 is connected between one end of the inductor L16 and the input end of the chip U15.
The second input filter capacitor is used for filtering a voltage signal input into the chip U13 and comprises a capacitor C58 and a capacitor C60, wherein the capacitor C58 is connected with the capacitor C60 in parallel, one end of the parallel connected capacitor is connected between the output end of the chip U15 and the input end of the chip U13, and the other end of the parallel connected capacitor is grounded.
The third input filter capacitor is used for filtering voltage signals input into the chip U16 and the chip U9 and comprises a capacitor C59 and a capacitor C56, one end of the capacitor C59 and the capacitor C56 which are connected in parallel is connected between the input end of the chip U16 and the input end of the chip U9 and the output end of the chip U13, and the other end of the capacitor C59 and the capacitor C56 which are connected in parallel is grounded.
The first output filter circuit is used for filtering an output voltage signal of the chip U16 and comprises a capacitor C61 and a capacitor C64, one end of the capacitor C61, which is connected with the capacitor C64 in parallel, is connected to the output ends of the chip U16 and the chip U9 respectively, and the other end of the capacitor C61, which is connected with the capacitor C64 in parallel, is grounded.
The second output filter circuit is used for filtering an output voltage signal of the chip U9 and comprises a capacitor C40, a capacitor C38, a capacitor C39 and an inductor L11, wherein one end of the inductor L11 is connected to the output end of the chip U9, the other end of the inductor L11 outputs 3.3V direct-current voltage, one end of the capacitor C40 and the capacitor C38 which are connected in parallel is connected between one end of the inductor L11 and the output end of the chip U9, the other end of the capacitor C40 and the capacitor C38 which are connected in parallel is grounded, one end of the capacitor C39 is grounded, and the other end of the capacitor C39 is connected between the other end of the inductor L11 and the 3.3V direct-current voltage.
Finally, it should be noted that: the above embodiments are only preferred embodiments of the present invention, and the protection scope of the present invention cannot be limited thereby, and any insubstantial changes and substitutions made by those skilled in the art based on the present invention are all within the protection scope of the present invention.
Claims (10)
1. A signal acquisition circuit is characterized by comprising a sensor, a constant-current or constant-voltage circuit, a multi-stage voltage stabilizing circuit, a gain amplification circuit and a filter circuit, wherein the output end of the multi-stage voltage stabilizing circuit is connected to the input end of the constant-current or constant-voltage circuit, the constant-current or constant-voltage circuit supplies power to the sensor, and the output end of the sensor is connected to an external signal receiver through the gain amplification circuit and the filter circuit.
2. The signal acquisition circuit of claim 1, wherein the constant current or constant voltage circuit comprises a chip U6, a resistor R12, a resistor R7, a PNP triode Q2, a PMOS tube Q10 and a resistor R13, wherein the chip U6 is XTR111, and an input end of the chip U6 is connected to an output end of the multi-stage voltage stabilizing circuit through the resistor R12; the output end of the chip U6 is connected to an emitter of a PNP triode Q2, the base of the PNP triode Q2 is connected to the source of a PMOS tube Q10, the gate driving pole of the chip U6 is connected to the gate of a PMOS tube Q10, the collector of the PNP triode Q2 is connected between the gate of the PMOS tube Q10 and the gate driving pole of the chip U6, two ends of the resistor R7 are respectively connected to the emitter and the base of the PNP triode Q2, and the drain of the PMOS tube Q10 is connected to the power supply end of the sensor through the resistor R13.
3. The signal acquisition circuit of claim 1, wherein the gain amplifier circuit comprises a chip U25 and a common mode inductor, the chip U25 is a PGA280, two input terminals of the common mode inductor are respectively connected to the positive output terminal and the negative output terminal of the sensor, two output terminals of the common mode inductor are respectively connected to the positive input terminal and the negative input terminal of a chip U25, and an output terminal of the chip U25 is connected to the filter circuit.
4. The signal acquisition circuit of claim 3 wherein the filter circuit comprises a filter sub-circuit and an impedance transformation sub-circuit, an input of the filter sub-circuit being connected to an output of a chip U25, an output of the filter sub-circuit being connected to the signal receiver via the impedance transformation sub-circuit.
5. The signal acquisition circuit as claimed in claim 4, wherein the filter sub-circuit comprises a resistor R49, a resistor R50 and one or more parallel filter capacitors, one end of the resistor R49 and one end of the resistor R50 are respectively connected to the positive output end and the negative output end of the chip U25, and the other end of the resistor R49 and the other end of the resistor R50 are respectively connected to two ends of the one or more parallel filter capacitors.
6. The signal acquisition circuit according to claim 5, wherein the impedance transformation sub-circuit comprises a resistor R46, a resistor R58, a capacitor C113, a capacitor C102 and a capacitor C124, one end of the capacitor C102 and the resistor R46 connected in parallel is grounded, and one end of the capacitor C124 and the resistor R58 connected in parallel is grounded; the capacitor C113 is connected in parallel with the one or more parallel filter capacitors, the other end of the capacitor C102 connected in parallel with the resistor R46 and the other end of the capacitor C124 connected in parallel with the resistor R58 are respectively connected to two ends of the capacitor C113, and two ends of the capacitor C113 are further connected to an input end of a signal receiver.
7. The signal acquisition circuit of any one of claims 1-6 wherein the signal receiver comprises an analog-to-digital conversion circuit and a microprocessor, an input of the analog-to-digital conversion circuit being coupled to an output of the filter circuit, an output of the analog-to-digital conversion circuit being coupled to an input of the microprocessor.
8. The signal acquisition circuit of claim 7, wherein the analog-to-digital conversion circuit comprises a chip U28, the chip U28 is ADS1255, two input terminals of the chip U28 are respectively connected to two output terminals of the filter circuit, and an output terminal of the chip U28 is connected to an input terminal of the microprocessor.
9. The signal acquisition circuit as claimed in any one of claims 1 to 6, wherein the multi-stage voltage regulation circuit comprises a chip U15, a chip U13, a chip U16 and a chip U9, the chip U15, the chip U13, the chip U16 and the chip U9 are respectively MC78M09, REF195GZ, ADR421 and AMS1117-3.3, an input terminal of the chip U15 is connected to an external direct current source, an input terminal of the chip U13 is connected to an output terminal of the chip U15, an input terminal of the chip U16 is connected to an output terminal of the chip U13, and an input terminal of the chip U9 is connected to an output terminal of the chip U13; the output end of the chip U16 is connected to the input end of a constant current or constant voltage circuit, and the output end of the chip U9 supplies power to the gain amplification circuit.
10. The signal acquisition circuit of claim 9 wherein the multi-stage voltage regulator circuit further comprises a first input filter circuit, a second input filter circuit, a third input filter circuit, and first and second output filter circuits; one end of the first input filter capacitor is connected between the input end of the chip U15 and an external direct current source, and the other end of the first input filter capacitor is grounded; one end of the second input filter capacitor is connected between the output end of the chip U15 and the input end of the chip U13, and the other end of the second input filter capacitor is grounded; one end of the third input filter capacitor is connected between the input end of the chip U16 or/and the chip U9 and the output end of the chip U13, and the other end of the third input filter capacitor is grounded; and one ends of the first output filter circuit and the second output filter circuit are respectively connected to the output ends of the chip U16 and the chip U9, and the other ends of the first output filter circuit and the second output filter circuit are both grounded.
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| CN202021534049.2U CN212258938U (en) | 2020-07-29 | 2020-07-29 | Signal acquisition circuit |
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| CN202021534049.2U CN212258938U (en) | 2020-07-29 | 2020-07-29 | Signal acquisition circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115066057A (en) * | 2022-08-15 | 2022-09-16 | 深圳市博德致远生物技术有限公司 | Multichannel optical acquisition system circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115066057A (en) * | 2022-08-15 | 2022-09-16 | 深圳市博德致远生物技术有限公司 | Multichannel optical acquisition system circuit |
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