CN216526923U - Reference voltage circuit applied to DDR - Google Patents
Reference voltage circuit applied to DDR Download PDFInfo
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- CN216526923U CN216526923U CN202122796097.XU CN202122796097U CN216526923U CN 216526923 U CN216526923 U CN 216526923U CN 202122796097 U CN202122796097 U CN 202122796097U CN 216526923 U CN216526923 U CN 216526923U
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Abstract
The utility model discloses a reference voltage circuit applied to DDR (double data rate), which comprises a first voltage circuit and a second voltage circuit, wherein the voltage output end of the first voltage circuit is electrically connected with a VREFCA (virtual random access memory) pin of a memory chip, the voltage output end of the second voltage circuit is electrically connected with the VREFDQ pin of the memory chip, the first voltage circuit comprises a first resistor and a first capacitor, the first resistor is connected with the first capacitor in parallel, one end of the first resistor is connected with a power supply after the first resistor is connected with the first capacitor in parallel, and the other end of the first resistor is connected with the VREFCA pin of the memory chip; the second voltage circuit comprises a third resistor and a sixth capacitor, the third resistor and the sixth capacitor are connected in parallel, one end of the third resistor is connected with a power supply after being connected in parallel, and the other end of the third resistor is connected with a VREFDQ pin of the memory chip.
Description
Technical Field
The utility model relates to the technical field of memory chip circuits, in particular to a reference voltage circuit applied to DDR.
Background
With the continuous progress of technology, the capacity and reading speed of a memory module (DDR Double Data Rate) have been greatly developed, and the memory module (or memory chip, memory granule) undertakes the work of information storage. The memory module is an indispensable part of the intelligent terminal, and the overall performance of the intelligent terminal is directly influenced by the quality of information transmission and storage.
In the prior art, an input receiver of a memory module is a differential stage receiver, and in order to increase a signal-to-noise level of a data bus in the memory module, a reference Voltage (VREF) needs to be provided to the memory module during operation. When the precision of the reference voltage is deteriorated, each timing signal of the memory module is changed when the memory module transmits data, thereby affecting the correct timing.
In the prior art, a reference voltage is obtained by connecting two resistors with the same resistance in series and dividing the filtered voltage, but the reference voltage circuit has poor capability of preventing voltage mutation and low stability, and finally, each time sequence signal of a memory module is changed when data is transmitted, or even a device is damaged.
SUMMERY OF THE UTILITY MODEL
In order to overcome the defects of the prior art, the utility model discloses a reference voltage circuit applied to DDR (double data rate), the technical scheme connects a resistor connected with a power supply in two series-connected voltage-dividing resistors in parallel with a capacitor, and the other voltage-dividing resistor is connected with a plurality of capacitors in parallel, so that the circuit oscillation can be inhibited, and a high-precision and stable reference voltage is provided for a memory chip, and the technical scheme is as follows:
a reference voltage circuit applied to DDR comprises a first voltage circuit and a second voltage circuit, wherein a voltage output end of the first voltage circuit is electrically connected with a VREFCA pin of a memory chip, and a voltage output end of the second voltage circuit is electrically connected with a VREFDQ pin of the memory chip.
The first voltage circuit comprises a first resistor and a first capacitor, the first resistor is connected with the first capacitor in parallel, one end of the first resistor is connected with a power supply after the first resistor is connected with the first capacitor in parallel, and the other end of the first resistor is connected with a VREFCA pin of the memory chip; the first voltage circuit further comprises a second resistor, the second resistor is connected with the first resistor in series, one end of the second resistor is electrically connected with one end of the first resistor, which is connected with the VREFCA pin of the memory chip, and the other end of the second resistor is grounded.
The first voltage circuit further comprises a second capacitor and a third capacitor, the second capacitor and the third capacitor are respectively connected with the second resistor in parallel, one end of the second capacitor and one end of the third capacitor are electrically connected with the first resistor and connected with one end of the VREFCA pin of the memory chip, and the other end of the second capacitor and one end of the third capacitor are grounded.
The second voltage circuit comprises a third resistor and a sixth capacitor, the third resistor and the sixth capacitor are connected in parallel, one end of the third resistor is connected with a power supply after the third resistor and the sixth capacitor are connected in parallel, and the other end of the third resistor is connected with a VREFDQ pin of the memory chip; the second voltage circuit also comprises a fourth resistor, the fourth resistor is connected with the third resistor in series, one end of the fourth resistor is electrically connected with one end of the third resistor, which is connected with the VREFDQ pin of the memory chip, and the other end of the fourth resistor is grounded.
The second voltage circuit further comprises a seventh capacitor and an eighth capacitor, the seventh capacitor and the eighth capacitor are respectively connected with the fourth resistor in parallel, one end of the seventh capacitor and one end of the eighth capacitor are electrically connected with the third resistor and connected with one end of the VREFDQ pin of the memory chip, and the other end of the seventh capacitor and one end of the eighth capacitor are grounded.
Furthermore, the first voltage circuit further comprises a fourth capacitor, the fourth capacitor is connected in parallel with the second resistor, one end of the fourth capacitor is electrically connected with one end of the first resistor connected with the VREFCA pin of the memory chip, and the other end of the fourth capacitor is grounded.
Furthermore, the first voltage circuit further comprises a fifth capacitor, the fifth capacitor is connected in parallel with the second resistor, one end of the fifth capacitor is electrically connected with one end of the first resistor connected with the VREFCA pin of the memory chip, and the other end of the fifth capacitor is grounded.
Furthermore, the second voltage circuit further comprises a ninth capacitor, the ninth capacitor is connected in parallel with the fourth resistor, one end of the ninth capacitor is electrically connected with one end of the third resistor connected with the VREFDQ pin of the memory chip, and the other end of the ninth capacitor is grounded.
Furthermore, the second voltage circuit further comprises a tenth capacitor, the tenth capacitor is connected in parallel with the fourth resistor, one end of the tenth capacitor is electrically connected with the third resistor and is connected with one end of the VREFDQ pin of the memory chip, and the other end of the tenth capacitor is grounded.
Furthermore, the specifications of the first resistor and the second resistor are the same; the third resistor and the fourth resistor have the same specification.
Furthermore, the specifications of the first capacitor and the second capacitor are the same; the specifications of the third capacitor, the fourth capacitor and the fifth capacitor are the same, and the specifications of the first capacitor and the second capacitor are different from the specifications of the third capacitor, the fourth capacitor and the fifth capacitor.
Furthermore, the specification of the sixth capacitor is the same as that of the seventh capacitor; the specifications of the eighth capacitor, the ninth capacitor and the tenth capacitor are the same, and the specifications of the sixth capacitor and the seventh capacitor are different from the specifications of the eighth capacitor, the ninth capacitor and the tenth capacitor.
The utility model relates to a reference voltage circuit applied to DDR (double data rate), which is characterized in that a resistor connected with a power supply in two series voltage dividing resistors is connected with a capacitor in parallel, so that voltage mutation can be prevented, circuit oscillation can be inhibited, and more stable reference voltage can be provided for a memory chip.
Drawings
FIG. 1 is a schematic diagram of a reference voltage circuit for DDR according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings.
For the purpose of better illustrating the embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; certain well-known structures in the drawings and omissions of their description may be apparent to those skilled in the art. The same or similar reference numerals correspond to the same or similar components.
Reference Voltage (VREF), where VREFCA is an address bus reference Voltage end of the memory chip, and VREFDQ is a data bus reference Voltage end of the memory chip, which can effectively improve the signal-to-noise level of the system data bus, so the VREFCA pin and the VREFDQ pin of the memory chip need to be connected to a stable reference Voltage.
The reference voltage in the prior art is obtained by dividing voltage by connecting two resistors with the same resistance in series, and the reference voltage circuit has poor capability of preventing voltage mutation and low stability.
The utility model is optimized on the basis of the prior art, the resistor connected with a power supply in two series-connected voltage-dividing resistors is connected with a capacitor in parallel to achieve the purposes of preventing voltage mutation and inhibiting circuit oscillation, the other resistor is added with a parallel capacitor to strengthen the protection effect on the filtering function and components of the circuit, the technical scheme can provide more stable reference voltage for a memory chip, and the specific embodiment of the technical scheme is as follows:
as shown in fig. 1, the present embodiment is a reference voltage circuit applied to DDR, which includes a first voltage circuit 21 and a second voltage circuit 22, wherein a voltage output terminal of the first voltage circuit 21 is electrically connected to a VREFCA pin of a memory chip 10, and a voltage output terminal of the second voltage circuit 22 is electrically connected to a VREFDQ pin of the memory chip 10 (the VREFCA pin is an address bus reference voltage terminal, and the VREFDQ pin is a data bus reference voltage terminal).
In this embodiment, the first voltage circuit 21 includes a first resistor R1 and a first capacitor C1, the first resistor R1 is connected in parallel with the first capacitor C1, one end of the parallel connection is connected to a power supply, and the other end is connected to the VREFCA pin of the memory chip 10.
The first resistor R1 connected in parallel and the first capacitor C1 form a unit for preventing voltage abrupt change. Specifically, the first capacitor C1 is used for preventing voltage abrupt change and absorbing overvoltage in a spike state, the first resistor R1 plays a damping role and consumes energy of the overvoltage, and the first resistor R1 and the first capacitor C1 are matched to achieve an oscillation suppression technical effect of the circuit.
In this embodiment, the first voltage circuit 21 further includes a second resistor R2, the second resistor R2 is connected in series with the first resistor R1, one end of the second resistor R2 is electrically connected to the first resistor R1 and connected to one end of the VREFCA pin of the memory chip 10, and the other end is grounded. It should be noted that the first resistor R1 and the second resistor R2 are resistors with the same specification, and have a voltage dividing function in the first voltage circuit 21, specifically, the values of the first resistor R1 and the second resistor R2 are preferably 10K Ω in this embodiment, and the values of the first resistor R1 and the second resistor R2 may also be other values, which is not described in this embodiment again.
In this embodiment, the first voltage circuit 21 further includes a second capacitor C2 and a third capacitor C3, the second capacitor C2 and the third capacitor C3 are respectively connected in parallel to the second resistor R2, one end of the second capacitor C2 and one end of the third capacitor C3 are electrically connected to the first resistor R1 and one end of the VREFCA pin of the memory chip 10, and the other end is grounded.
In a more preferred embodiment, the first voltage circuit 21 further includes a fourth capacitor C4, the fourth capacitor C4 is connected in parallel with the second resistor R2, one end of the fourth capacitor C4 is electrically connected to the first resistor R1 and is connected to one end of the VREFCA pin of the memory chip 10, and the other end is grounded.
In a more preferred embodiment, the first voltage circuit 21 further includes a fifth capacitor C5, the fifth capacitor C5 is connected in parallel with the second resistor R2, one end of the fifth capacitor C5 is electrically connected to the first resistor R1 and is connected to one end of the VREFCA pin of the memory chip 10, and the other end is grounded.
The second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 play a role of filtering, and the second resistor R2 can absorb electric energy of the capacitors, so that the discharge current of the capacitors can be prevented from being too large, and the electronic components can be prevented from being damaged by the large current. In this embodiment, two capacitors of the first capacitor C1 and the second capacitor C2 are capacitors with the same specification, three capacitors of the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 are capacitors with the same specification, and the specifications of two capacitors of the first capacitor C1 and the second capacitor C2 are different from the specifications of three capacitors of the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5.
In this embodiment, the capacitance values of the first capacitor C1 and the second capacitor C2 are 100nF, and the capacitance values of the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5 are 1 nF.
In this embodiment, the parallel capacitance of the second resistor R2 is the second capacitor C2 and the third capacitor C3, or the second capacitor C2, the third capacitor C3 and the fourth capacitor C4, or the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5, and in a preferable scheme, the parallel capacitance of the second resistor R2 is the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5.
It should be noted that, in any of the three parallel capacitance schemes of the second resistor R2, the three devices of the second resistor R2, the second capacitor C2 and the third capacitor C3 are all disposed together. For example, in a preferred embodiment, the parallel capacitance of the second resistor R2 is the second capacitor C2, the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5, wherein three devices of the second resistor R2, the second capacitor C2 and the third capacitor C3 are disposed together, and the fourth capacitor C4 and the fifth capacitor C5 may be separately disposed at other positions of the circuit board.
In this embodiment, the second voltage circuit 22 includes a third resistor R3 and a sixth capacitor C6, the third resistor R3 and the sixth capacitor are connected in parallel to C6, one end of the parallel connection is connected to a power supply, and the other end is connected to the VREFDQ pin of the memory chip 10.
Similarly, the third resistor R3 and the sixth capacitor C6 connected in parallel form a unit for preventing voltage abrupt change. Specifically, the sixth capacitor C6 also functions to prevent voltage abrupt change and absorb overvoltage in a spike state, the third resistor R3 also functions as a damping function and consumes energy of the overvoltage, and the third resistor R3 and the sixth capacitor C6 cooperate to achieve the technical effect of suppressing oscillation of the circuit.
In this embodiment, the second voltage circuit 22 further includes a fourth resistor R4, the fourth resistor R4 is connected in series with the third resistor R3, one end of the fourth resistor R4 is electrically connected to the third resistor R3 and connected to one end of the VREFDQ pin of the memory chip 10, and the other end is grounded. It should be noted that the third resistor R3 and the fourth resistor R4 are resistors with the same specification, and have a voltage dividing function in the second voltage circuit 22, specifically, the values of the third resistor R3 and the fourth resistor R4 are preferably 10K Ω in this embodiment, and the values of the third resistor R3 and the fourth resistor R4 may also be other values, which is not described in this embodiment again.
In this embodiment, the second voltage circuit 22 further includes a seventh capacitor C7 and an eighth capacitor C8, the seventh capacitor C7 and the eighth capacitor C8 are respectively connected in parallel to the fourth resistor R4, one end of the seventh capacitor C7 and one end of the eighth capacitor C8 are electrically connected to the third resistor R3 and one end of the VREFDQ pin of the memory chip 10, and the other end is grounded.
In a more preferred embodiment, the second voltage circuit 22 further includes a ninth capacitor C9, the ninth capacitor C9 is connected in parallel with the fourth resistor R4, one end of the ninth capacitor C9 is electrically connected to the third resistor R3 and is connected to one end of the VREFDQ pin of the memory chip 10, and the other end is grounded.
In a more preferred embodiment, the second voltage circuit 22 further includes a tenth capacitor C10, the tenth capacitor C10 is connected in parallel with the fourth resistor R4, one end of the tenth capacitor C10 is electrically connected to the third resistor R3 and is connected to one end of the VREFDQ pin of the memory chip 10, and the other end is grounded.
The seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10 play a role of filtering, and since the fourth resistor R4 can absorb electric energy of the capacitors, the discharge current of the capacitors can be prevented from being too large, so that the electronic components are prevented from being damaged by the large current. In this embodiment, two capacitors of the sixth capacitor C6 and the seventh capacitor C7 are capacitors with the same specification, three capacitors of the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10 are capacitors with the same specification, and the specifications of two capacitors of the sixth capacitor C6 and the seventh capacitor C7 are different from the specifications of three capacitors of the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10.
In this embodiment, the capacitance values of the sixth capacitor C6 and the seventh capacitor C7 are 100nF, and the capacitance values of the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10 are 1 nF.
In this embodiment, the parallel capacitance of the fourth resistor R4 is the seventh capacitor C7 and the eighth capacitor C8, or the seventh capacitor C7, the eighth capacitor C8 and the ninth capacitor C9, or the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10, and in a preferable scheme, the parallel capacitance of the fourth resistor R4 is the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9 and the tenth capacitor C10.
It should be noted that, in any of the three parallel capacitance schemes of the fourth resistor R4, the four resistors R4, the seventh capacitor C7 and the eighth capacitor C8 are all disposed together. For example, in a preferred embodiment, the parallel capacitance of the fourth resistor R4 is a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C10, wherein three devices of the fourth resistor R4, the seventh capacitor C7 and the eighth capacitor C8 are disposed together, and the ninth capacitor C9 and the tenth capacitor C10 may be separately disposed at other positions of the circuit board.
It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. The utility model provides a be applied to DDR's reference voltage circuit, includes first voltage circuit and second voltage circuit, the voltage output end electric connection memory chip's VREFCA pin of first voltage circuit, the voltage output end electric connection memory chip's VREFDQ pin of second voltage circuit which characterized in that:
the first voltage circuit comprises a first resistor and a first capacitor, the first resistor and the first capacitor are connected in parallel, one end of the first resistor is connected with a power supply after the first resistor and the first capacitor are connected in parallel, and the other end of the first resistor and the first capacitor is connected with a VREFCA pin of the memory chip; the first voltage circuit also comprises a second resistor, the second resistor is connected with the first resistor in series, one end of the second resistor is electrically connected with one end of the first resistor, which is connected with the VREFCA pin of the memory chip, and the other end of the second resistor is grounded;
the first voltage circuit further comprises a second capacitor and a third capacitor, the second capacitor and the third capacitor are respectively connected with the second resistor in parallel, one end of the second capacitor and one end of the third capacitor are electrically connected with the first resistor and connected with one end of the VREFCA pin of the memory chip, and the other end of the second capacitor and one end of the third capacitor are grounded;
the second voltage circuit comprises a third resistor and a sixth capacitor, the third resistor and the sixth capacitor are connected in parallel, one end of the third resistor is connected with a power supply after the third resistor and the sixth capacitor are connected in parallel, and the other end of the third resistor is connected with a VREFDQ pin of the memory chip; the second voltage circuit also comprises a fourth resistor, the fourth resistor is connected with the third resistor in series, one end of the fourth resistor is electrically connected with one end of the third resistor, which is connected with the VREFDQ pin of the memory chip, and the other end of the fourth resistor is grounded;
the second voltage circuit further comprises a seventh capacitor and an eighth capacitor, the seventh capacitor and the eighth capacitor are respectively connected with the fourth resistor in parallel, one end of the seventh capacitor and one end of the eighth capacitor are electrically connected with the third resistor and connected with one end of the VREFDQ pin of the memory chip, and the other end of the seventh capacitor and one end of the eighth capacitor are grounded.
2. The reference voltage circuit for DDR of claim 1, wherein said first voltage circuit further comprises a fourth capacitor, said fourth capacitor is connected in parallel with said second resistor, one end of said fourth capacitor is electrically connected to said first resistor and connected to one end of said VREFCA pin of said memory chip, and the other end of said fourth capacitor is grounded.
3. The reference voltage circuit for DDR of claim 2, wherein said first voltage circuit further comprises a fifth capacitor, said fifth capacitor is connected in parallel with said second resistor, one end of said fifth capacitor is electrically connected to said first resistor and connected to one end of said VREFCA pin of said memory chip, and the other end of said fifth capacitor is grounded.
4. The reference voltage circuit for DDR of claim 1, wherein said second voltage circuit further comprises a ninth capacitor, said ninth capacitor is connected in parallel with said fourth resistor, one end of said ninth capacitor is electrically connected to said third resistor and connected to one end of said VREFDQ pin of said memory chip, and the other end of said ninth capacitor is grounded.
5. The reference voltage circuit for DDR as claimed in claim 4, wherein said second voltage circuit further comprises a tenth capacitor, said tenth capacitor is connected in parallel with said fourth resistor, one end of said tenth capacitor is electrically connected to said third resistor and connected to one end of VREFDQ pin of said memory chip, and the other end is grounded.
6. The reference voltage circuit applied to DDR of claim 1, wherein said first resistor and said second resistor have the same specification; the third resistor and the fourth resistor have the same specification.
7. The reference voltage circuit applied to DDR as claimed in claim 3, wherein the first capacitor and the second capacitor have the same specification; the specifications of the third capacitor, the fourth capacitor and the fifth capacitor are the same.
8. The reference voltage circuit applied to DDR as claimed in claim 7, wherein the first capacitor and the second capacitor have different specifications than the third capacitor, the fourth capacitor and the fifth capacitor.
9. The reference voltage circuit applied to DDR as claimed in claim 5, wherein the sixth capacitor and the seventh capacitor have the same specification; the specifications of the eighth capacitor and the ninth capacitor are the same as those of the tenth capacitor.
10. The reference voltage circuit applied to the DDR of claim 9, wherein the specifications of the sixth capacitor and the seventh capacitor are different from the specifications of the eighth capacitor, the ninth capacitor and the tenth capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122796097.XU CN216526923U (en) | 2021-11-16 | 2021-11-16 | Reference voltage circuit applied to DDR |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122796097.XU CN216526923U (en) | 2021-11-16 | 2021-11-16 | Reference voltage circuit applied to DDR |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216526923U true CN216526923U (en) | 2022-05-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202122796097.XU Active CN216526923U (en) | 2021-11-16 | 2021-11-16 | Reference voltage circuit applied to DDR |
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|---|---|
| CN (1) | CN216526923U (en) |
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2021
- 2021-11-16 CN CN202122796097.XU patent/CN216526923U/en active Active
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