CN108228502B - Back plate meeting electrical characteristics of ARINC659 bus - Google Patents
Back plate meeting electrical characteristics of ARINC659 bus Download PDFInfo
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- CN108228502B CN108228502B CN201611155416.6A CN201611155416A CN108228502B CN 108228502 B CN108228502 B CN 108228502B CN 201611155416 A CN201611155416 A CN 201611155416A CN 108228502 B CN108228502 B CN 108228502B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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Abstract
The invention provides a backboard designed based on a three-terminal voltage regulator, a precision resistor and a printed board, which comprises a voltage conversion circuit and an impedance matching circuit, is mainly applied to the realization of a bus backboard of an onboard computer conforming to an ARINC659 bus protocol, and can meet the characteristics of electrical isolation, level stability, impedance matching and the like required by the ARINC659 bus protocol.
Description
Technical Field
The invention belongs to the technical field of airborne computer bus communication, and realizes a bus backboard meeting the electrical characteristic requirements of an ARINC659 bus protocol.
Background
With the development of civil and military aircraft, electronic systems of the aircraft gradually enter the full information fusion era, and a bus is needed to realize rapid and reliable communication among modules in an onboard computer. The Arinc659 bus is increasingly widely used as a high-reliability fault-tolerant serial bus. The ARINC659 protocol requires a bus backplane that meets a variety of electrical characteristics.
However, the electrical design data of the ARINC659 bus backboard is not seen in China, and no detailed implementable data can be referred to due to technical blockade at abroad.
In order to meet the requirements of an ARINC659 bus protocol, the invention provides a backboard designed based on a three-terminal regulator, a precision resistor and a printed board, which can meet the electrical characteristics required by the protocol.
Disclosure of Invention
The invention provides a bus backboard designed based on a three-terminal voltage stabilizer, a precision resistor and a printed board, which can meet the electric characteristics of the backboard required by an ARINC659 bus protocol.
The back panel comprises 4 groups of identical combined circuits, and each group of combined circuits comprises a voltage conversion circuit and an impedance matching circuit. The computer 5V power supply is connected with the voltage conversion circuit, and the converted 2.1V power supply is respectively connected with the impedance matching circuit from the left end and the right end of the back plate.
The voltage conversion circuit comprises a three-terminal voltage regulator N1, a first filter capacitor C1, a second filter capacitor C2, an energy storage capacitor C3, a resistor R1 and a resistor R2. A5V power supply of the computer is divided into two paths after passing through a fuse F1, one path is connected with the input end of a three-terminal voltage regulator N1, the other path is connected with one end of a first filter capacitor C1, and the other end of the C1 is connected with DGND. The adjusting end of the three-terminal voltage stabilizer N1 is divided into two paths, one path is connected with one end of a resistor R1 and one end of a resistor R2, and the other end of the resistor R2 is connected with DGND. The output end of the three-terminal voltage regulator N1 is divided into two paths, one path is connected with the other end of the R1, and the other path is output outwards. The second filter capacitor C2 and the energy storage capacitor C3 are respectively connected between the output end of the three-terminal regulator N1 and DGND, and the resistance value of R1 is as follows: r2 resistance 4: 3.
in the impedance matching circuit, each group of bus signals CK, D0 and D1 in the three groups of bus signals are respectively connected with a 33-omega constant value resistor at two ends of the backboard (CK is connected with R4 and R7; D0 is connected with R5 and R8; D1 is connected with R6 and R9). Resistors R4, R5, R6 are connected to the left 2.1V level; r7, R8, R9 are connected to the right 2.1V level and 0.1uF fixed filter capacitances C4, C5, C6 are connected between the left 2.1V level and Digital Ground (DGND); between the right 2.1V level and Digital Ground (DGND) 0.1uF constant filter capacitances C7, C8, C9 are connected. When printed wiring is performed, characteristic impedance is controlled to 33 Ω uniformly for each set of bus signals (CK, D0, D1), and packet digital (DGND) processing is performed.
The invention has the technical effects that:
the bus backplane that meets the ARINC659 protocol requirements has the following electrical characteristics:
a. the voltage of the backboard bus terminal is required to be not less than +2V and not more than + 2.2V;
b. four groups of buses on the back plate realize electrical isolation, and the failure of any one group of buses does not affect other bus groups;
c. the back plate provides tail end series impedance matching for the four groups of buses, so that the signal integrity is ensured;
d. when the output level of each module is 1.2V, the backboard can provide the absorption current of 100mA for the low level of the signal driver;
e. the series impedance of the backplane bus must be limited to a range such that the maximum rise in voltage should be less than 100mV when a signal is output by any driven module to a termination resistor at either end of the backplane;
f. the voltage difference between all the bandgap grounds of any two modules connected to the backplane is no more than 50 mV.
Drawings
FIG. 1 is a circuit diagram of a backplane;
FIG. 2 is a schematic diagram of a voltage conversion circuit;
fig. 3 is a schematic diagram of an impedance matching circuit.
Detailed Description
A backplane that satisfies ARINC659 bus electrical characteristics includes 4 sets of identical combinatorial circuits, each set of combinatorial circuits including a voltage conversion circuit and an impedance matching circuit. The computer 5V power supply is connected with the voltage conversion circuit, and the converted 2.1V power supply is respectively connected with the impedance matching circuit from the left end and the right end of the back plate. See fig. 1.
The voltage conversion circuit comprises a three-terminal voltage regulator N1, a first filter capacitor C1, a second filter capacitor C2, an energy storage capacitor C3, a resistor R1 and a resistor R2. A5V power supply of the computer is divided into two paths after passing through a fuse F1, one path is connected with the input end of a three-terminal voltage regulator N1, the other path is connected with one end of a first filter capacitor C1, and the other end of the C1 is connected with DGND. The adjusting end of the three-terminal voltage stabilizer N1 is divided into two paths, one path is connected with one end of a resistor R1 and one end of a resistor R2, and the other end of the resistor R2 is connected with DGND. The output end of the three-terminal voltage regulator N1 is divided into two paths, one path is connected with the other end of the R1, and the other path is output outwards. The second filter capacitor C2 and the energy storage capacitor C3 are respectively connected between the output end of the three-terminal regulator N1 and DGND, and the resistance value of R1 is as follows: r2 resistance 4: 3.
the fuse realizes that the power supply conversion circuit is electrically isolated from a 5V power supply in the airborne computer. JW1083 is selected as the three-terminal voltage stabilizer N1, resistances of voltage dividing resistors R1 and R2 are respectively 100 omega and 75 omega, F-level 1% precision resistors are selected, a first filter capacitor C1 and a second filter capacitor C2 are selected as ceramic dielectric capacitors with capacitance values of 0.1uF, an energy storage capacitor C3 is selected as tantalum capacitors with capacitance values of 10uF, and a fuse wire is selected as 473001. The circuit converts a 5V power supply in an onboard computer into 2.1V power supply with the accuracy of +/-100 mV and the maximum driving capability of 5A, and outputs stable pull-up levels for four groups of buses respectively, and the circuit is shown in figure 2.
Each group of bus signals (CK, D0 and D1) in the impedance matching circuit are respectively connected with a 33-omega constant value resistor at two ends of the backboard (CK is connected with R4 and R7; D0 is connected with R5 and R8; D1 is connected with R6 and R9). Resistors R4, R5, R6 are connected to the left 2.1V level; r7, R8, R9 are connected to the right 2.1V level and 0.1uF fixed filter capacitances C4, C5, C6 are connected between the left 2.1V level and Digital Ground (DGND); between the right 2.1V level and Digital Ground (DGND) 0.1uF constant filter capacitances C7, C8, C9 are connected. When printed wiring is performed, characteristic impedance is controlled to 33 Ω uniformly for each set of bus signals (CK, D0, D1), and packet digital (DGND) processing is performed.
All resistors in the impedance matching circuit are precision resistors with the precision of F grade 1%, and all capacitors are ceramic dielectric capacitors, and the reference is made to fig. 3.
The invention provides a backboard designed based on a three-terminal voltage stabilizer, a precision resistor and a printed board, which is applied to an airborne computer system, and the backboard designed according to the circuit principle provided by the invention can meet the electrical characteristics required by the ARINC659 bus protocol.
Claims (3)
1. A backplane that satisfies ARINC659 bus electrical characteristics, comprising: the circuit comprises 4 groups of identical combination circuits, wherein each group of combination circuits comprises a voltage conversion circuit and an impedance matching circuit; the computer 5V power supply is connected with the voltage conversion circuit, and the converted 2.1V power supply is respectively connected with the impedance matching circuit from the left end and the right end of the back plate;
the voltage conversion circuit comprises a three-terminal voltage regulator N1, a first filter capacitor C1, a second filter capacitor C2, an energy storage capacitor C3, a resistor R1 and a resistor R2; the 5V power supply of the computer is divided into two paths after passing through a fuse F1, one path is connected with the input end of a three-terminal voltage regulator N1, the other path is connected with one end of a first filter capacitor C1, and the other end of C1 is connected with DGND; the adjusting end of the three-terminal voltage stabilizer N1 is divided into two paths, one path is connected with one end of a resistor R1 and one end of a resistor R2, and the other end of the resistor R2 is connected with DGND; the output end of the three-terminal voltage regulator N1 is divided into two paths, one path is connected with the other end of the R1, and the other path is output outwards; the second filter capacitor C2 and the energy storage capacitor C3 are respectively connected between the output end of the three-terminal regulator N1 and DGND;
each group of bus signals CK, D0 and D1 in the impedance matching circuit are respectively connected with 33 omega constant value resistors R4, R5, R7, R6, R8 and R9 at two ends of a backboard, and CK is connected with R4 and R7; d0 is connected with R5 and R8; d1 is connected with R6 and R9; resistors R4, R5, R6 are connected to the left 2.1V level; r7, R8, R9 are connected to the right 2.1V level and 0.1uF fixed filter capacitances C4, C5, C6 are connected between the left 2.1V level and Digital Ground (DGND); between the right 2.1V level and Digital Ground (DGND) 0.1uF constant filter capacitances C7, C8, C9 are connected.
2. The backplane according to claim 1, wherein said backplane comprises: the R1 resistance value: r2 resistance 4: 3.
3. the backplane according to claim 1, wherein said backplane comprises: when printed wiring is performed, characteristic impedance is uniformly controlled to be 33 Ω for each group of bus signals CK, D0, D1 in the impedance matching circuit, and packet Digital Ground (DGND) processing is performed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611155416.6A CN108228502B (en) | 2016-12-14 | 2016-12-14 | Back plate meeting electrical characteristics of ARINC659 bus |
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| CN201611155416.6A CN108228502B (en) | 2016-12-14 | 2016-12-14 | Back plate meeting electrical characteristics of ARINC659 bus |
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| CN108228502B true CN108228502B (en) | 2021-03-26 |
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| CN109144904A (en) * | 2018-08-30 | 2019-01-04 | 郑州云海信息技术有限公司 | A kind of SGPIO signal buffer circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101158868A (en) * | 2007-09-21 | 2008-04-09 | 江苏金智科技股份有限公司 | Double locomotive data interchange module based on bus low pressure differential signal transmission |
| CN101859166A (en) * | 2009-04-10 | 2010-10-13 | 黄勍 | Power supply device and computer case with the same |
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2016
- 2016-12-14 CN CN201611155416.6A patent/CN108228502B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101158868A (en) * | 2007-09-21 | 2008-04-09 | 江苏金智科技股份有限公司 | Double locomotive data interchange module based on bus low pressure differential signal transmission |
| CN101859166A (en) * | 2009-04-10 | 2010-10-13 | 黄勍 | Power supply device and computer case with the same |
Non-Patent Citations (3)
| Title |
|---|
| ARINC659背板总线的电气特性研究与设计改进;张晓敏 和 刘炜;《计算机测量与控制》;20141231;全文 * |
| LM317 THREE-TERMINAL ADJUSTABLE POSITIVE VOLTAGE REGULATOR;SEMICONDUCTOR TECHNICAL DATA;《ON Semiconductor》;20020131;正文第1页 * |
| 航空数字数据传输系统接口设计;高扬 和 徐景硕;《航空计算技术》;20011231;全文 * |
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