CN213069550U

CN213069550U - Radar signal controller based on PCIE interface

Info

Publication number: CN213069550U
Application number: CN202022274050.2U
Authority: CN
Inventors: 张建; 喻垚; 梁国超
Original assignee: Chengdu Zhongdian Avionics Technology Co ltd
Current assignee: Chengdu Zhongdian Avionics Technology Co ltd
Priority date: 2020-10-13
Filing date: 2020-10-13
Publication date: 2021-04-27
Anticipated expiration: 2030-10-13

Abstract

The utility model discloses a radar signal controller based on PCIE interface, include: FPGA, bridging chip, digital potentiometer, amplifier, external interface, SDRAM memory cell, JTAG interface, first crystal oscillator, second crystal oscillator and PCIE interface, FPGA connects gradually digital potentiometer, amplifier and external interface, FPGA connects the external interface through second voltage buffer, third voltage buffer, fourth voltage buffer respectively, the external interface passes through first voltage buffer and connects FPGA, FPGA connects SDRAM memory cell, FPGA is connected respectively to JTAG interface, FPGA connects bridging chip reconnection PCIE interface, second crystal oscillator connects bridging chip. The scheme improves the integration level of the equipment and reduces the cost of the equipment.

Description

Radar signal controller based on PCIE interface

Technical Field

The utility model relates to a radar signal control technical field, especially a radar signal controller based on PCIE interface.

Background

With the improvement of safety requirements of people on airplanes, the application technology of computers is increasingly wide, aviation airborne electronic equipment is increasingly complex, and full-automatic test equipment-ATE (automatic test equipment) is adopted for detection and maintenance of the aviation airborne electronic equipment abroad. At present, the integrated design is carried out on the market through a universal board card, and a digital IO board card, a digital DA card, a pulse signal generating card and a special signal generator card are needed. However, the existing radar signal controller has low integration level and high production cost.

SUMMERY OF THE UTILITY MODEL

The to-be-solved technical problem of the utility model is: in order to solve the above problems, a radar signal controller based on a PCIE interface is provided.

In order to achieve the above object, the utility model adopts the following technical scheme: a radar signal controller based on a PCIE interface comprises: FPGA, bridging chip, digital potentiometer, amplifier, external interface, SDRAM memory cell, JTAG interface, first crystal oscillator, second crystal oscillator and PCIE interface, FPGA connects gradually digital potentiometer, amplifier and external interface, FPGA connects the external interface through second voltage buffer, third voltage buffer, fourth voltage buffer respectively, the external interface passes through first voltage buffer and connects FPGA, FPGA connects SDRAM memory cell, FPGA is connected respectively to JTAG interface, FPGA connects bridging chip reconnection PCIE interface, second crystal oscillator connects bridging chip.

Further, the SDRAM storage unit comprises four parallel SDRAM storages.

Further, the radar signal controller based on the PCIE interface further includes a power supply, and the power supply is 12V.

Further, the digital potentiometer adopts a DS1267B chip.

Furthermore, the amplifier comprises an AD8018 chip, a first resistor, a second resistor, a third resistor and a fourth resistor, wherein a first pin of the AD8018 chip is sequentially connected with the first resistor and the second resistor and then grounded, the second pin is connected with the second resistor and then grounded, a seventh pin is sequentially connected with the third resistor and the fourth resistor and then grounded, and a sixth pin is connected with the fourth resistor and then grounded.

Further, the FPGA adopts an EP3C120F484I7N chip.

Furthermore, the external interface adopts a SCSI100 connector.

Compared with the prior art, the utility model discloses following beneficial effect has: the technical scheme of the utility model based on the PCIE interface, constituted the special standard card of radar signal controller, integrated digital IO integrated circuit board, digital DA card, the function of complicated pulse signal production card and special signal generator card can satisfy multiple model radar alarm test demand. The utility model discloses a radar signal controller based on PCIE interface, improve equipment's integrated level reduces equipment cost simultaneously.

Drawings

Fig. 1 is the utility model discloses radar signal controller's based on PCIE interface structural diagram.

Fig. 2 is a schematic diagram of an amplifier implementation structure according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings. It is to be understood that the embodiments described are only some embodiments of the invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it is noted that the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

As shown in fig. 1, a radar signal controller based on a PCIE interface includes: the FPGA is sequentially connected with the digital potentiometer, the amplifier and the external interface, the digital potentiometer and the amplifier form an amplitude modulation circuit to generate a plurality of paths of amplitude modulation signals and transmit the amplitude modulation signals to the external interface, the FPGA generates a plurality of paths of DO signals through a second voltage buffer from 3.3v to 5v, the FPGA generates a plurality of paths of complex pulse signals through a third voltage buffer from 3.3v to 5v, the FPGA generates a plurality of paths of self-checking signals through a fourth voltage buffer from 3.3v to 5v, the plurality of paths of DO signals, the complex pulse signals and the self-checking signals are transmitted to the external interface, the external interface outputs a plurality of paths of level self-checking signals and is connected to the FPGA through a first voltage buffer from 5v to 3.3v, the FPGA is connected with the SDRAM storage unit, the JTAG interface and the first crystal oscillator are respectively connected with an FPGA, the working frequency of the first crystal oscillator is 25MHz, the FPGA is connected with a bridging chip through a PCI (peripheral component interconnect) line, the bridging chip is connected with a PCIE (peripheral component interconnect express) interface through a PCIE (peripheral component interconnect express) line, the second crystal oscillator is connected with the bridging chip, and the working frequency of the second crystal oscillator is 66 MHz. In the embodiment, the functions of multi-channel amplitude modulation signal output, multi-channel complex pulse output, multi-channel self-detection signal output, multi-channel general IO output and multi-channel level self-detection acquisition are integrated on one PCIE interface board card.

Preferably, the selection of the FPGA needs to consider both the number of IO and the size of capacity. In this embodiment, the FPGA selects an EP3C120F484I7N chip, available IOs are 283, and the LE number is 119K. The RAM supports DDR2, DDR and SDR. The I/O standard supports PCI, PCI-X, LVTTL, LVCMOS, LVDS, LVPECL, SSTL-18, etc. The FPGA contains 4 PLLs. All the aspects can meet the current logic design requirement and the later requirement.

Preferably, the PCIE bridge chip selects a PI7C9X130 chip to realize the PCI Express to PCI-X reversible bridge.

Preferably, the amplitude modulation precision is designed to be: the voltage of 0.2V to 5V can be adjusted, the stepping is 100mV, and the error is 10 mV. An amplitude modulation circuit is formed by adopting a digital potentiometer and an amplifier. The register value of the digital potentiometer is controlled through the FPGA, and further the resistance value proportion of the digital potentiometer is controlled, so that the gain of the operational amplifier is controlled, and the final output voltage is adjusted within a certain range. Meanwhile, the pulse type of the output waveform is controlled through other IO pins of the FPGA. Finally, the purpose of simultaneously controlling the pulse type and the amplitude of the signal is achieved. The digital potentiometer of the embodiment adopts a DS1267B chip. As shown IN fig. 2, the amplifier includes an AD8018 chip, a first pin is connected to an OP _ OUT1 interface, the first pin is sequentially connected to a first resistor and a second resistor for further grounding, the second pin is connected to the second resistor for further grounding, a third pin is connected to an IN1_ OP1 interface, a fourth pin is connected to a-VS interface, a fifth pin is connected to an IN2_ OP2 interface, a sixth pin is connected to the fourth resistor for further grounding, a seventh pin is connected to an OP _ OUT2 interface, a seventh pin is sequentially connected to the third resistor and the fourth resistor for further grounding, and an eighth pin is connected to a + VS interface.

Preferably, the SDRAM memory unit comprises four parallel SDRAM memories, which are of type K4S 643232H.

Preferably, the radar signal controller based on the PCIE interface further includes a power supply, the board card obtains power from the PCIE slot, and the power supply voltage is 12V. The main power consumption devices are FPGA, operational amplifier and the like. The operational amplifier needs to adopt positive and negative power supplies. The positive power supply (e.g., +5V), negative power supply (e.g., -5V) are implemented using low cost MC 34063. Because the multi-chip operational amplifier needs to consume larger negative power supply current, the current can reach 1.5A at most by adopting the MC34063 external transistor current expansion mode. In addition, the FPGA and the level conversion chip also need voltage rails of +5V, +3.3V, 2.5V (needed by FPGA PLL), 1.2V (needed by FPGA core voltage and PLL digital part) and the like. Other voltages may be converted from + 5V.

Preferably, the external interface is a SCSI100 connector, and the definition of the interface can be set as in table 1 below according to actual needs.

TABLE 1

Finally, it should be noted that: the above embodiments are only preferred embodiments of the present invention to illustrate the technical solution of the present invention, but not to limit the same, and certainly not to limit the scope of the present invention; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention; that is, the technical problems solved by the present invention are still consistent with the present invention, and all the modifications or colors made in the spirit and the idea of the main design of the present invention are included in the protection scope of the present invention; in addition, will the technical scheme of the utility model direct or indirect application is in other relevant technical field, all including on the same reason the utility model discloses an in the patent protection scope.

Claims

1. A radar signal controller based on a PCIE interface is characterized by comprising: FPGA, bridging chip, digital potentiometer, amplifier, external interface, SDRAM memory cell, JTAG interface, first crystal oscillator, second crystal oscillator and PCIE interface, FPGA connects gradually digital potentiometer, amplifier and external interface, FPGA connects the external interface through second voltage buffer, third voltage buffer, fourth voltage buffer respectively, the external interface passes through first voltage buffer and connects FPGA, FPGA connects SDRAM memory cell, FPGA is connected respectively to JTAG interface, FPGA connects bridging chip reconnection PCIE interface, second crystal oscillator connects bridging chip.

2. The PCIE interface-based radar signal controller of claim 1, wherein the SDRAM storage unit comprises four SDRAM memories connected in parallel.

3. The PCIE interface-based radar signal controller of claim 1, wherein the PCIE interface-based radar signal controller further comprises a power supply, and the power supply is 12V.

4. The PCIE interface-based radar signal controller of claim 1, wherein the digital potentiometer employs a DS1267B chip.

5. The PCIE interface-based radar signal controller of claim 1, wherein the amplifier comprises an AD8018 chip, a first resistor, a second resistor, a third resistor, and a fourth resistor, a first pin of the AD8018 chip is sequentially connected to the first resistor and the second resistor for further grounding, a second pin of the AD8018 chip is connected to the second resistor for further grounding, a seventh pin of the AD8018 chip is sequentially connected to the third resistor and the fourth resistor for further grounding, and a sixth pin of the AD8018 chip is connected to the fourth resistor for further grounding.

6. The PCIE interface-based radar signal controller of claim 1, wherein the FPGA employs an EP3C120F484I7N chip.

7. The PCIE interface-based radar signal controller of claim 1, wherein the external interface employs a SCSI100 connector.