CN217035143U

CN217035143U - Terminal structure of DDR3 signal end

Info

Publication number: CN217035143U
Application number: CN202220948965.3U
Authority: CN
Inventors: 董一志; 周伟杨; 曹戎格
Original assignee: BDstar Intelligent and Connected Vehicle Technology Co Ltd
Current assignee: BDstar Intelligent and Connected Vehicle Technology Co Ltd
Priority date: 2022-04-22
Filing date: 2022-04-22
Publication date: 2022-07-22
Anticipated expiration: 2032-04-22

Abstract

The application provides terminal terminating structure of DDR3 signal relates to mobile unit technical field, includes: the device comprises a resistor and a capacitor, wherein one end of the resistor is connected with a system-on-chip through one or more pieces of serially connected DDR3, and the other end of the resistor is connected with the capacitor; the resistance value of the resistor is 50 ohms; the capacitance value of the capacitor is 100 uf. The method and the device reduce the hardware cost on the premise of not influencing the DDR signal quality.

Description

Terminal connection structure of DDR3 signal end

Technical Field

The application relates to the technical field of vehicle-mounted equipment, in particular to a terminal connection structure of a DDR3 signal terminal.

Background

DDR3 memory has push-pull output buffering, while the input receiver is a differential stage, requiring a reference bias midpoint VREF. Therefore, the DDR3 memory needs an input voltage terminal capable of supplying current and sinking current. The current multi-chip DDR3 interconnection method has the disadvantage of high cost because a pull-up resistance of 0.75v is added to the signal terminal and a power supply of 0.75v is adopted.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present application provides a termination structure of DDR3 signal terminals to solve the above-mentioned problems.

The embodiment of the application provides a terminal structure of DDR3 signal end, includes: the device comprises a resistor and a capacitor, wherein one end of the resistor is connected with a system-on-chip through a plurality of serially connected DDR3, and the other end of the resistor is connected with the capacitor; the resistance value of the resistor is 50 ohms; the capacitance value of the capacitor is 100 uf.

Further, the capacitor is grounded.

Further, the system-on-chip, the plurality of DDR3 and the resistor are connected through an address line.

Further, the system-on-chip provides a supply voltage of 1.5V, and the voltage of the capacitor is stabilized at about 0.75V.

Further, the number of the DDR3 is 4.

The method and the device reduce the hardware cost on the premise of not influencing the DDR signal quality.

Drawings

In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings used in the detailed description or the prior art description will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic diagram of a termination structure of a DDR3 signal termination according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, as presented in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

First, the design idea of the embodiment of the present application is briefly introduced.

DDR3 memory has push-pull output buffering, while the input receiver is a differential stage, requiring a reference bias midpoint VREF. Therefore, the DDR3 memory needs an input voltage terminal capable of supplying current and sinking current. When multiple pieces of DDR3 are interconnected, 0.75v pull-up resistance is added to the signal end, and a 0.75v power supply is adopted, so that the method has the disadvantage of high cost.

In order to solve the above technical problem, an embodiment of the present application provides a termination structure of a DDR3 signal end, including: a 50 ohm resistor and a 100uf capacitor, which can save the cost of a power supply without affecting the signal quality.

The signal quality requirement of DDR3 is met with low cost, and the method has the advantage of low cost.

After introducing the application scenario and the design idea of the embodiment of the present application, the following describes a technical solution provided by the embodiment of the present application.

As shown in fig. 1, the present application provides a termination structure of a DDR3 signal termination, including: the device comprises a resistor and a capacitor, wherein one end of the resistor is connected with a System On Chip (SOC) through one or more pieces of serially connected DDR3, and the other end of the resistor is connected with the capacitor; the resistance value of the resistor is 50 ohms; the capacitance value of the capacitor is 100 uf. The capacitor is grounded.

Preferably, the number of the DDRs 3 is 4.

The system-level chip, the DDR3 and the resistor are connected through an address line.

In this embodiment, the power supply voltage of the SOC is 1.5V, since the level of the address line is continuously jittered, and in 2 adjacent clock cycles, there are both high level and low level, it can be known from the charge and discharge formula of the capacitor that, when the capacitor is smaller than 0.75V, the voltage charged by the capacitor at high level is much greater than the voltage discharged by the capacitor at low level, so the voltage on the capacitor will continuously rise when the capacitor is jittered until it reaches 0.75V, which will basically be maintained at about 0.75V, and will change very slowly when it approaches 0.75V, which is also beneficial for the address line to stably maintain 0.75V voltage when the level is uncertain, and the actual ripple test is about ten millivolts.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A termination structure for a DDR3 signal termination, comprising: the circuit comprises a resistor and a capacitor, wherein one end of the resistor is connected with a system-on-chip through a plurality of pieces of DDR3 connected in series, and the other end of the resistor is connected with the capacitor; the resistance value of the resistor is 50 ohms; the capacitance value of the capacitor is 100 uf.

2. The termination structure at the signal termination of DDR3 of claim 1, wherein said capacitor is coupled to ground.

3. The termination structure for DDR3 signal terminals according to claim 1, wherein the system-on-chip, DDR3 and resistor are connected via address lines.

4. The termination structure of the DDR3 signal terminal of claim 1, wherein the system on chip provides a supply voltage of 1.5V, and the capacitor is stabilized at a voltage of about 0.75V.

5. The termination structure at the signal end of DDR3, wherein the number of DDR3 is 4.