CN219145076U - Quick charging circuit - Google Patents
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- CN219145076U CN219145076U CN202320135240.7U CN202320135240U CN219145076U CN 219145076 U CN219145076 U CN 219145076U CN 202320135240 U CN202320135240 U CN 202320135240U CN 219145076 U CN219145076 U CN 219145076U
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Abstract
The utility model provides a quick charging circuit which is characterized by comprising a power adapter, mobile terminal equipment, a protocol control circuit, a switch circuit, a D+ control circuit and a D-control circuit, wherein the input end of the protocol control circuit is respectively connected with the VCC end of the power adapter and the mobile terminal equipment, and the output end of the protocol control circuit is respectively connected with the D+ control circuit and the D-control circuit; the first side of the switch circuit is connected with the D+ and D-ends of the power adapter respectively, the connection of the second side of the switch circuit is selectively divided into two groups, the first group is connected with the D+ control circuit and the D-control circuit respectively, the second group is connected with the D+ and D-ends of the CPU of the mobile terminal device respectively, the switch circuit is arranged to select one group between the two groups of connection of the second side to be connected with the first side, so that the D+ and D-ends of the power adapter are connected with the D+ and D-ends of the CPU of the mobile terminal device respectively, or the D+ and D-ends of the power adapter are connected with the D+ control circuit and the D-control circuit.
Description
Technical Field
The utility model relates to the technical field of electronics, in particular to a quick charging circuit compatible with QC protocols and used for mobile terminal equipment (particularly mobile phones and POS equipment).
Background
The QC Quick Charge protocol (high-pass Quick Charge protocol) is a Quick Charge protocol commonly used for electronic equipment, the electronic equipment outputs voltage signals to a charging adapter through a USB data communication port D+ and a D-end, and a USB decoding chip arranged in the charging adapter judges the voltage to be output. Typically, industry standards are: 5V, 9V, 12V, and 20V output voltages. Currently, most mobile terminal devices (including mobile phones, POS devices, etc.) support QC fast-charge protocols.
Fig. 1 and fig. 2 show a charging circuit technical scheme supporting QC fast charging protocol in the prior art, in which a control circuit is added to d+, D-of an electricity module. The D+ is designed at 0.6V through voltage division, the D-is designed at 0.6V through a delay circuit and a bleeder circuit, the QC fast charging adapter recognizes that the D+ and the D-voltages are all at 0.6V, a fast charging protocol is triggered, the QC adapter outputs 12V voltage, and the output power is improved, so that the fast charging function is realized.
However, the technical solution described above has the following drawbacks: 1. d+ and D-control circuits are directly loaded on the power utilization module, so that communication can be influenced, and data transmission failure is caused; 2. the d+ and D-voltages are designed to be 0.6V, the adapter outputs 12V, and the power module of some mobile terminal devices (e.g., POS devices) does not need such a high charging voltage, otherwise, the voltage resistance problem is brought to the device, and the high voltage also generates higher heat, so that the electronic device heats up, and the battery life is reduced.
Disclosure of Invention
The utility model aims at the defects of the prior art and provides an improved quick charging circuit compatible with QC quick charging protocol. The improved quick charging circuit is added with a protocol control circuit and a switching circuit on the basis of the original quick charging circuit in the prior art, and modifies a D+ and D-control circuit, so that the improved quick charging circuit is more in line with the actual charging requirements and applications of mobile terminal equipment (such as mobile phones, POS equipment and the like).
In order to achieve the above object, the present utility model provides a fast charging circuit for fast charging a mobile terminal device supporting QC fast charging protocol, wherein the fast charging circuit comprises a power adapter, a mobile terminal device, a protocol control circuit, a switching circuit, a d+ control circuit and a D-control circuit,
the input end of the protocol control circuit is respectively connected with the VCC end of the power adapter and the mobile terminal equipment, and the output end of the protocol control circuit is respectively connected with the D+ control circuit and the D-control circuit;
the first side of the switch circuit is connected with the D+ and D-ends of the power adapter respectively, the connection of the second side of the switch circuit is selectively divided into two groups, the first group is connected with the D+ control circuit and the D-control circuit respectively, the second group is connected with the D+ and D-ends of the CPU of the mobile terminal device respectively, the switch circuit is arranged to select one group between the two groups of connection of the second side to be connected with the first side, so that the D+ and D-ends of the power adapter are connected with the D+ and D-ends of the CPU of the mobile terminal device respectively, or the D+ and D-ends of the power adapter are connected with the D+ control circuit and the D-control circuit respectively.
According to a preferred embodiment of the present utility model, the protocol control circuit includes a PMOS transistor, a first NPN transistor, a first resistor, a first capacitor, and a second resistor.
The first resistor and the first capacitor are connected in parallel, one end of the first resistor and the first capacitor are connected with the VCC input of the power adapter, and the other end of the first resistor and the first capacitor is connected with the grid electrode of the PMOS tube;
the source electrode of the PMOS tube is connected with the VCC input of the power adapter, the drain electrode of the PMOS tube is used as the output end of the protocol control circuit, and the output end is respectively connected with the D+ control circuit and the D-control circuit and used as the power supplies of the D+ control circuit and the D-control circuit;
one end of the second resistor is connected with the grid electrode of the PMOS, and the other end of the second resistor is connected with the collector electrode of the NPN tube;
the base electrode of the first NPN tube is connected with a control signal CTRL of the mobile terminal device CPU, the emitter electrode of the first NPN tube is grounded, and the first NPN tube is provided with a built-in resistor.
According to a preferred embodiment of the utility model, the switching circuit comprises a two-way analog switch, a third resistor, and a second capacitor.
The 6 th pin and the 7 th pin of the two-way analog switch are respectively connected with the D+ end and the D-end of the power adapter, the 2 nd pin and the 3 rd pin of the two-way analog switch are respectively connected with the D-end and the D+ end of the mobile terminal equipment CPU, the 10 th pin and the 1 st pin of the two-way analog switch are respectively connected with the D-control circuit and the D+ control circuit, the 4 th pin and the 8 th pin ALP_SEL of the two-way analog switch are grounded, the 5 th pin of the two-way analog switch is connected with a 3.3V power supply, and the 9 th pin of the two-way analog switch is connected with a control signal CTRL of the mobile terminal equipment CPU;
one end of the second capacitor is connected with the 5 th pin of the two-way analog switch, and the other end of the second capacitor is connected with the 4 th pin of the two-way analog switch;
one end of the third resistor is connected with the 9 th pin of the two-way analog switch, and the other end of the third resistor is grounded.
According to a preferred embodiment of the present utility model, the d+ control circuit includes a fourth resistor, a fifth resistor and a sixth resistor.
One end of the fourth resistor is connected with the drain electrode of the PMOS tube of the protocol control circuit, and the other end of the fourth resistor is respectively connected with the fifth resistor and the sixth resistor;
one end of the fifth resistor is connected with the fourth resistor, and the other end of the fifth resistor is grounded;
one end of the sixth resistor is connected with the fourth resistor and the fifth resistor, and the other end of the sixth resistor is used as the output of the D+ control circuit.
Preferably, the ratio of the resistance of the fourth resistor to the resistance of the sixth resistor is less than or equal to 1:1.5, and the resistance of the fifth resistor is a current limiting resistor, and the resistance of the fifth resistor is 1000 ohms. More preferably, the resistance of the fourth resistor is 200 ohms, and the resistance of the sixth resistor is 300 ohms.
Alternatively, the d+ control circuit includes a regulator tube, the voltage of which is maintained above 1.925V, preferably at about 3V.
According to a preferred embodiment of the present utility model, the D-control circuit includes a third capacitor, a fourth capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first diode, a second diode, a third diode, and a second NPN tube.
The third capacitor is used as a filter capacitor, one end of the third capacitor is connected with the drain electrode of the PMOS tube of the protocol control circuit, and the other end of the third capacitor is grounded;
the eighth resistor, the ninth resistor and the first diode form a bleeder circuit;
the seventh resistor and the tenth resistor form a voltage dividing circuit of the input voltage;
the twelfth resistor and the fourteenth resistor form a voltage dividing circuit of the output voltage;
the eleventh resistor and the fourth capacitor form a power-on delay circuit of the D-control circuit;
the second NPN tube is used as a switch, and the second diode and the third diode are connected with the emitter of the second NPN tube, so that the voltage clamp is 1.4V when the second NPN tube is conducted, and saturated conduction is ensured.
Preferably, the resistance value of the eleventh resistor is 200kΩ, the fourth capacitor is 15uF, the resistance values of the eighth resistor and the ninth resistor are both 4.7kΩ, and the resistance values of the seventh resistor and the tenth resistor are both 100kΩ.
According to a preferred embodiment of the utility model, the mobile terminal device comprises a mobile phone and a POS device.
The quick charging circuit for charging the mobile terminal equipment supporting the QC quick charging protocol has the following beneficial technical effects:
first, problems related to the interference of charging on data communication: the fast charging circuit of the utility model is added with a protocol control circuit and a switching circuit, and the output of the protocol control circuit and the switching of the switching circuit are controlled by the control signal CTRL of the CPU of the mobile terminal equipment. On the one hand, in a default state (when USB data transmission is needed), the protocol control circuit is not conducted and has no output, and the switch circuit is connected to enable the D+ end and the D-end of the mobile terminal device CPU to be directly connected with the D+ end and the D-end of the power adapter J1 terminal, so that the data transmission is not interfered, and the integrity of the data transmission is ensured. On the other hand, when the software enumeration does not recognize the communication signal, the protocol control circuit is started through the control signal CTRL of the CPU of the mobile terminal device, and the switch circuit is switched to the D+ and D-control circuit, so that the power adapter starts the QC fast charging protocol to rapidly charge the mobile terminal device.
Secondly, regarding the problem that the fast charging output voltage of the power adapter is too high: the fast charging circuit of the present utility model modifies the d+ control circuit and the D-control circuit, respectively. On the one hand, the D+ control circuit is designed to be above 1.925V through a voltage division circuit, and is preferably set to be 3.3V; on the other hand, the D-circuit is designed between 0.325V and 1.925V through the voltage dividing circuit, so that the output voltage of the QC quick-charging adapter is reduced, the output voltage of the adapter is reduced to 9V from 12V in the prior art, the utilization rate of energy efficiency is improved, and the withstand voltage problem of devices is reduced.
In addition, the fast charging circuit also modifies the D-control circuit, improves the resistance of the seventh resistor and the tenth resistor of the voltage dividing circuit, and reduces the capacitance of the fourth capacitor, thereby realizing miniaturized packaging and reducing the leakage current of the capacitor.
Drawings
The present utility model will be described in further detail with reference to the accompanying drawings. Those skilled in the art will readily appreciate that these drawings are for illustrative purposes only and are not intended to limit the scope of the present utility model. The same reference numbers will be used throughout the drawings to refer to the same or like parts. For purposes of illustration, the figures are not drawn to scale entirely.
Fig. 1 shows a block diagram of a prior art fast charge circuit supporting QC fast charge protocol.
Fig. 2 shows a circuit diagram of a prior art fast charge circuit as shown in fig. 1.
Fig. 3 shows a circuit diagram of a protocol control circuit according to an embodiment of the utility model.
Fig. 4 shows a circuit diagram of a switching circuit according to an embodiment of the utility model.
Fig. 5 shows a circuit diagram of a d+ control circuit according to an embodiment of the utility model.
Fig. 6 shows a circuit diagram of a D-control circuit according to an embodiment of the utility model.
Fig. 7 shows a block diagram of a fast charge circuit supporting QC fast charge protocol in accordance with one embodiment of the present utility model.
Fig. 8 shows a flow chart of a handshake protocol procedure according to an embodiment of the utility model.
Detailed Description
It will be appreciated by those skilled in the art that the following examples are only for the purpose of more clearly describing the technical solution of the present utility model and are not intended to limit the scope of the present utility model in any way.
Fig. 7 shows an overall frame structure diagram of the fast charge circuit 1 supporting the QC fast charge protocol according to one embodiment of the utility model. The fast charging circuit 1 is used for fast charging a mobile terminal device 102 supporting QC fast charging protocol, and the mobile terminal device 102 may be, for example, a mobile phone or a POS device. The fast charge circuit 1 includes a power adapter 101, a mobile terminal device 102, a protocol control circuit 103, a switch circuit 104, a d+ control circuit 105, and a D-control circuit 106. An input terminal of the protocol control circuit 103 is connected to the VCC terminal of the power adapter 101 and the mobile terminal device 102, respectively, and an output terminal of the protocol control circuit 103 is connected to the d+ control circuit 105 and the D-control circuit 106, respectively. The first side of the switching circuit 104 is connected to the d+ and D-terminals of the power adapter 101, respectively, the connection of the second side of the switching circuit (the side opposite to the first side) is selectively divided into two groups, the first group is connected to the d+ control circuit 105 and the D-control circuit 106, respectively, the second group is connected to the d+ and D-terminals of the CPU of the mobile terminal device 102, respectively, so that the switching circuit 104 is arranged to select a group to be connected to the first side between the two groups of connections on the second side, thereby directly connecting the d+ and D-terminals of the power adapter 101 to the d+ and D-terminals of the CPU of the mobile terminal device 102, or the d+ and D-terminals of the power adapter 101 are connected to the d+ control circuit 105 and the D-control circuit 106, respectively.
Fig. 3 to 6 show circuit diagrams of the protocol control circuit 103, the switching circuit 104, the d+ control circuit 105 and the D-control circuit 106, respectively, according to an embodiment of the present utility model.
As shown in fig. 3, the protocol control circuit 103 is composed of a PMOS transistor Q11, a first resistor R78, a first capacitor C75, a second resistor R44, and a first NPN transistor Q9. Wherein, R78 and C75 are connected in parallel, one end of which is connected with the source electrode of Q11, and the other end is connected with the grid electrode of Q11. The source of Q11 is connected with the VCC input end of the power adapter 101; the drain of Q11 outputs 5v_d, and the output of the protocol control circuit 103 is used as power supply for the d+ control circuit 105 and D-control circuit 106 at the back end. R44 has one end connected to the gate of Q11 and the other end connected to the collector of Q9. The output signal QC2.0_CTRL of the CPU of the mobile terminal device 102 is used as a control signal and is connected with the base electrode of Q9, and the emitter electrode of Q9 is grounded GND.
As shown in fig. 4, the switching circuit 104 is composed of a two-way analog switch WAS4768Q, a third resistor R3, and a second capacitor C11. The 6 th and 7 th pins of the two-way analog switch are connected with D-, D+ ends of a J1 terminal of the power adapter 101, the 2 nd and 3 rd pins are connected with D-, D+ ends of a CPU pin of the mobile terminal equipment 102, the 10 th and 1 st pins are respectively connected with a D-control circuit 106 and a D+ control circuit 105, the 8 th pin ALP_SEL is grounded GND, a C11 capacitor is connected between the 5 th pin and the 4 th pin, the 5 th pin is connected with 3.3V voltage of the system, the 9 th pin is connected with QC2.0_CTRL control signals of the CPU of the mobile terminal equipment 102, one end of R3 is connected with the 9 th pin, and the other end of the R3 is grounded GND.
As shown in fig. 5, the d+ control circuit 105 is composed of a fourth resistor R10, a fifth resistor R11, and a sixth resistor R12. Wherein, one end of R10 is connected with the output end 5V_D of the protocol control circuit 103, and the other end of R10 is respectively connected with R11 and R12; the other end of R12 is grounded to GND, and the other end of R11 is connected to QC2.0_D+ pin as the output of D+ control circuit 105. Preferably, R11 is a current limiting resistor, which may take the value of 1kΩ. Voltage V of qc2.0_d+ pin QC2.0_D+ And is greater than 1.925V, so that the ratio of R10 to R12 is less than or equal to 1:1.5. preferably, R10 and R12 can take the values 200Ω and 300Ω, then V QC2.0_D+ The output voltage is about 3V, which meets the requirement.
Alternatively, in an embodiment not shown, the D+ control circuit 105 may also use an AMS1117-3.3 regulator or other regulator to achieve the voltage output requirements of the QC2.0_D+ pin described above, with the voltage of the regulator remaining above 1.925V, preferably at about 3V.
As shown in fig. 6, the D-control circuit 106 is composed of third and fourth capacitors C1, C2, seventh to fifteenth resistors R1, R2, R13, R4, R5, R6, R7, R8, R9, first to third diodes D1, D2, D3, and a second transistor (NPN tube) Q1. The capacitor C1 is used as a filter capacitor, one end of which is connected to the output terminal 5v_d of the protocol control circuit 103, and the other end of which is grounded to GND, preferably having a value of 10nF. The resistors R2, R13 and the diode D1 form a bleeder circuit. The resistors R1 and R4 form a capacitor charging voltage circuit, the resistors R5 and C2 form a delay circuit, the D2 and D3 are connected with the emitter of the Q1, so that the voltage clamp is 1.4V when the resistor is conducted, and the resistors R6 and R8 form an output voltage division circuit. Preferably, the D-control circuit shown in fig. 6 has a delay time of 2.5S, where r1=r4, and the charging voltage is 2.5V. Vq1=vdd [1-e ] according to the calculation formula -t/RC ]Taking here rc=3, r5=200kΩ, c2=15uf, assuming that C2 is fully discharged within 50ms after power failure of the power adapter, r2=r13 < 5.7kΩ is required, preferably r2=r13=4.7kΩ is required here, and r1=r4 > r2 is required (resistance values of the resistors R1, R4 are much larger than the resistance value of R2), preferably r1=r4=100deg.kΩ is required here.
Fig. 8 shows a flow chart of a handshake protocol procedure when powering on a connection of the fast charging circuit 1 according to one embodiment of the utility model with the mobile terminal device 102. The method comprises the following specific steps:
when the power adapter 101 and the mobile terminal device 102 handshake, the mobile terminal device 102 will signal whether to perform fast charging or not through the qc2.0_ctrl control signal. If the output is a low level signal, the switch circuit 104 is switched to the L/R end (pins 2 and 3 in FIG. 4), the protocol control circuit 103 is not conducted, the voltage of the D+ control circuit and the D-control circuit is 0V, the USB communication is not affected, and the mobile terminal device 102 normally communicates; if the output is a high level signal, the switch circuit 104 is switched to the d+ control circuit and the D-control circuit, at this time, the protocol control circuit 103 is turned on, and the power adapter 101 provides a 5V voltage output for the protocol control circuit 103, so that the output of the d+ control circuit is 3V, the output of the D-control circuit is 0.6V after 2.5S delay, thereby conforming to the QC fast charging protocol, and the output voltage of the power adapter 101 is 9V, so as to achieve the fast charging purpose.
The accompanying drawings and the foregoing description describe non-limiting specific embodiments of the present utility model. Some conventional aspects have been simplified or omitted in order to teach the inventive principles. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the utility model. Those skilled in the art will appreciate that the features described above can be combined in various ways to form multiple variations of the utility model. Thus, the present utility model is not limited to the specific embodiments described above, but only by the claims and their equivalents.
Claims (11)
1. The fast charging circuit is used for fast charging mobile terminal equipment supporting QC fast charging protocol and is characterized by comprising a power adapter, mobile terminal equipment, a protocol control circuit, a switch circuit, a D+ control circuit and a D-control circuit, wherein the input end of the protocol control circuit is respectively connected with the VCC end of the power adapter and the mobile terminal equipment, and the output end of the protocol control circuit is respectively connected with the D+ control circuit and the D-control circuit;
the first side of the switch circuit is connected with the D+ and D-ends of the power adapter respectively, the connection of the second side of the switch circuit is selectively divided into two groups, the first group is connected with the D+ control circuit and the D-control circuit respectively, the second group is connected with the D+ and D-ends of the CPU of the mobile terminal device respectively, the switch circuit is arranged to select one group between the two groups of connection of the second side to be connected with the first side, so that the D+ and D-ends of the power adapter are connected with the D+ and D-ends of the CPU of the mobile terminal device respectively, or the D+ and D-ends of the power adapter are connected with the D+ control circuit and the D-control circuit respectively.
2. The fast charge circuit of claim 1, wherein the protocol control circuit comprises a PMOS transistor, a first NPN transistor, a first resistor, a first capacitor, and a second resistor, wherein the first resistor and the first capacitor are connected in parallel, one end of which is connected to the VCC input of the power adapter, and the other end of which is connected to the gate of the PMOS transistor;
the source electrode of the PMOS tube is connected with the VCC input of the power adapter, the drain electrode of the PMOS tube is used as the output end of the protocol control circuit, and the output end is respectively connected with the D+ control circuit and the D-control circuit and used as the power supplies of the D+ control circuit and the D-control circuit;
one end of the second resistor is connected with the grid electrode of the PMOS, and the other end of the second resistor is connected with the collector electrode of the NPN tube; the base electrode of the first NPN tube is connected with a control signal CTRL of the mobile terminal device CPU, the emitter electrode of the first NPN tube is grounded, and the first NPN tube is provided with a built-in resistor.
3. The quick charge circuit according to claim 1 or 2, wherein the switching circuit comprises a two-way analog switch, a third resistor, and a second capacitor,
the 6 th pin and the 7 th pin of the two-way analog switch are respectively connected with the D+ end and the D-end of the power adapter, the 2 nd pin and the 3 rd pin of the two-way analog switch are respectively connected with the D-end and the D+ end of the mobile terminal equipment CPU, the 10 th pin and the 1 st pin of the two-way analog switch are respectively connected with the D-control circuit and the D+ control circuit, the 4 th pin and the 8 th pin ALP_SEL of the two-way analog switch are grounded, the 5 th pin of the two-way analog switch is connected with a 3.3V power supply, and the 9 th pin of the two-way analog switch is connected with a control signal CTRL of the mobile terminal equipment CPU;
one end of the second capacitor is connected with the 5 th pin of the two-way analog switch, and the other end of the second capacitor is connected with the 4 th pin of the two-way analog switch;
one end of the third resistor is connected with the 9 th pin of the two-way analog switch, and the other end of the third resistor is grounded.
4. The fast charging circuit according to claim 1 or 2, wherein the D+ control circuit comprises a fourth resistor, a fifth resistor and a sixth resistor,
one end of the fourth resistor is connected with the drain electrode of the PMOS tube of the protocol control circuit, and the other end of the fourth resistor is respectively connected with the fifth resistor and the sixth resistor;
one end of the fifth resistor is connected with the fourth resistor, and the other end of the fifth resistor is grounded;
one end of the sixth resistor is connected with the fourth resistor and the fifth resistor, and the other end of the sixth resistor is used as the output of the D+ control circuit.
5. The quick charge circuit as recited in claim 4 wherein the ratio of the fourth resistor to the sixth resistor is less than or equal to 1:1.5, and the fifth resistor is a current limiting resistor having a resistance of 1000 ohms.
6. The quick charge circuit of claim 5 wherein the fourth resistor has a resistance of 200 ohms and the sixth resistor has a resistance of 300 ohms.
7. The fast charge circuit of claim 1 or 2, wherein the d+ control circuit comprises a regulator tube, the voltage of the regulator tube being maintained above 1.925V.
8. The fast charge circuit of claim 7 wherein the voltage of the regulator tube is maintained at 3V.
9. The quick charge circuit according to claim 1 or 2, wherein the D-control circuit comprises a third capacitor, a fourth capacitor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first diode, a second diode, a third diode, a second NPN tube,
the third capacitor is used as a filter capacitor, one end of the third capacitor is connected with the drain electrode of the PMOS tube of the protocol control circuit, and the other end of the third capacitor is grounded;
the eighth resistor, the ninth resistor and the first diode form a bleeder circuit;
the seventh resistor and the tenth resistor form a voltage dividing circuit of the input voltage;
the twelfth resistor and the fourteenth resistor form a voltage dividing circuit of the output voltage;
the eleventh resistor and the fourth capacitor form a power-on delay circuit of the D-control circuit; the second NPN tube is used as a switch, and the second diode and the third diode are connected with the emitter of the second NPN tube, so that the voltage clamp is 1.4V when the second NPN tube is conducted, and saturated conduction is ensured.
10. The quick charge circuit of claim 9 wherein the eleventh resistor has a resistance of 200kΩ, the fourth capacitor has a resistance of 15uF, the eighth resistor and the ninth resistor each have a resistance of 4.7kΩ, and the seventh resistor and the tenth resistor each have a resistance of 100kΩ.
11. A quick charge circuit as claimed in claim 1 or 2 wherein the mobile terminal device comprises a cell phone and a POS device.
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| CN202320135240.7U CN219145076U (en) | 2023-01-11 | 2023-01-11 | Quick charging circuit |
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| CN202320135240.7U CN219145076U (en) | 2023-01-11 | 2023-01-11 | Quick charging circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117293978A (en) * | 2023-11-27 | 2023-12-26 | 合肥联宝信息技术有限公司 | Quick-charging interface circuit supporting wide voltage and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117293978A (en) * | 2023-11-27 | 2023-12-26 | 合肥联宝信息技术有限公司 | Quick-charging interface circuit supporting wide voltage and electronic equipment |
| CN117293978B (en) * | 2023-11-27 | 2024-02-23 | 合肥联宝信息技术有限公司 | Quick-charging interface circuit supporting wide voltage and electronic equipment |
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Address after: Floor 3-4, Building 3A, Zone A, Fuzhou Software Park, No. 89, Software Avenue, Gulou District, Fuzhou City, Fujian Province, 350001 Patentee after: Yinjie Nico (Fujian) Technology Co.,Ltd. Address before: Floor 3-4, Building 3A, Zone A, Fuzhou Software Park, No. 89, Software Avenue, Gulou District, Fuzhou City, Fujian Province, 350001 Patentee before: Fujian Liandi Commercial Technology Co.,Ltd. |