CN216287519U - Drive chip test circuit and system - Google Patents
Drive chip test circuit and system Download PDFInfo
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- CN216287519U CN216287519U CN202122391202.1U CN202122391202U CN216287519U CN 216287519 U CN216287519 U CN 216287519U CN 202122391202 U CN202122391202 U CN 202122391202U CN 216287519 U CN216287519 U CN 216287519U
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Abstract
The application discloses driver chip test circuit and system for improving test efficiency. The drive chip test circuit that this application embodiment provided includes: the control module, the program control voltage module and the signal conversion module; the control module is connected with the program control voltage module and the signal conversion module through a control interface and a test interface respectively and is used for generating a control signal and a test signal; the program control voltage module is connected with a voltage input interface of the signal conversion module and used for generating preset voltages with different amplitudes according to the control signal; the signal conversion module is in communication connection with the driving chip to be detected and is used for converting the voltage amplitude of the test signal according to the preset voltage and outputting the voltage amplitude to the driving chip to be detected so as to detect the driving chip to be detected.
Description
Technical Field
The application relates to the technical field of liquid crystal display detection, in particular to a drive chip test circuit and a drive chip test system.
Background
Liquid Crystal Displays (LCDs) have many advantages such as thin body, power saving, no radiation, etc., and have been widely used in the field of digital products. A liquid crystal display module (LCM), which is an important component of a liquid crystal display, generally displays an image by driving an Integrated Circuit Chip (IC). In order to ensure the performance and stability of the display product, verification tests on the driving IC are often required, for example, the stability of the driving IC under different driving voltages is tested.
However, the existing driver IC test system is limited by the amplitude of the communication signal of the micro control unit of the test system, and can usually only test the same type of driver chips with a single same voltage specification, and the application range is narrow, that is, the 1.8V test system can only test the stability of the IC under the 1.8V driver voltage, but cannot directly test the stability of the IC under other different voltages, so when testing the stability of the IC under other different voltages, a new test system is usually required to be replaced, the production cost is additionally increased, or the amplitude conversion is performed on the level conversion chip added to the original test system, but the reference voltage needs to be manually modified each time, so that the test efficiency is low, and the universality is not strong.
SUMMERY OF THE UTILITY MODEL
The embodiment of the application provides a driver chip test circuit and a driver chip test system, which are used for improving test efficiency.
The embodiment of the application provides a driver chip test circuit, driver chip test circuit includes: the control module, the program control voltage module and the signal conversion module;
the control module is connected with the program control voltage module and the signal conversion module through a control interface and a test interface respectively and is used for generating a control signal and a test signal;
the program control voltage module is connected with a voltage input interface of the signal conversion module and used for generating preset voltages with different amplitudes according to the control signal;
the signal conversion module is in communication connection with the driving chip to be detected and is used for converting the voltage amplitude of the test signal according to the preset voltage and outputting the voltage amplitude to the driving chip to be detected so as to detect the driving chip to be detected.
Optionally, the control module comprises a single chip microcomputer; the singlechip is provided with a plurality of test interfaces and a control interface internally provided with a digital-to-analog conversion module.
Optionally, the control interface comprises: a first control interface and a second control interface;
the first control interface is to: generating a first control signal;
the second control interface is to: a second control signal is generated.
Optionally, the program-controlled voltage module includes: a first voltage module and a second voltage module;
the first voltage module is connected with the first control interface and used for generating a first preset voltage according to the first control signal;
the second voltage module is connected with the second control interface and used for generating a second preset voltage according to the second control signal.
Optionally, the first voltage module comprises: a first multiplier, and a first voltage follower;
the second voltage module includes: a second multiplier, and a second voltage follower;
the input end of the first multiplier is used for receiving a first control signal, the first multiplier is used for generating a first preset voltage according to the first control signal, and the output end of the first multiplier is electrically connected with the input end of the first voltage follower; the output end of the first voltage follower is used for outputting a first preset voltage;
the input end of the second multiplier is used for receiving a second control signal, the second multiplier is used for generating a second preset voltage according to the second control signal, and the output end of the second multiplier is electrically connected with the input end of the second voltage follower; the output end of the second voltage follower is used for outputting a second preset voltage; the first preset voltage and the second preset voltage are not equal.
Optionally, the first multiplier comprises: a first operational amplifier, a first resistor, a second resistor, and a third resistor;
the second multiplier includes: a second operational amplifier, a fourth resistor, a fifth resistor, and a sixth resistor;
the positive phase input end of the first operational amplifier is electrically connected with one end of the third resistor, and the negative phase input end of the first operational amplifier is electrically connected with one end of the first resistor and one end of the second resistor; the output end of the first operational amplifier is electrically connected with the input end of the first voltage follower and the other end of the second resistor;
the other end of the first resistor is grounded;
the other end of the third resistor is used for receiving a first control signal;
the positive phase input end of the second operational amplifier is electrically connected with one end of the sixth resistor, and the negative phase input end of the second operational amplifier is electrically connected with one end of the fourth resistor and one end of the fifth resistor; the output end of the second operational amplifier is electrically connected with the input end of the second voltage follower and the other end of the fifth resistor;
the other end of the fourth resistor is grounded;
the other end of the sixth resistor is used for receiving a second control signal.
Optionally, the first voltage follower comprises: a third operational amplifier;
the positive phase input end of the third operational amplifier is electrically connected with the output end of the first multiplier, and the negative phase input end of the third operational amplifier is electrically connected with the output end of the third operational amplifier; the output end of the third operational amplifier is used for outputting a first preset voltage;
the second voltage follower includes: a fourth operational amplifier;
the positive phase input end of the fourth operational amplifier is electrically connected with the output end of the second multiplier, and the negative phase input end of the fourth operational amplifier is electrically connected with the output end of the fourth operational amplifier; the output end of the fourth operational amplifier is used for outputting a second preset voltage.
Optionally, the signal conversion module comprises: a multi-channel bidirectional level conversion chip;
the multichannel bidirectional level conversion chip includes: the test circuit comprises a first voltage input interface for receiving a first preset voltage, a second voltage input interface for receiving a second preset voltage and a plurality of test signal transmission interfaces which are correspondingly connected with a control module test interface and a to-be-tested drive chip respectively;
the multi-channel bidirectional level conversion chip is specifically used for: and converting the voltage amplitudes of the first preset voltage and the second preset voltage mutually according to the first preset voltage and the second preset voltage so as to realize the transmission of the test signal of the control module and the feedback of the test result of the to-be-tested drive chip.
Optionally, the driver chip test circuit further includes: the upper computer is connected with the control module;
the upper computer is used for: setting voltage parameters, setting test parameters, storing the read-write times of the drive chip to be tested, and reading test results.
The application provides a driver chip test system, including the driver chip test circuit that this application provided.
According to the drive chip test circuit and the drive chip test system, the control module generates the control signal, and the program-controlled voltage module generates the preset voltage according to the control signal, so that the signal conversion module can convert the voltage amplitude of the test signal according to the preset voltage. Therefore, the driver chip test circuit provided by the embodiment of the application only needs to input the preset voltage parameter corresponding to the preset voltage, so that the corresponding preset voltage can be generated through the control module and the program control voltage module, the voltage input by the voltage input interface of the signal conversion module does not need to be manually modified, the test operation and the test flow can be simplified, the test time is saved, and the test efficiency is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a driver chip test circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another driver chip test circuit according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another driver chip test circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic flowchart illustrating a process of testing a driver chip by using a driver chip test circuit according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a driver chip testing system according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings of the embodiments of the present application. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all embodiments. And the embodiments and features of the embodiments in the present application may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the application without any inventive step, are within the scope of protection of the application.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. As used in this application, the terms "first," "second," and the like do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present disclosure. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.
An embodiment of the present application provides a driver chip test circuit, as shown in fig. 1, the driver chip test circuit 12 includes: the system comprises a control module 1, a program control voltage module 2 and a signal conversion module 3;
the control module 1 is connected with the program control voltage module 2 and the signal conversion module 3 through a control interface 4 and a test interface 5 respectively and is used for generating a control signal dac and a test signal text;
the program control voltage module 2 is connected with a voltage input interface 8 of the signal conversion module 3 and is used for generating preset voltages VCC with different amplitudes according to the control signal dac;
the signal conversion module 3 is in communication connection with the driver chip 13 to be tested, and is configured to convert a voltage amplitude of the test signal text according to a preset voltage VCC and output the converted voltage amplitude to the driver chip 13 to be tested, so as to detect the driver chip 13 to be tested.
According to the drive chip test circuit provided by the embodiment of the application, the control module generates the control signal, and the program-controlled voltage module generates the preset voltage according to the control signal, so that the signal conversion module can convert the voltage amplitude of the test signal according to the preset voltage. Therefore, the driver chip test circuit provided by the embodiment of the application only needs to input the preset voltage parameter corresponding to the preset voltage, so that the corresponding preset voltage can be generated through the control module and the program control voltage module, the voltage input by the voltage input interface of the signal conversion module does not need to be manually modified, the test operation and the test flow can be simplified, the test time is saved, and the test efficiency is improved.
In some embodiments, as shown in fig. 1, the control module 1 comprises: a plurality of control interfaces 4, and a plurality of test interfaces 5;
the program-controlled voltage module 2 comprises: a plurality of control signal input interfaces 6 electrically connected in one-to-one correspondence with the plurality of control interfaces 4, and a plurality of voltage signal output interfaces 7 electrically connected in one-to-one correspondence with the control signal input interfaces 6;
the signal conversion module 3 includes: a plurality of voltage input interfaces 8 which are electrically connected with the voltage signal output interfaces 7 in a one-to-one correspondence manner, and a test signal transmission interface 9; the test signal transmission interface 9 includes a plurality of first test signal transmission interfaces 10 and a plurality of second test signal transmission interfaces 11; the plurality of first test signal transmission interfaces 10 are electrically connected with the plurality of test interfaces 5 in a one-to-one correspondence manner; the plurality of second test signal transmission interfaces 11 are electrically connected to the driving chip to be tested, and are configured to: when the driver chip 13 to be tested is tested by the driver chip test circuit 12, the driver chip is electrically connected with the driver chip 13 to be tested;
the control module 1 is used for: generating a plurality of control signals dac according to a plurality of preset voltage parameters IN the test parameters IN, and respectively outputting the control signals dac to each electrically connected control signal input interface 6 through the control interface 4; generating a plurality of test signals text according to the test parameters IN and outputting the test signals text to each electrically connected first test signal transmission interface 10 through the test interface 5;
the program-controlled voltage module 2 is used for generating preset voltages with different amplitudes according to the control signal, and specifically comprises: generating a plurality of preset voltages VCC according to the plurality of control signals dac and respectively outputting the preset voltages VCC to the electrically connected voltage input interface 8; the voltage values of the preset voltages VCC output by the different voltage signal output interfaces 7 are different, and the preset voltages VCC correspond to the preset voltage parameters.
It should be noted that, when the driver chip test circuit provided in the embodiment of the present application is used to test an element to be tested, a test signal generated by the control module is transmitted to the first test signal transmission interface, and after amplitude conversion is performed on the test signal input by the first test signal transmission interface through the signal conversion module, the test signal is transmitted to the driver chip to be tested through the second test signal transmission interface. And the driving chip to be tested reads and writes according to the input test signal and feeds back the test signal to the second test signal transmission interface. The signal conversion module performs amplitude conversion on the feedback test signal input by the second test signal transmission interface and then transmits the test signal to the control module through the first test signal transmission interface, so that the component to be detected is tested once.
According to the drive chip test circuit provided by the embodiment of the application, the control module generates the corresponding control signal according to the preset voltage parameter, and the program-controlled voltage module generates the preset voltage corresponding to the preset voltage parameter according to the control signal, so that the signal conversion module can convert the voltage amplitude of the test signal according to the preset voltage corresponding to the preset voltage parameter. Therefore, the driver chip test circuit provided by the embodiment of the application only needs to input the required preset voltage parameter, so that the preset voltage corresponding to the preset voltage parameter can be generated through the control module and the program control voltage module, the reference voltage input by the voltage input interface of the signal conversion module does not need to be manually modified, the test operation can be simplified, the test flow is simplified, the test time is saved, and the test efficiency is improved.
It should be noted that fig. 1 illustrates an example of the driver chip test circuit being electrically connected to the driver chip to be tested.
In specific implementation, the driving chip is tested, for example, the stability of the driving chip under different driving voltages can be detected, and the driving chip can be repeatedly read and written under different driving voltages. The repeated read-write times under each driving voltage can be tested according to actual needs. The drive chip test circuit provided by the embodiment of the application is suitable for different drive chips and has strong universality. The driving chip may be, for example, various driving chips in a display product, such as a Timing Controller (TCON), a flash memory chip (flash), and an Electrically Erasable Programmable Read Only Memory (EEPROM). The display product is provided with a test interface which is used for testing and electrically connected with the driving chip, and when the driving chip in the display product needs to be tested, the driving chip test circuit is electrically connected with the test interface.
In some embodiments, as shown in fig. 2, the control module 1 includes a single chip microcomputer, and the single chip microcomputer may specifically select an STM32F103RCT6 type single chip microcomputer.
In some embodiments, as shown in fig. 2, the single chip has a plurality of test interfaces 5 and a control interface 4 with a digital-to-analog conversion module DAC built therein;
the control interface 4 includes: a first control interface 16 and a second control interface 17;
the first control interface 16 is for: generating a first control signal dac 1;
the second control interface 17 is used for: generating a second control signal dac 2.
The digital-to-analog conversion module DAC comprises: a first digital-to-analog conversion module DAC1, a second digital-to-analog conversion module DAC 2;
the plurality of preset voltage parameters include: a first preset voltage parameter and a second preset voltage parameter;
the first control interface 16 comprises a first digital-to-analog conversion module DAC1, specifically configured to: generating a first control signal dac1 according to a first predetermined voltage parameter;
the second control interface 17 comprises a second digital-to-analog conversion module DAC2, specifically configured to: generating a second control signal dac2 according to a second predetermined voltage parameter;
it should be noted that the first control signal generated by the first digital-to-analog conversion module and the second control signal generated by the second digital-to-analog conversion module are digital-to-analog conversion signals.
In some embodiments, the single chip further comprises a test signal generation module for generating a test signal according to the test parameter.
In specific implementation, the test signal includes, for example: chip select signal, serial clock signal, serial data signal.
The test interface includes, for example: a Chip Select signal (CS) transmission interface, a Serial clock Signal (SCL) transmission interface, and a Serial Data Signal (SDA) transmission interface.
Correspondingly, the first test signal transmission interface, the second test signal transmission interface and the test interface of the signal to be tested also include: CS transmission interface, SCL transmission interface, SDA transmission interface.
In some embodiments, as shown in fig. 2, the programmable voltage module 2 includes: a first voltage module 201 and a second voltage module 202;
the first voltage module 201 is connected to the first control interface 16, and is configured to generate a first preset voltage VCCB according to a first control signal dac 1;
the second voltage module 202 is connected to the second control interface 17 and is configured to generate a second predetermined voltage VCCA according to a second control signal dac 2.
In some embodiments, as shown in fig. 2, the first voltage module 201 includes: a first multiplier 2011, and a first voltage follower 2012;
the second voltage module 202 includes: a second multiplier 2021, and a second voltage follower 2022;
an input terminal of the first multiplier 2011 is configured to receive the first control signal dac1, an output terminal of the first multiplier 2011 is configured to generate the first preset voltage VCCB according to the first control signal dac1, and an output terminal of the first multiplier 2011 is electrically connected to an input terminal of the first voltage follower 2011; an output terminal of the first voltage follower 2011 is configured to output a first preset voltage VCCB;
an input terminal of the second multiplier 2021 is configured to receive the second control signal dac2, an output terminal of the second multiplier 2021 is configured to generate the second preset voltage VCCA according to the second control signal dac2, and an output terminal of the second multiplier 2021 is electrically connected to an input terminal of the second voltage follower 2022; the output end of the second voltage follower 2022 is used for outputting a second preset voltage VCCA; the first preset voltage VCCB and the second preset voltage VCCA are not equal.
Namely, the input ends of the first multiplier and the second multiplier are used as control signal input interfaces, and the output ends of the first voltage follower and the second voltage follower are used as voltage signal output interfaces.
In the test circuit for the driver chip provided by the embodiment of the application, the multiplier in the program-controlled voltage module is used for generating the preset voltage corresponding to the digital-to-analog conversion signal according to the digital-to-analog conversion signal, and the program-controlled voltage module can specifically select the SGM8210 dual operational amplifier chip with the function of a multiplier. After the first preset voltage and the second preset voltage respectively pass through each voltage follower in the program control voltage module, the voltage of the preset voltage is unchanged, and the current is amplified, so that the load carrying capacity of the circuit can be enhanced, and the driving capacity of the output voltage is enhanced.
In some embodiments, as shown in fig. 2, the first multiplier 2011 includes: a first operational amplifier OP1, a first resistor R1, a second resistor R2, and a third resistor R3;
the second multiplier 2021 includes: a second operational amplifier OP2, a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6;
a first input terminal of the first operational amplifier OP1 is electrically connected to one end of the third resistor R3, and an inverting input terminal of the first operational amplifier OP1 is electrically connected to one end of the first resistor R1 and one end of the second resistor R2; the output end of the first operational amplifier OP1 is electrically connected to the input end of the first voltage follower 2012 and the other end of the second resistor R2;
the other end of the first resistor R1 is grounded GND;
the other end of the third resistor R3 is used for receiving a first control signal dac 1;
a non-inverting input terminal of the second operational amplifier OP2 is electrically connected to one end of the sixth resistor R6, and an inverting input terminal of the second operational amplifier OP is electrically connected to one end of the fourth resistor R4 and one end of the fifth resistor R5; the output end of the second operational amplifier OP is electrically connected to the input end of the second voltage follower 2022 and the other end of the fifth resistor R5;
the other end of the fourth resistor R4 is grounded GND;
the other end of the sixth resistor R6 is used for receiving the second control signal dac 2.
Namely, the third resistor is electrically connected with the first digital-to-analog conversion module, and the sixth resistor is electrically connected with the second digital-to-analog conversion module.
In some embodiments, as shown in fig. 2, the first voltage follower 2012 includes: a third operational amplifier OP 3;
the non-inverting input terminal of the third operational amplifier OP3 is electrically connected to the output terminal of the first multiplier 2011, and the inverting input terminal of the third operational amplifier OP3 is electrically connected to the output terminal of the third operational amplifier OP 3; the output end of the third operational amplifier OP3 is used for outputting a first preset voltage VCCB;
the second voltage follower 2022 includes: a fourth operational amplifier OP 4;
the non-inverting input terminal of the fourth operational amplifier OP4 is electrically connected to the output terminal of the second multiplier 2021, and the inverting input terminal of the fourth operational amplifier OP4 is electrically connected to the output terminal of the fourth operational amplifier OP 4; the output terminal of the fourth operational amplifier OP4 is used for outputting a second preset voltage VCCA.
In the programmable voltage module 2 shown in fig. 2, taking the first control signal dac1 as an example, the voltage of the first control signal dac1 is set as Udac1Then, the first multiplication is performedVoltage output after the law device OP1
Due to UOUT1The voltage is consistent before and after passing through the first voltage follower, namely UOUT1As VCCB, i.e.
Wherein r is1Is the resistance value of the first resistor, r2Is the resistance of the second resistor. In the same way, the method for preparing the composite material,
wherein, Udac2Is the voltage of the second control signal dac2, r4Is the resistance value of the fourth resistor, r5Is the resistance of the fifth resistor. That is, the single chip microcomputer can program control the amplitude of the required preset voltage only by controlling the amplitude of the direct-current voltage of the first control signal dac1 and the second control signal dac 2.
It should be noted that, in specific implementation, the voltage amplitude of the first preset voltage corresponds to the voltage amplitude of the driving voltage required for testing the driving chip, and the voltage amplitude of the second preset voltage corresponds to the voltage amplitude of the communication signal of the single chip microcomputer.
In some embodiments, as shown in fig. 2, the signal conversion module 3 includes: the multi-channel bidirectional level conversion chip can specifically select a TXB0304 type conversion level;
the multichannel bidirectional level conversion chip includes: the test device comprises a first voltage input interface 801 for receiving a first preset voltage VCCB, a second voltage input interface 802 for receiving a second preset voltage VCCA, and a plurality of test signal transmission interfaces 9 which are correspondingly connected with a test interface 5 of the control module 1 and a drive chip 13 to be tested respectively;
the multi-channel bidirectional level conversion chip is specifically used for: and performing mutual conversion according to the voltage amplitudes of the first preset voltage VCCB and the second preset voltage VCCA to realize transmission of the test signal tex st of the control module 1 and feedback of the test result of the to-be-tested drive chip 13.
In some embodiments, the test signal transmission interface 9 comprises a plurality of first test signal transmission interfaces 10 and a plurality of second test signal transmission interfaces 11; the plurality of first test signal transmission interfaces 10 are electrically connected with the plurality of test interfaces 5 in a one-to-one correspondence manner; the plurality of second test signal transmission interfaces 11 are electrically connected with the driving chip to be tested;
the transmission of the test signal tex st of the interconversion control module 1 is performed according to the voltage amplitudes of the first preset voltage VCCB and the second preset voltage VCCA, and specifically includes: converting the voltage amplitude of the test signal text input by the first test signal transmission interface 10 from the voltage amplitude of the second preset voltage VCCA to the voltage amplitude of the first preset voltage VCCB according to the first preset voltage VCCB and the second preset voltage VCCA, and outputting the test signal text after the voltage amplitude conversion through the second test signal transmission interface 11; or; according to the first preset voltage VCCB and the second preset voltage VCCA, the voltage amplitude of the test signal text input to the second test signal transmission interface text is converted from the voltage amplitude of the first preset voltage VCCB to the voltage amplitude of the second preset voltage VCCA, and the test signal text after the voltage amplitude conversion is output through the first test signal transmission interface 10.
It should be noted that, when the driver chip test circuit provided in this embodiment of the present application is used to test an element to be tested, a test signal generated by the single chip microcomputer is transmitted to the first test signal transmission interface, a voltage amplitude of the test signal input to the first test signal transmission interface through the multi-channel bidirectional level conversion chip is converted from a voltage amplitude of a second preset voltage to a voltage amplitude of a first preset voltage, and the test signal after the voltage amplitude conversion is output to the driver chip to be tested through the second test signal transmission interface. And the driving chip to be tested reads and writes according to the input test signal and feeds back the test signal to the second test signal transmission interface. The voltage amplitude of the feedback test signal input by the multi-channel bidirectional level conversion chip to the second test signal transmission interface is converted from the voltage amplitude of the first preset voltage to the voltage amplitude of the second preset voltage, and then the voltage amplitude is transmitted to the single chip microcomputer through the first test signal transmission interface, so that the component to be detected is tested once.
In some embodiments, the test parameters further include: pulse modulation signal parameters;
the singlechip is also used for generating a pulse modulation signal PWM according to the pulse modulation signal parameter; the singlechip also comprises a first pulse modulation signal transmission interface PWM1 for transmitting a pulse modulation signal PWM;
the signal conversion module 3 further includes: a second pwm signal transmission interface pwm2 electrically connected to the first pwm signal transmission interface pwm1, and a third pwm signal transmission interface pwm 3; the third pwm signal transmission interface pwm3 is configured to: when the driver chip 13 to be tested is tested by the driver chip test circuit 12, the driver chip is electrically connected with the driver chip 13 to be tested;
the signal conversion module 3 is further configured to: and converting and outputting the voltage amplitude of the input pulse modulation signal PWM according to a plurality of preset voltages VCC.
It should be noted that the pulse modulation signal parameter includes, for example, a pulse modulation signal duty ratio or a frequency. In specific implementation, the test signal generation module of the single chip microcomputer can generate a test signal according to the pulse modulation signal parameter. When the test signal needs to be transmitted according to the pulse of the pulse modulation signal, the single chip microcomputer outputs the generated pulse modulation signal to the multi-channel bidirectional level conversion chip through the first pulse modulation signal transmission interface, and the multi-channel bidirectional level conversion chip outputs the pulse modulation signal to the driving chip after performing amplitude conversion on the pulse modulation signal. And after the drive chip finishes one read-write test, feeding back signals to the multi-channel bidirectional level conversion chip, wherein the feedback signals comprise feedback signals of the test signals and feedback signals of the pulse modulation signals. And after receiving the fed back pulse modulation signal, the multichannel bidirectional level conversion chip performs amplitude conversion and outputs the pulse modulation signal to the single chip microcomputer.
In some embodiments, the single chip further comprises: a monitoring module;
the monitoring module is used for: and storing the read-write times of the drive chip to be tested, and judging whether the read-write of the drive chip to be tested is successful.
According to the drive chip test circuit provided by the embodiment of the application, the single chip microcomputer further comprises the monitoring module, so that the read-write times can be monitored and the read-write errors can be monitored in the process of testing the drive chip.
In some embodiments, the test parameters further include a preset number of reads and writes. The monitoring module is further configured to: when the read-write times are smaller than the preset read-write times, judging that the current preset voltage test is not finished on the driving chip, and keeping the current transmission signal to continuously perform the read-write test on the driving chip; and when the read-write times are equal to the preset read-write times, judging that the current preset voltage test is finished on the driving chip.
In some embodiments, as shown in fig. 3, the driver chip test circuit further includes: an upper computer; the upper computer is connected with the control module 1;
the upper computer is used for: setting voltage parameters, setting test parameters, storing the read-write times of the drive chip to be tested, and reading test results.
The test parameters are input to the control module through the upper computer, the read-write times of the drive chip are stored through the upper computer, and the test result is read.
The drive chip test circuit provided by the embodiment of the application can provide corresponding input parameters for the control module by setting the voltage parameters and the test parameters through the upper computer, and does not need to additionally input relevant parameters through input modules such as an external keyboard and the like. And the upper computer stores the read-write times of the drive chip and reads the test result, and can also realize the read-write times monitoring and the read-write error monitoring in the process of testing the drive chip.
In some embodiments, the test parameters further include: and reading and writing the data type.
In some embodiments, the first preset voltage parameter includes a plurality of preset voltage parameters.
During specific implementation, the single chip microcomputer generates corresponding digital-to-analog conversion signals according to the multiple groups of preset voltage parameters, and automatic switching of the digital-to-analog conversion signals corresponding to the multiple groups of preset voltages is achieved. In a specific implementation, for example, the first preset voltage parameter includes n preset voltage parameters. The method comprises the steps that currently, the 1 st preset voltage parameter is required to be used as a driving voltage for testing a driving chip, a first digital-to-analog conversion module in a single chip microcomputer generates a first digital-to-analog conversion signal corresponding to the 1 st preset voltage parameter, a first preset voltage corresponding to the 1 st preset voltage parameter is generated through a program control voltage module, the driving chip is subjected to read-write testing, and when the testing frequency does not reach the preset testing frequency, the first digital-to-analog conversion module is kept generating the first digital-to-analog conversion signal corresponding to the 1 st preset voltage parameter. When the test frequency reaches the preset test frequency, the first digital-to-analog conversion module is controlled to generate a first digital-to-analog conversion signal corresponding to the 2 nd preset voltage parameter, a first preset voltage corresponding to the 2 nd preset voltage parameter is generated through the program control voltage module, and the read-write test is carried out on the drive chip. So on, it is not described herein.
Next, the first preset voltage parameter includes: the driving chip test circuit provided by the embodiment of the present application exemplifies a driving chip test, where the driving chip test circuit includes 1.8 volts (V), 2.5V, 3.3V, and 5.0V, the second preset voltage parameter is 3.3V, and the preset read-write frequency is 1 ten thousand. As shown in fig. 4, the test flow includes:
s101, inputting test parameters;
s102, reading an Identity (ID) of a drive chip to be tested;
s103, judging whether the ID of the driving chip is correct or not; if yes, executing step S104; otherwise, executing step S102;
judging whether the ID of the driving chip is correct or not so as to judge whether the connection between the driving chip test circuit and the driving chip is successful or not, if the ID of the driving chip is correct, indicating that the connection between the driving chip test circuit and the driving chip is successful, otherwise, indicating that the connection between the driving chip test circuit and the driving chip is failed;
s104, under the conditions that the 1 st read value of the first preset voltage parameter is 1.8V and the second preset voltage parameter is 3.3V, performing 1 ten thousand read-write tests on the driving chip, and recording the read-write success and error times by the single chip microcomputer;
s105, under the conditions that the 2 nd read value of the first preset voltage parameter is 2.5V and the second preset voltage parameter is 3.3V, 1 ten thousand read-write tests are carried out on the driving chip, and the single chip microcomputer records the read-write success and the error times;
s106, under the conditions that the 3 rd read value of the first preset voltage parameter is 3.3V and the second preset voltage parameter is 3.3V, 1 ten thousand read-write tests are carried out on the driving chip, and the single chip microcomputer records the read-write success and the error times;
s107, under the conditions that the 4 th read value of the first preset voltage parameter is 5.0V and the second preset voltage parameter is 3.3V, 1 ten thousand read-write tests are carried out on the driving chip, and the single chip microcomputer records the read-write success and the error times;
and S108, ending the test.
Based on the same inventive concept, the embodiment of the application also provides a driver chip test system which comprises the driver chip test circuit provided by the application.
In some embodiments, as shown in fig. 5, the driver chip test system further includes: a signal input module 14 and an information display module 15 electrically connected with the control module 1.
In specific implementation, the signal input module is used for inputting each test parameter. The input module may be, for example, a keyboard, and for example, the preset voltage parameter value, the number of times of reading and writing signals, the duty ratio/frequency of the pulse modulation signal, and the like are input through the keyboard. The information display module is used for displaying each test parameter, and the display module can be a display device or the like with a display function.
Of course, in some embodiments, the signal input module and the information display module may be integrated into the same system. For example, the control module may also be electrically connected to the computer host, and the test parameters may be input via the keyboard of the computer and displayed via the display screen of the computer.
In some embodiments, when the single chip further includes the monitoring module, the information display module is further configured to display the read-write times of the driver chip to be tested in the test process.
Or, in some embodiments, when the driver chip test circuit includes an upper computer, the voltage parameter and the test parameter may be set by the upper computer, and the upper computer displays the test parameters and the read-write times of the driver chip to be tested in the test process, so that the driver chip test system does not need to additionally provide a signal input module and an information display module.
To sum up, according to the driver chip test circuit and the driver chip test system provided by the embodiment of the application, the control module generates the control signal, and the program-controlled voltage module generates the preset voltage according to the control signal, so that the signal conversion module can convert the voltage amplitude of the test signal according to the preset voltage. Therefore, the driver chip test circuit provided by the embodiment of the application only needs to input the preset voltage parameter corresponding to the preset voltage, so that the corresponding preset voltage can be generated through the control module and the program control voltage module, the voltage input by the voltage input interface of the signal conversion module does not need to be manually modified, the test operation and the test flow can be simplified, the test time is saved, and the test efficiency is improved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A driver chip test circuit, comprising: the control module, the program control voltage module and the signal conversion module;
the control module is connected with the program control voltage module and the signal conversion module through a control interface and a test interface respectively and is used for generating a control signal and a test signal;
the program control voltage module is connected with a voltage input interface of the signal conversion module and used for generating preset voltages with different amplitudes according to the control signal;
the signal conversion module is in communication connection with the driving chip to be detected and is used for converting the voltage amplitude of the test signal according to the preset voltage and outputting the voltage amplitude to the driving chip to be detected so as to detect the driving chip to be detected.
2. The driver chip test circuit of claim 1, wherein the control module comprises a single chip microcomputer having a plurality of test interfaces and a control interface with a built-in digital-to-analog conversion module.
3. The driver chip test circuit of claim 2, wherein the control interface comprises: a first control interface and a second control interface;
the first control interface is to: generating a first control signal;
the second control interface is to: a second control signal is generated.
4. The driver chip test circuit of claim 3, wherein the program-controlled voltage module comprises: a first voltage module and a second voltage module;
the first voltage module is connected with the first control interface and used for generating a first preset voltage according to the first control signal;
the second voltage module is connected with the second control interface and used for generating a second preset voltage according to the second control signal.
5. The driver chip test circuit according to claim 4,
the first voltage module includes: a first multiplier, and a first voltage follower;
the second voltage module includes: a second multiplier, and a second voltage follower;
the input end of the first multiplier is used for receiving the first control signal, the first multiplier is used for generating a first preset voltage according to the first control signal, and the output end of the first multiplier is electrically connected with the input end of the first voltage follower; the output end of the first voltage follower is used for outputting the first preset voltage;
the input end of the second multiplier is used for receiving the second control signal, the second multiplier is used for generating a second preset voltage according to the second control signal, and the output end of the second multiplier is electrically connected with the input end of the second voltage follower; the output end of the second voltage follower is used for outputting the second preset voltage; the first preset voltage and the second preset voltage are not equal.
6. The driver chip test circuit of claim 5, wherein the first multiplier comprises: a first operational amplifier, a first resistor, a second resistor, and a third resistor;
the second multiplier includes: a second operational amplifier, a fourth resistor, a fifth resistor, and a sixth resistor;
a positive phase input end of the first operational amplifier is electrically connected with one end of the third resistor, and an inverted phase input end of the first operational amplifier is electrically connected with one end of the first resistor and one end of the second resistor; the output end of the first operational amplifier is electrically connected with the input end of the first voltage follower and the other end of the second resistor;
the other end of the first resistor is grounded;
the other end of the third resistor is used for receiving the first control signal
A positive phase input end of the second operational amplifier is electrically connected with one end of the sixth resistor, and an inverted phase input end of the second operational amplifier is electrically connected with one end of the fourth resistor and one end of the fifth resistor; the output end of the second operational amplifier is electrically connected with the input end of the second voltage follower and the other end of the fifth resistor;
the other end of the fourth resistor is grounded;
the other end of the sixth resistor is used for receiving the second control signal.
7. The driver chip test circuit of claim 5, wherein the first voltage follower comprises: a third operational amplifier;
the positive phase input end of the third operational amplifier is electrically connected with the output end of the first multiplier, and the negative phase input end of the third operational amplifier is electrically connected with the output end of the third operational amplifier; the output end of the third operational amplifier is used for outputting the first preset voltage;
the second voltage follower includes: a fourth operational amplifier;
the positive phase input end of the fourth operational amplifier is electrically connected with the output end of the second multiplier, and the negative phase input end of the fourth operational amplifier is electrically connected with the output end of the fourth operational amplifier; and the output end of the fourth operational amplifier is used for outputting the second preset voltage.
8. The driver chip test circuit according to any one of claims 5 to 7, wherein the signal conversion module comprises: a multi-channel bidirectional level conversion chip;
the multi-channel bidirectional level conversion chip comprises: the test circuit comprises a first voltage input interface for receiving the first preset voltage, a second voltage input interface for receiving the second preset voltage and a plurality of test signal transmission interfaces which are correspondingly connected with the control module test interface and the to-be-tested drive chip respectively;
the multi-channel bidirectional level conversion chip is specifically used for: and converting the voltage amplitudes of the first preset voltage and the second preset voltage mutually according to the first preset voltage and the second preset voltage so as to realize the transmission of the test signal of the control module and the feedback of the test result of the to-be-tested drive chip.
9. The driver chip test circuit according to claim 1, wherein the driver chip test circuit further comprises: the upper computer is connected with the control module;
the upper computer is used for: setting voltage parameters, setting test parameters, storing the read-write times of the to-be-tested drive chip, and reading a test result.
10. A driver chip test system comprising the driver chip test circuit according to any one of claims 1 to 9.
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| CN202122391202.1U CN216287519U (en) | 2021-09-30 | 2021-09-30 | Drive chip test circuit and system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114546016A (en) * | 2022-04-26 | 2022-05-27 | 武汉精立电子技术有限公司 | Test equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114546016A (en) * | 2022-04-26 | 2022-05-27 | 武汉精立电子技术有限公司 | Test equipment |
| CN114546016B (en) * | 2022-04-26 | 2022-08-05 | 武汉精立电子技术有限公司 | Test equipment |
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