CN216250731U - 半导体功率器件 - Google Patents

半导体功率器件 Download PDF

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CN216250731U
CN216250731U CN202122841877.1U CN202122841877U CN216250731U CN 216250731 U CN216250731 U CN 216250731U CN 202122841877 U CN202122841877 U CN 202122841877U CN 216250731 U CN216250731 U CN 216250731U
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power device
device chip
super
junction mosfet
igbt
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龚轶
刘磊
刘伟
袁愿林
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Suzhou Dongwei Semiconductor Co ltd
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Suzhou Dongwei Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本实用新型属于半导体功率器件技术领域，具体公开了一种半导体功率器件，包括封装在同一个封装体内的超级结MOSFET功率器件芯片和IGBT功率器件芯片，其中：所述超级结MOSFET功率器件芯片的漏极与所述IGBT功率器件芯片的集电极均电性连接所述封装体的集电极引脚；所述超级结MOSFET功率器件芯片的源极和栅极、以及所述IGBT功率器件芯片的发射极均电性连接所述封装体的发射极引脚；所述IGBT功率器件芯片的栅极电性连接所述封装体的栅极引脚。本实用新型可以降低IGBT功率器件的反并联二极管的正向导通损耗。

Description

半导体功率器件
技术领域
本实用新型属于半导体功率器件技术领域，特别是涉及一种IGBT功率器件。
背景技术
IGBT功率器件因具有高输入阻抗、低控制功率、驱动电路简单、开关速度快、导通压降低、通态电流大、损耗小的优点，已渐渐成为电力电子技术的核心器件之一。然而，IGBT功率器件不像MOSFET功率器件那样拥有体二极管，在反向工作时，它只能等效于一个不能导通的开基极PNP晶体管，因此，这需要将IGBT功率器件和一个二极管反并联来续流，由于二极管的正向导通电压(Vf)较高，使得二极管的正向导通损耗较大。
实用新型内容
有鉴于此，本实用新型的目的是提供一种半导体功率器件，以解决现有技术中的IGBT功率器件的反并联二极管的正向导通损耗大的问题。
为达到本实用新型的上述目的，本实用新型提供了一种半导体功率器件，包括：
封装在同一个封装体内的超级结MOSFET功率器件芯片和IGBT功率器件芯片，其中：
所述超级结MOSFET功率器件芯片的漏极与所述IGBT功率器件芯片的集电极均电性连接所述封装体的集电极引脚；
所述超级结MOSFET功率器件芯片的源极和栅极、以及所述IGBT功率器件芯片的发射极均电性连接所述封装体的发射极引脚；
所述IGBT功率器件芯片的栅极电性连接所述封装体的栅极引脚。
可选的，所述超级结MOSFET功率器件芯片为平面栅结构的超级结功率晶体管。
可选的，所述超级结MOSFET功率器件芯片为沟槽栅结构的超级结功率晶体管。
本实用新型提供的一种半导体功率器件将超级结MOSFET功率器件芯片和IGBT功率器件芯片封装在同一个封装体内，将超级结MOSFET功率器件芯片的栅极电性连接到封装体的发射极电极上，用超级结MOSFET功率器件芯片作为IGBT功率器件芯片的反并联二极管，降低IGBT功率器件的反并联二极管的正向导通损耗。
附图说明
为了更加清楚地说明本实用新型示例性实施例的技术方案，下面对描述实施例中所需要用到的附图做一简单介绍。
图1是本实用新型提供的一种半导体功率器件中的超级结MOSFET功率器件芯片和IGBT功率器件芯片封装在同一个封装体内的一个实施例的内部结构示意图。
具体实施方式
为使本实用新型的目的、技术方案和优点更加清楚，以下将结合本实用新型实施例中的附图，通过具体方式，完整地描述本实用新型的技术方案。
图1是本实用新型提供的一种半导体功率器件中的超级结MOSFET功率器件芯片和IGBT功率器件芯片封装在同一个封装体内的一个实施例的内部结构示意图，图1中仅示例性的示出了超级结MOSFET功率器件芯片60和IGBT功率器件芯片50封装在同一个封装体内的打线结构示意图，如图1所示，本实用新型提供的一种半导体功率器件中：超级结MOSFET功率器件芯片60的源极(源极pad层)61和栅极(栅极pad层)63、以及IGBT功率器件芯片50的发射极(发射极pad层)51分别通过金属导线70、金属导线71、金属导线72电性连接封装体的发射极引脚81；超级结MOSFET功率器件芯片60的漏极与IGBT功率器件芯片50的集电极均电性连接封装体的集电极引脚82(超级结MOSFET功率器件芯片60的漏极金属层与IGBT功率器件芯片50的集电极金属层均是位于其芯片的背面，从而均与封装体中的金属框架直接接触连接至集电极引脚82，而不需要打线)；IGBT功率器件芯片50的栅极(栅极pad层)53通过金属导线73电性连接封装体的栅极引脚83。
本实用新型将超级结MOSFET功率器件芯片60和IGBT功率器件芯片50封装在同一个封装体内，将超级结MOSFET功率器件芯片60的栅极63电性连接到封装体的发射极电极81上，用超级结MOSFET功率器件芯片60作为IGBT功率器件芯片50的反并联二极管，超级结MOSFET功率器件芯片60作为二极管时的正向导通电压较低，可以降低IGBT功率器件的反并联二极管的正向导通损耗。
需要说明的是，图1中的超级结MOSFET功率器件芯片60和IGBT功率器件芯片50仅是示例性的结构，根据不同的设计要求，超级结MOSFET功率器件芯片60和IGBT功率器件芯50均可以有不同的芯片尺寸和耐压，也可以均有不同的pad层形状或结构。此外，超级结MOSFET功率器件芯片60和IGBT功率器件芯片50也都可以内置栅极电阻。
本实用新型的一种半导体功率器件中的超级结MOSFET功率器件芯片可以为平面栅结构的超级结功率晶体管，也可以为沟槽栅结构的超级结功率晶体管。本实用新型对超级结MOSFET功率器件芯片和IGBT功率器件芯片的类型及结构不作限制。
以上具体实施方式及实施例是对本实用新型技术思想的具体支持，不能以此限定本实用新型的保护范围，凡是按照本实用新型提出的技术思想，在本技术方案基础上所做的任何等同变化或等效的改动，均仍属于本实用新型技术方案保护的范围。

Claims (3)

1.半导体功率器件，其特征在于，包括：
封装在同一个封装体内的超级结MOSFET功率器件芯片和IGBT功率器件芯片，其中：
所述超级结MOSFET功率器件芯片的漏极与所述IGBT功率器件芯片的集电极均电性连接所述封装体的集电极引脚；
所述超级结MOSFET功率器件芯片的源极和栅极、以及所述IGBT功率器件芯片的发射极均电性连接所述封装体的发射极引脚；
所述IGBT功率器件芯片的栅极电性连接所述封装体的栅极引脚。
2.如权利要求1所述的半导体功率器件，其特征在于，所述超级结MOSFET功率器件芯片为平面栅结构的超级结功率晶体管。
3.如权利要求1所述的半导体功率器件，其特征在于，所述超级结MOSFET功率器件芯片为沟槽栅结构的超级结功率晶体管。
CN202122841877.1U 2021-11-19 2021-11-19 半导体功率器件 Active CN216250731U (zh)

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