CN216216823U - Power preceding stage power supply modulation circuit - Google Patents

Power preceding stage power supply modulation circuit Download PDF

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Publication number
CN216216823U
CN216216823U CN202122512138.8U CN202122512138U CN216216823U CN 216216823 U CN216216823 U CN 216216823U CN 202122512138 U CN202122512138 U CN 202122512138U CN 216216823 U CN216216823 U CN 216216823U
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triode
resistor
power
mos tube
power supply
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CN202122512138.8U
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Chinese (zh)
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蒋庆祥
汪超
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Chengdu Kejiaxin Microelectronic Co ltd
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Chengdu Kejiaxin Microelectronic Co ltd
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Abstract

The utility model discloses a power preceding-stage power supply modulation circuit, which comprises a first control circuit and a second control circuit; the first control circuit comprises a MOS transistor Q1, a triode Q2 and a triode Q3; the second control circuit comprises a MOS transistor Q4 and a triode Q5. The device adopts the same control signal to realize the opposite working states of the two MOS tubes. Therefore, only one control signal needs to be transmitted, the MOS transistor Q4 is turned on in synchronization with the turn-off of the MOS transistor Q1, and the MOS transistor Q4 is turned off in synchronization with the turn-on of the MOS transistor Q1, so that the power switch at the signal transmitting and receiving positions is synchronously controlled, and the possibility of interference is greatly reduced.

Description

Power preceding stage power supply modulation circuit
Technical Field
The utility model relates to a power supply control circuit, in particular to a power preceding stage power supply modulation circuit.
Background
MOS pipe is often used in switch for power, be used for controlling the power break-make, among the current signal reception transmitting circuit, when carrying out signal reception, can turn off the power supply among the transmitting circuit, when carrying out signal transmission, can turn off the power among the receiving circuit, cross influence has been avoided, but among the current circuit, generally all be that receiving circuit and transmitting circuit respectively have own switch, and need send the order respectively, carry out the switch respectively, but carry out synchronous control more difficultly through two signals, so often there is the delay, lead to the time quantum that signal transmission and signal reception opened simultaneously often appearing, can produce the interference in this time quantum.
SUMMERY OF THE UTILITY MODEL
It is an object of the present invention to address at least the above problems.
The utility model aims to provide a power preceding stage power supply modulation circuit, which solves the problem that the signal interference occurs when the receiving and the transmitting are carried out in the same time period due to the fact that a power supply switch is difficult to be synchronously controlled in the existing signal receiving and transmitting circuit.
To achieve these objects and other advantages in accordance with the purpose of the utility model, there is provided a power preceding stage power supply modulation circuit including a first control circuit and a second control circuit;
the first control circuit comprises an MOS tube Q1, a triode Q2 and a triode Q3, wherein the source of the MOS tube Q1 is connected to a power input end Vin1, the drain is connected to a power output end Vout1, the gate is connected to the collector of the triode Q2 through a resistor R2, the gate of the MOS tube Q1 is also connected to the power input end Vin1 through a resistor R1, the emitter of the triode Q2 is grounded, one path of the base of the triode Q2 is connected to the collector of the triode Q3, one path is connected to the power input end Vin1 through a resistor R3, the other path is grounded through a resistor R4, the emitter of the triode Q3 is grounded, one path of the base is connected to a control signal input end 2 through a resistor R5, and the other path is grounded through a resistor R6;
the second control circuit comprises a MOS tube Q4 and a triode Q5, wherein the source of the MOS tube Q4 is connected to a power input end Vin1, the drain of the MOS tube Q4 is connected to a power output end Vout2, the grid of the MOS tube Q4 is connected to the collector of the triode Q5 through a resistor R9, the grid of the MOS tube Q4 is also connected to a power input end Vin1 through a resistor R8, the emitter of the triode Q5 is grounded, one path of the base of the MOS tube Q5 is connected to a control signal input end Vin2 through a resistor R10, and the other path of the base of the MOS tube Q4 is grounded through a resistor R11.
In one possible design, the emitter of transistor Q2 is coupled to ground via diode D1.
In one possible design, a current limiting resistor R7 is connected in series with the base of the transistor Q2.
In one possible design, a ground capacitor C1 and a ground capacitor C2 are connected to the power input terminal Vin 1.
In one possible design, the power output terminal Vout is connected to a ground capacitor C3.
In one possible design, the emitter of transistor Q5 is coupled to ground via diode D2.
In one possible design, a current limiting resistor R12 is connected in series with the base of the transistor Q5.
In one possible design, the control signal input terminal Vin2 is connected to a ground capacitor C4.
The utility model at least comprises the following beneficial effects: the device adopts the same control signal to realize the opposite working states of the two MOS tubes. Therefore, only one control signal needs to be transmitted, the MOS transistor Q4 is turned on in synchronization with the turn-off of the MOS transistor Q1, and the MOS transistor Q4 is turned off in synchronization with the turn-on of the MOS transistor Q1, so that the power switch at the signal transmitting and receiving positions is synchronously controlled, and the possibility of interference is greatly reduced.
Additional advantages, objects, and features of the utility model will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the utility model.
Drawings
Fig. 1 is a schematic circuit diagram of the present device.
Detailed Description
The utility model is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely illustrative of example embodiments of the utility model. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It is to be noted that the experimental methods described in the following embodiments are all conventional methods unless otherwise specified, and the reagents and materials, if not otherwise specified, are commercially available; in the description of the present invention, the terms "lateral", "longitudinal", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention.
As shown in fig. 1, a power front-stage power supply modulation circuit includes a first control circuit and a second control circuit;
the first control circuit comprises an MOS tube Q1, a triode Q2 and a triode Q3, wherein the source of the MOS tube Q1 is connected to a power input end Vin1, the drain is connected to a power output end Vout1, the gate is connected to the collector of the triode Q2 through a resistor R2, the gate of the MOS tube Q1 is also connected to the power input end Vin1 through a resistor R1, the emitter of the triode Q2 is grounded, one path of the base of the triode Q2 is connected to the collector of the triode Q3, one path is connected to the power input end Vin1 through a resistor R3, the other path is grounded through a resistor R4, the emitter of the triode Q3 is grounded, one path of the base is connected to a control signal input end 2 through a resistor R5, and the other path is grounded through a resistor R6;
the second control circuit comprises a MOS tube Q4 and a triode Q5, wherein the source of the MOS tube Q4 is connected to a power input end Vin1, the drain of the MOS tube Q4 is connected to a power output end Vout2, the grid of the MOS tube Q4 is connected to the collector of the triode Q5 through a resistor R9, the grid of the MOS tube Q4 is also connected to a power input end Vin1 through a resistor R8, the emitter of the triode Q5 is grounded, one path of the base of the MOS tube Q5 is connected to a control signal input end Vin2 through a resistor R10, and the other path of the base of the MOS tube Q4 is grounded through a resistor R11.
Referring to fig. 1, in the device, two control circuits are designed, corresponding to the power supplies of the transmitting circuit and the receiving circuit respectively, Vin1 is a 5V power supply, Vout1 and Vout2 are outputs, and 0V or 5V is output by the MOS transistor control.
Vin2 is a control signal and is 5V or 27V, when Vin2 is 5V, in the first control circuit, Vin2 obtained by the base stage of the transistor Q3 divides voltage on the resistor R6, and the resistors R5 and R6 form a voltage dividing circuit, but the resistor R6 is far smaller than the resistor R5, so that the voltage obtained by the base stage of the transistor Q3 is small (about 0.3V), and the transistor Q3 is cut off; the triode Q2 obtains the partial voltage of Vin1 on a resistor R4 (R3 and R4 form a partial voltage circuit), the voltage on the base level of the triode Q2 is about 1.7V, the triode Q2 is conducted, the grid electrode of the MOS tube Q1 obtains the partial voltage of Vin1 on R2, thus, the voltage difference exists between the grid electrode and the source level S, the MOS tube Q1 is conducted, and the voltage of 5V is obtained at the position of Vout 1; in the second control circuit, the base voltage of the triode Q5 is about 0.3V and is also cut off, no voltage difference exists between the grid and the source of the MOS transistor Q4, the MOS transistor cannot be conducted, and the Vout2 outputs 0V voltage.
When Vin2 is 27V, in the first control circuit, the base voltage of the transistor Q3 is about 1.7V, the transistor Q3 is turned on, the base of the transistor Q2 obtains low level, the transistor Q1 is turned off, and the voltage Vout1 obtains 0V; in the second control circuit, the voltage at the base stage of the triode Q5 is about 1.7V, the MOS transistor Q4 is turned on, and Vout2 outputs 5V.
As shown in fig. 1, it can be seen that when Vin2 inputs a 5V level, the first control circuit is turned on and the second control circuit is turned off; when Vin2 inputs 27V level, the first control circuit is turned off and the second control circuit is turned on. The two control circuits are in opposite working states. When the power supply circuit is used for supplying power in a signal circuit, for example, the first control circuit is used for a power supply switch of the signal receiving circuit, the second control circuit is used for a power supply switch of the signal transmitting circuit, when an input control signal Vin2 is 5V, the signal receiving circuit is turned on, the signal transmitting circuit is turned off, and when an input control signal Vin2 is 27V, the signal transmitting circuit is turned on, and the signal receiving circuit is turned off. Synchronous and opposite switching of the receiving and transmitting circuits can be achieved.
As shown in fig. 1, the emitter of the transistor Q2 is coupled to ground via a diode D1. The emitter of the transistor Q5 is coupled to ground through a diode D2. The diode D1 and the diode D2 have the same function, mainly increase the base level voltage of the triode, and the cut-off effect of the triode is better.
As shown in fig. 1, a current limiting resistor R7 is connected in series to the base of the transistor Q2. The base stage of the triode Q5 is connected in series with a current limiting resistor R12. Current limiting resistor R7 and current limiting resistor R12 reduce the electric current on the triode, avoid the electric current too big, cause the device to damage.
As shown in fig. 1, a ground capacitor C1 and a ground capacitor C2 are connected to the power input terminal Vin 1. The power output terminal Vout is connected to a ground capacitor C3. The control signal input terminal Vin2 is connected to a ground capacitor C4. The grounded capacitor functions as a filter.
While embodiments of the utility model have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the utility model pertains, and further modifications may readily be made by those skilled in the art, it being understood that the utility model is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.

Claims (8)

1. A power preceding stage power supply modulation circuit is characterized by comprising a first control circuit and a second control circuit;
the first control circuit comprises an MOS tube Q1, a triode Q2 and a triode Q3, wherein the source of the MOS tube Q1 is connected to a power input end Vin1, the drain is connected to a power output end Vout1, the gate is connected to the collector of the triode Q2 through a resistor R2, the gate of the MOS tube Q1 is also connected to the power input end Vin1 through a resistor R1, the emitter of the triode Q2 is grounded, one path of the base of the triode Q2 is connected to the collector of the triode Q3, one path is connected to the power input end Vin1 through a resistor R3, the other path is grounded through a resistor R4, the emitter of the triode Q3 is grounded, one path of the base is connected to a control signal input end 2 through a resistor R5, and the other path is grounded through a resistor R6;
the second control circuit comprises a MOS tube Q4 and a triode Q5, wherein the source of the MOS tube Q4 is connected to a power input end Vin1, the drain of the MOS tube Q4 is connected to a power output end Vout2, the grid of the MOS tube Q4 is connected to the collector of the triode Q5 through a resistor R9, the grid of the MOS tube Q4 is also connected to a power input end Vin1 through a resistor R8, the emitter of the triode Q5 is grounded, one path of the base of the MOS tube Q5 is connected to a control signal input end Vin2 through a resistor R10, and the other path of the base of the MOS tube Q4 is grounded through a resistor R11.
2. The power pre-stage power supply modulation circuit as claimed in claim 1, wherein the emitter of said transistor Q2 is connected to ground via a diode D1.
3. The power pre-stage power supply modulation circuit as claimed in claim 1, wherein a current limiting resistor R7 is connected in series with the base of said transistor Q2.
4. The power pre-stage power supply modulation circuit as claimed in claim 1, wherein the power input terminal Vin1 is connected with a grounded capacitor C1 and a grounded capacitor C2.
5. The power pre-stage power supply modulation circuit as claimed in claim 1, wherein a ground capacitor C3 is connected to said power output terminal Vout.
6. The power pre-stage power supply modulation circuit as claimed in claim 1, wherein the emitter of said transistor Q5 is connected to ground via a diode D2.
7. The power pre-stage power supply modulation circuit as claimed in claim 1, wherein a current limiting resistor R12 is connected in series with the base of said transistor Q5.
8. The power pre-stage power supply modulation circuit as claimed in claim 1, wherein the control signal input terminal Vin2 is connected with a ground capacitor C4.
CN202122512138.8U 2021-10-19 2021-10-19 Power preceding stage power supply modulation circuit Active CN216216823U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202122512138.8U CN216216823U (en) 2021-10-19 2021-10-19 Power preceding stage power supply modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202122512138.8U CN216216823U (en) 2021-10-19 2021-10-19 Power preceding stage power supply modulation circuit

Publications (1)

Publication Number Publication Date
CN216216823U true CN216216823U (en) 2022-04-05

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202122512138.8U Active CN216216823U (en) 2021-10-19 2021-10-19 Power preceding stage power supply modulation circuit

Country Status (1)

Country Link
CN (1) CN216216823U (en)

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