CN214756076U

CN214756076U - MOS pipe control circuit and device

Info

Publication number: CN214756076U
Application number: CN202023058341.4U
Authority: CN
Inventors: 陈楚泽; 陈颜新
Original assignee: Huizhou Topband Electronic Technology Co Ltd
Current assignee: Huizhou Topband Electronic Technology Co Ltd
Priority date: 2020-12-16
Filing date: 2020-12-16
Publication date: 2021-11-16
Anticipated expiration: 2030-12-16

Abstract

The utility model is suitable for an electronic circuit technical field provides a MOS pipe control circuit and device, and the circuit includes that level conversion module is connected with at least two control signal ends for respectively receiving the control signal of at least two control signal end inputs and converting into the level signal of presetting the magnitude of voltage; the gate logic module is connected with the output end of the level conversion module and used for receiving the level signal output by the level conversion module and carrying out logic and operation to generate a driving control signal; the output end of the driving module is connected with the control end of the target MOS tube. The level conversion module is used for converting control signals input by at least two control signal ends into level signals with uniform voltage values, outputting the level signals to the gate logic module to carry out logic and operation to generate driving control signals, and outputting the driving control signals to the driving module to control the on-off of the target MOS tube, so that the on-off of the MOS tube can be controlled in a plurality of ways in a combined manner, and the MOS tube can be flexibly controlled.

Description

MOS pipe control circuit and device

Technical Field

The utility model belongs to the technical field of the electronic circuit, especially, relate to a MOS pipe control circuit and device.

Background

The MOS Transistor is an abbreviation of MOSFET, and the MOSFET is a Metal-Oxide-Semiconductor Field Effect Transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET for short). In a circuit, a MOS transistor is generally used as a switching transistor to control the on/off of the circuit, and the principle is to use the gate of the MOS transistor to control the on/off of the source and the drain of the MOS transistor, thereby constructing a switching circuit. The MOS tube comprises an N-channel MOS tube and a P-channel MOS tube, wherein due to the characteristics of the P-channel MOS tube, Vgs is conducted when the Vgs is smaller than a certain value and is suitable for the condition that a source electrode is connected with VCC, and Vgs refers to the voltage of a grid electrode G and the source electrode S, namely the grid electrode is conducted when the grid electrode is lower than the power supply by a certain voltage. And due to the characteristics of the N-channel MOS tube, the Vgs is conducted when the Vgs is larger than a certain value, the N-channel MOS tube is suitable for the situation when the source electrode is grounded, as long as the grid voltage is larger than the Vgs given in a parameter manual, the drain electrode D is connected with a power supply, and the source electrode S is grounded.

In Battery Management System (BMS), the condition that needs multiple mode to control charge-discharge MOS pipe exists, but current MOS pipe control often is that MCU output control signal realizes controlling the MOS pipe to the MOS pipe, and the mode is more single, can't control the break-make of MOS pipe at any time, for example can't turn off the MOS pipe after MCU breaks down inefficacy, leads to the inflexible inconvenience of MOS pipe control.

SUMMERY OF THE UTILITY MODEL

The utility model provides a MOS pipe control circuit aims at solving the single problem of current MOS pipe control mode.

The utility model discloses a realize like this, a MOS pipe control circuit, include:

the level conversion module is connected with the at least two control signal ends and used for respectively receiving the control signals input by the at least two control signal ends and converting the control signals into level signals with preset voltage values;

the gate logic module is connected with the output end of the level conversion module and used for receiving at least two level signals output by the level conversion module and carrying out logic and operation to generate a driving control signal;

and the output end of the driving module is connected with the control end of the target MOS tube.

Furthermore, the level conversion module comprises an acquisition end conversion unit and a control chip signal unit, the at least two control signal ends comprise a first control signal end and a second control signal end, the input end of the acquisition end conversion unit is connected with the first control signal end, and the output end of the acquisition end conversion unit is connected with the first input end of the gate logic module; the input end of the control chip signal unit is connected with the second control signal end, and the output end of the control chip signal unit is connected with the second input end of the gate logic module.

Furthermore, the acquisition terminal conversion unit comprises a first resistor R1 having one end connected to the first control signal terminal, the other end of the first resistor R1 is connected to the cathode of a first zener diode Z1, the anode of the first zener diode Z1 is grounded, the first zener diode Z1 is connected in parallel with a second resistor R2, the other end of the first resistor R1 is further connected to the gate of a first field-effect transistor Q1, the source of the first field-effect transistor Q1 is grounded, the drain of the first field-effect transistor Q1 is connected to the internal voltage terminal VDD through a third resistor R3, the drain of the first field-effect transistor Q1 is further connected to the gate of a second field-effect transistor Q2, the source of the second field-effect transistor Q2 is connected to the internal voltage terminal VDD, the drain of the second field-effect transistor Q2 is grounded through a fourth resistor R4 and a fifth resistor R5 in sequence, the end of the fourth resistor R4 connected to the fifth resistor R5 is further connected to the acquisition signal output terminal a _ DSG, the acquisition signal output end A _ DSG is connected with the first input end; the control chip signal unit comprises an MCU, a signal input end of the MCU is connected with the second control signal end, and an MCU signal output end M _ DSG of the MCU is connected with the second input end.

Furthermore, the level conversion module further comprises a controller signal conversion unit and a switch signal conversion unit, the at least two control signal ends further comprise a third control signal end and a fourth control signal end, the input end of the controller signal conversion unit is connected with the third control signal end, and the output end of the controller signal conversion unit is connected with the third input end of the gate logic module; the input end of the switching signal conversion unit is connected with the fourth control signal end, and the output end of the switching signal conversion unit is connected with the fourth input end of the gate logic module.

Furthermore, the controller signal conversion unit includes a sixth resistor R6 having one end connected to the third control signal end, the other end of the sixth resistor R6 is connected to the first input end of the optocoupler, the second input end of the optocoupler is connected to ground, the first output end of the optocoupler is connected to the internal voltage end VDD, the second output end of the optocoupler is connected to ground through a seventh resistor R7, the second output end of the optocoupler is connected to the controller signal output end CTRL, and the controller signal output end CTRL is connected to the third input end.

Further, the switching signal converting unit includes a switch S1 having one end connected to the fourth control signal end, the other end of the switch S1 is connected to the cathode of a second zener diode Z2 through an eighth resistor R8, the anode of the second zener diode Z2 is grounded, the second zener diode Z2 is connected in parallel to a ninth resistor R9, the cathode of the second zener diode Z2 is further connected to the gate of the third fet Q3, the source of the third fet Q3 is grounded, the drain of the third fet Q3 is connected to the internal voltage end through a tenth resistor R10, the drain of the third fet Q3 is further connected to the gate of the fourth fet Q4, the source of the fourth fet Q4 is connected to the internal voltage end VDD, the drain of the fourth fet Q4 is grounded through an eleventh resistor R11 and a twelfth resistor R12 in sequence, the end of the eleventh resistor R11 connected to the twelfth resistor R12 is further connected to the switching signal output end SW, the switch signal output end SW is connected with the fourth input end.

Furthermore, the gate logic module includes a first gate logic chip U1, a first pin of the first gate logic chip U1 is connected to the acquisition signal output terminal a _ DSG as a first input terminal, a second pin of the first gate logic chip U1 is connected to the MCU signal output terminal M _ DSG as a second input terminal, a third pin of the first gate logic chip U1 is grounded, a fourth pin of the first gate logic chip U1 is connected to the input terminal of the driving module, a fifth pin of the first gate logic chip U1 is connected to the internal voltage terminal VDD, and a fifth pin of the first gate logic chip U1 is also grounded through a first capacitor C1.

Furthermore, the gate logic module includes a second gate logic chip U2 and a third gate logic chip U3, a first pin of the second gate logic chip U2 is connected as a third input terminal to the controller signal output terminal CTRL, a second pin of the second gate logic chip U2 is connected as a fourth input terminal to the switch signal output terminal SW, a third pin of the second gate logic chip U2 is grounded, a fifth pin of the second gate logic chip U2 is connected to the internal voltage terminal VDD, and a fifth pin of the second gate logic chip U2 is also grounded through a second capacitor C2; the first pin of the third gate logic chip U3 is connected with the fourth pin of the first gate logic chip U1, the second pin of the third gate logic chip U3 is connected with the fourth pin of the second gate logic chip U2, the third pin of the third gate logic chip U3 is grounded, the fourth pin of the third gate logic chip U3 is connected with the input end of the driving module, the fifth pin of the third gate logic chip U3 is connected to the internal voltage end VDD, and the fifth pin of the third gate logic chip U3 is grounded through a third capacitor C3.

Furthermore, the driving module includes a thirteenth resistor R13, one end of the thirteenth resistor R13 is used as an input end of the driving module and is connected to an output end of the gate logic module, the other end of the thirteenth resistor R13 is connected to the gate of the fifth field effect transistor Q5, the source of the fifth field effect transistor Q5 is grounded, a fourteenth resistor R14 is connected between the gate and the source of the fifth field effect transistor Q5, the drain of the fifth field effect transistor Q5 is connected to the first voltage terminal VAE through the fifteenth resistor R15 and the sixteenth resistor R16 in sequence, the first voltage terminal VAE is further connected to the emitter of the triode Q6, the base of the triode Q6 is connected to a line between the fifteenth resistor R15 and the sixteenth resistor R16, the collector of the triode Q6 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to a driving signal output terminal DSG _ MOS through the seventeenth resistor R17, and the driving signal output terminal DSG _ MOS is used for being connected to a control end of the target MOS.

Furthermore, the driving module further includes an eighteenth resistor R18, one end of the eighteenth resistor R18 is connected to the output terminal of the gate logic module as the input terminal of the driving module, the other end of the eighteenth resistor R18 is connected to the gate of the sixth fet Q7, the source of the sixth fet Q7 is grounded, a nineteenth resistor R19 is connected between the gate and the source of the sixth fet Q7, the drain of the sixth fet Q7 is connected to the gate of the seventh fet Q8, the gate of the seventh fet Q8 is further connected to the first voltage terminal VAE through a twentieth resistor R20, the source of the seventh fet Q8 is grounded, a twenty-first resistor R21 is connected between the gate and the source of the seventh fet Q8, the drain of the seventh fet Q8 is connected to the driving signal output terminal DSG _ MOS through a twelfth resistor R22, the driving signal output terminal DSG _ MOS is further grounded through a thirteenth resistor R23 and a fourth capacitor C4, the driving signal output terminal DSG _ MOS is also connected to the cathode of the third zener diode Z3, and the anode of the third zener diode Z3 is grounded.

Furthermore, the driving module further includes a fifth capacitor C5, and the first voltage terminal VAE is grounded through the fifth capacitor C5.

In a second aspect, the present application further provides a MOS transistor control apparatus, which includes a target MOS transistor and the MOS transistor control circuit as described above, wherein a control terminal of the target MOS transistor is connected to an output terminal of a driving module of the MOS transistor control circuit.

The embodiment of the utility model provides a through setting up level conversion module, level conversion module is used for converting the control signal of two way at least control signal end input into the level signal of predetermineeing the magnitude of voltage, and export this level signal to gate logic module, gate logic module is used for carrying out logic and operation according to a plurality of received level signals and generates drive control signal and export to drive module, drive module is used for the break-make through drive control signal control target MOS pipe, because two at least level signals are through logic and operation back control target MOS pipe, so when one of them control mode became invalid, break-make through other control mode control MOS pipe, improve the flexibility of MOS pipe control.

Drawings

Fig. 1 is a schematic block diagram of a MOS control circuit provided by the present invention;

fig. 2 is a schematic diagram of a unit structure of an embodiment of a level shift module provided by the present invention;

fig. 3 is a schematic circuit diagram of a MOS control circuit according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a unit structure of another embodiment of a level shift module provided by the present invention;

fig. 5 is a schematic circuit diagram of a MOS control circuit according to another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The existing MOS tube control mode is usually realized by MCU control, when the MCU fails, the MOS tube can not be controlled to be turned off in time, and the control mode is single and inflexible. This application is through the break-make of multiple control mode combination control MOS pipe, when one of them control mode broke down inefficacy, can realize the control of MOS pipe through other control mode, improves the flexibility of MOS pipe control.

Example one

In some alternative embodiments, please refer to fig. 1, in which fig. 1 is a block diagram of a control circuit according to an embodiment of the present application.

As shown in fig. 1, the present application provides a MOS transistor control circuit, which includes a level shift module 1, a gate logic module 2, and a driving module 3.

The level conversion module 1 is connected with at least two control signal ends and used for respectively receiving control signals input by the at least two control signal ends and converting the control signals into level signals with preset voltage values; the gate logic module 2 is connected with the output end of the level conversion module 1 and is used for receiving at least two level signals output by the level conversion module and carrying out logic and operation to generate a driving control signal; the driving module 3 is connected with the output end of the gate logic module 2, and the output end of the driving module 3 is connected with the control end of the target MOS tube.

In implementation, the level conversion module 1 is connected to at least two control signal terminals, where the control signal terminals are used to output control signals, the level values of the control signals output by different control signal terminals are different, and the level conversion module 1 converts each control signal into a level signal with a uniform voltage value, for example, uniformly converts the control signal into a TTL level signal, which is the level of a TTL device and includes a range of high level and low level, and in implementation, the TTL level signal specifies that +5V is equivalent to logic "1" and 0V is equivalent to logic "0" (when binary is used to represent data). Such a data communication and level regulation method is called a TTL (transistor-transistor logic level) signal.

The gate logic module 2 receives the plurality of level signals output by the level conversion module 1 to perform logical and operation to generate a driving control signal, in some embodiments, taking the example that the gate logic module 2 receives two level signals, namely a first level signal corresponding to one control signal terminal and a second level signal corresponding to the other control signal terminal, the gate logic module 2 performs and operation on the first level signal and the second level signal to generate the driving control signal, and outputs the driving control signal to the driving module 3, the output end of the driving module 3 is connected with the control end of the target MOS tube, the MOS tube is a metal oxide semiconductor field effect transistor, the MOS tube has G, D, S three pins, wherein, G, D, S three feet respectively represent the grid, the drain and the source of the MOS tube, the control end of the target MOS tube is the grid of the MOS tube, and controlling the level of the control end of the target MOS tube through the driving module 3 according to the driving control signal. For example, the control signal terminal is a 5V high level signal output by the MCU, the other control signal terminal is a 3.3V power voltage signal output by the power supply terminal, the level shift module 1 can uniformly shift the 5V high level signal and the 3.3V power voltage signal output by the MCU into a 3V level signal, in the gate logic block 2, 3V is equivalent to logic "1" and 0V is equivalent to logic "0", then two level signals equivalent to logic "1" are received by the gate logic block 2, then, the AND operation is carried out according to the level signal to generate a driving control signal and the driving control signal is output to the driving module 3, the driving module 3 controls the MOS tube to be continuously conducted, taking an MOS transistor as a PMOS (P-channel MOS transistor) transistor as an example, the output end of the driving module 3 is connected with the grid electrode of the PMOS transistor, when the driving module 3 outputs high level to the PMOS tube to enable Vgs of the PMOS tube to be smaller than a conduction threshold value, the PMOS tube is continuously conducted; when the MCU fails, the MCU continuously outputs a 5V high level signal to cause the MCU to be incapable of automatically turning off the MOS tube, and at the moment, if the MCU wants to turn off the MOS tube, the other control signal end is 0V by disconnecting the 3.3V power supply voltage signal, at this time, the level conversion module 1 receives the two control signals of 5V and 0V, then outputs two level signals of 3V and 0V respectively, that is, the gate logic module 2 receives one of the level signals equivalent to logic "1", and the other level signal equivalent to logic "0", the gate logic module 2 performs a logical and operation according to the two level signals to generate a driving control signal and output the driving control signal to the driving module 3, and the driving module 3 controls the MOS transistor not to be turned on according to the driving control signal, or taking the above PMOS as an example, the driving module 3 outputs a low level to turn off the PMOS transistor, thereby realizing flexible control of the target MOS transistor.

This application embodiment is through setting up level conversion module 1, level conversion module 1 is used for converting the control signal of two at least control signal end inputs into the level signal of default voltage value, and export level signal to gate logic module 2, gate logic module 2 is used for carrying out logic and operation according to a plurality of level signals and generates drive control signal and export to drive module 3, drive module 3 is used for the break-make through drive control signal control target MOS pipe, because at least two control signal pass through gate logic and operation back control target MOS pipe, when one of them control mode became invalid, can control the break-make of MOS pipe through other control mode, improve the flexibility of MOS pipe control.

Example two

In some alternative embodiments, please refer to fig. 2, where fig. 2 is a schematic diagram of a unit structure of a level shifter module according to an embodiment of the present application.

As shown in fig. 2, the level shift module 1 includes a collecting end shift unit 11 and a control chip signal unit 12, at least two control signal ends include a first control signal end and a second control signal end, an input end of the collecting end shift unit 11 is connected to the first control signal end, and an output end of the collecting end shift unit 11 is connected to a first input end of the gate logic module 2; the input end of the control chip signal unit 12 is connected to the second control signal end, and the output end of the control chip signal unit 12 is connected to the second input end of the gate logic module 2.

In practice, please refer to fig. 3, fig. 3 is a schematic circuit structure diagram according to an embodiment of the present application.

As shown in fig. 3, the acquisition terminal conversion unit 11 includes a first resistor R1 having one end connected to an acquisition signal terminal DSG _ D, the acquisition signal terminal DSG _ D is a first control signal terminal, the other end of the first resistor R1 is connected to the cathode of a first zener diode Z1, the anode of the first zener diode Z1 is grounded, the first zener diode Z1 is connected in parallel with a second resistor R2, the other end of the first resistor R1 is further connected to the gate of a first fet Q1, the source of the first fet Q1 is grounded, the drain of the first fet Q1 is connected to an internal voltage terminal VDD through a third resistor R3, the drain of the first fet Q1 is further connected to the gate of a second fet Q2, the source of the second fet Q2 is connected to the internal voltage terminal VDD, the drain of the second fet Q2 is sequentially connected to the fourth resistor R4 and a fifth resistor R5, the fourth resistor R4 and the fifth resistor R5 are connected to the signal output terminal DSG _ D, the acquisition signal output end A _ DSG is connected with a first input end of the gate logic module 2; the control chip signal unit 12 comprises an MCU, a signal input end of the MCU is connected with the second control signal end, and an MCU signal output end M _ DSG of the MCU is connected with the second input end.

In implementation, the collection signal terminal DSG _ D inputs a collection signal, for example, the collection signal terminal DSG _ D is connected to a temperature sensor or a humidity sensor, so as to receive a temperature or humidity collection signal collected by the temperature sensor or the humidity sensor, when the collection signal terminal DSG _ D is at a high level, the first fet Q1 is turned on and the second fet Q2 is turned on, the collection signal output terminal a _ DSG outputs a voltage of the internal voltage terminal VDD to the first input terminal of the gate logic module 2, the internal voltage terminal VDD is a working voltage of the circuit, since electrical signal levels of output signals of the temperature sensor or the humidity sensor are not consistent, the collection terminal conversion unit can output a control signal of a uniform level signal, the MCU outputs the control signal to the second input terminal of the gate logic module 2 through the MCU signal output terminal according to the control signal of the second control signal terminal, the MCU can be not connected with the second control signal end and directly outputs the control signal to the second input end of the gate logic module 2 in a timed or self-triggered mode, and the control signal output by the MCU is consistent with the level of the internal voltage end VDD, so that the gate logic module 2 can conveniently carry out logic AND operation to generate a driving control signal.

EXAMPLE III

In some embodiments, the gate logic module 2 of the MOS transistor control circuit provided by the present application includes a first gate logic chip U1, a first pin of the first gate logic chip U1 is connected as a first input terminal to the acquisition signal output terminal a _ DSG, a second pin of the first gate logic chip U1 is connected as a second input terminal to the MCU signal output terminal M _ DSG, a third pin of the first gate logic chip U1 is grounded, a fourth pin of the first gate logic chip U1 is connected to an input terminal of the driving module 3, a fifth pin of the first gate logic chip U1 is connected to the internal voltage terminal VDD, and a fifth pin of the first gate logic chip U1 is further grounded through a first capacitor C1.

The first input end and the second input end of the first gate logic chip U1 are respectively connected with the acquisition signal output end a _ DSG and the MCU signal output end M _ DSG, the first gate logic chip U1 is a hardware circuit chip capable of implementing basic logic and operation, taking the first gate logic chip U1 as and gate logic as an example, for example, the model of the first gate logic chip U1 is SN74AHC1G08, SN74AHC1G08 is a logic chip for two-way input signal and gate operation, and the input voltage range of the SN74AHC1G08 is-0.5V-7V, so that a preset voltage value can be set between-0.5V-7V, for example, at least two control signals are uniformly converted into a level signal with a voltage value of 2V and then output to the SN74AHC1G08 chip, so as to meet the operation requirement of the SN74AHC1G08 chip. Taking the example that the level conversion module 1 outputs two paths of level signals, the first input end of the SN74AHC1G08 chip is connected with one output end of the level conversion module 1 for receiving one path of level signal, the second input end of the SN74AHC1G08 chip is connected with the other output end of the level conversion module 1 for receiving the other path of level signal, and the fourth pin of the SN74AHC1G08 chip outputs the driving control signal DSG to the input end of the driving module 3, thereby controlling the on-off of the target MOS transistor through the driving module 3.

Example four

In some alternative embodiments, please refer to fig. 4, where fig. 4 is a schematic diagram of a unit structure of a level shifter module according to another embodiment of the present application.

As shown in fig. 4, the level shift module 1 further includes a controller signal conversion unit 13 and a switch signal conversion unit 14, the at least two control signal terminals further include a third control signal terminal and a fourth control signal terminal, an input terminal of the controller signal conversion unit 13 is connected to the third control signal terminal, and an output terminal of the controller signal conversion unit 13 is connected to a third input terminal of the gate logic module 2; the input end of the switching signal conversion unit 14 is connected to the fourth control signal end, and the output end of the switching signal conversion unit 14 is connected to the fourth input end of the and logic module 2.

In practice, please refer to fig. 5, fig. 5 is a schematic circuit structure diagram according to an embodiment of the present application.

As shown in fig. 5, the controller signal converting unit 13 includes a sixth resistor R6 having one end connected to the controller signal terminal CONTROL, i.e., a third CONTROL signal terminal, the other end of the sixth resistor R6 is connected to the first input terminal of the optical coupler, the second input terminal of the optical coupler is grounded, the first output terminal of the optical coupler is connected to the internal voltage terminal VDD, the second output terminal of the optical coupler is grounded through a seventh resistor R7, the second output terminal of the optical coupler is connected to the controller signal output terminal CTRL, and the controller signal output terminal CTRL is connected to the third input terminal of the gate logic module 2.

In some alternative embodiments, the switching signal converting unit 14 of the MOS transistor control circuit provided in the present application includes a switch S1 having one end connected to an external voltage terminal VCC, where the external voltage terminal VCC is a fourth control signal terminal, the other end of the switch S1 is connected to the cathode of a second zener diode Z2 through an eighth resistor R8, the anode of the second zener diode Z2 is grounded, the second zener diode Z2 is connected in parallel to a ninth resistor R9, the cathode of the second zener diode Z2 is further connected to the gate of a third fet Q3, the source of the third fet Q3 is grounded, the drain of the third fet Q3 is connected to the internal voltage terminal VDD through a tenth resistor R10, the drain of the third fet Q3 is further connected to the gate of a fourth fet Q4, the source of the fourth fet Q4 is connected to the internal voltage terminal VDD, the drain of the fourth fet Q4 is grounded through an eleventh resistor R11 and a twelfth resistor R12 in sequence, one end of the eleventh resistor R11, which is connected to the twelfth resistor R12, is further connected to the switch signal output terminal SW, and the switch signal output terminal SW is connected to the fourth input terminal of the and logic module 2.

In some optional embodiments, the gate logic module 2 of the MOS transistor control circuit provided by the present application includes a second gate logic chip U2 and a third gate logic chip U3, a first pin of the second gate logic chip U2 is connected as a third input terminal to the controller signal output terminal CTRL, a second pin of the second gate logic chip U2 is connected as a fourth input terminal to the switch signal output terminal SW, a third pin of the second gate logic chip U2 is grounded, a fifth pin of the second gate logic chip U2 is connected to the internal voltage terminal VDD, a fifth pin of the second gate logic chip U2 is further grounded through a second capacitor C2, a first pin of the third gate logic chip U3 is connected to a fourth pin of the first gate logic chip U1, a second pin of the third gate logic chip U3 is connected to a fourth pin of the second gate logic chip U2, a third pin of the third gate logic chip U3 is grounded, a fourth pin of the third gate logic chip U3 is connected to the input terminal of the driver module U353, the fifth pin of the third gate logic chip U3 is connected to the internal voltage terminal VDD, and the fifth pin of the third gate logic chip U3 is also connected to ground through a third capacitor C3.

The first gate logic chip U1 is configured to output a first driving control signal DSG1 to a first pin of the third gate logic chip U3 after performing a logical and operation on a control signal output by the acquisition signal output terminal a _ DSG and a control signal output by the MCU signal output terminal M _ DSG, the second gate logic chip U2 is configured to output a second driving control signal DSG2 to a second pin of the third gate logic chip U3 after performing a logical and operation on a control signal output by the controller signal output terminal CTRL and a control signal output by the switch signal output terminal SW, and the third gate logic chip U3 performs a logical and operation on the first driving control signal DSG1 and the second driving control signal DSG2 to generate a driving control signal DSG and output the driving control signal DSG to an input terminal of the driving module 3.

EXAMPLE five

In some alternative embodiments, the driving module 3 of the MOS transistor control circuit provided in the present application includes a thirteenth resistor R13, one end of the thirteenth resistor R13 is used as an input terminal of the driving module 3 and is connected to an output terminal of the gate logic module 2, the other end of the thirteenth resistor R13 is connected to a gate of a fifth fet Q5, a source of the fifth fet Q5 is grounded, a fourteenth resistor R14 is connected between a gate and a source of the fifth fet Q5, a drain of the fifth fet Q5 is connected to the first voltage terminal VAE through a fifteenth resistor R15 and a sixteenth resistor R16 in sequence, the first voltage terminal VAE is further connected to an emitter of a transistor Q6, a base of the transistor Q6 is connected to a line between the fifteenth resistor R15 and the sixteenth resistor R16, a collector of the transistor Q6 is connected to an anode of a diode D1, a cathode of the diode D1 is connected to the driving signal output terminal DSG _ MOS through a seventeenth resistor R17, and the driving signal output end DSG _ MOS is used for being connected with the control end of the target MOS tube.

In implementation, when the driving control signal output by the gate logic module 2 is at a high level, the fifth fet Q5 is turned on to turn on the transistor Q6, and the first voltage terminal VAE sequentially passes through the transistor Q6, the diode D1, and the seventeenth resistor R17 to output a voltage to the driving signal output terminal DSG _ MOS, thereby implementing a function of controlling the MOS transistor.

EXAMPLE six

In some optional embodiments, the driving module 3 of the MOS transistor control circuit provided in the present application further includes an eighteenth resistor R18, one end of the eighteenth resistor R18 is connected as an input end of the driving module 3 to an output end of the gate logic module 2, the other end of the eighteenth resistor R18 is connected to a gate of a sixth fet Q7, a source of the sixth fet Q7 is grounded, a nineteenth resistor R19 is connected between a gate and a source of the sixth fet Q7, a drain of the sixth fet Q7 is connected to a gate of a seventh fet Q8, a gate of the seventh fet Q8 is further connected to the first voltage terminal VAE through a twentieth resistor R20, a source of the seventh fet Q8 is grounded, a twenty-first resistor R21 is connected between the gate and the source of the seventh fet Q8, a drain of the seventh fet Q8 is connected to the driving signal output terminal DSG _ MOS through a twelfth resistor R22, when the driving control signal DSG output by the gate logic module 2 is at a high level, the fifth field effect transistor Q5 is turned on, so that the triode Q6 is turned on, and the sixth field effect transistor Q7 is turned on, so that the seventh field effect transistor Q8 is not turned on, and the driving signal output terminal DSG _ MOS outputs a high level signal to the gate of the target MOS transistor, so as to control the MOS transistor to be continuously turned on; when the driving control signal DSG outputted by the gate logic module 2 is at a low level, the fifth field effect transistor Q5 is not turned on, so that the triode Q6 is not turned on, and the sixth field effect transistor Q7 is not turned on, so that the seventh field effect transistor Q8 is turned on, the driving signal output terminal DSG _ MOS is pulled to a low level, the target MOS transistor is not turned on, a circuit is subjected to a bleeding effect, and the circuit is prevented from being damaged by components in the circuit due to power supply disconnection. In addition, the driving signal output terminal DSG _ MOS is grounded through a thirteenth resistor R23 and a fourth capacitor C4, respectively, the driving signal output terminal DSG _ MOS is further connected to the cathode of a third zener diode Z3, the anode of the third zener diode Z3 is grounded, the third zener diode Z3 can keep the voltage of the driving signal output terminal DSG _ MOS stable, when the driving signal output terminal DSG _ MOS outputs a high level, the fourth capacitor C4 is charged, and when the driving signal output terminal DSG _ MOS outputs a low level, the fourth capacitor C4 is discharged through a thirteenth resistor 23, which can effectively filter the peak generated when the voltage is switched on, reduce the voltage fluctuation, and provide the circuit stability.

In implementation, the driving module 3 further includes a fifth capacitor C5, and the first voltage terminal VAE is grounded through the fifth capacitor C5. The fifth capacitor C5 filters the power supply to reduce interference with the circuit.

EXAMPLE seven

In some optional embodiments, the present application further provides a MOS transistor control apparatus, which includes a target MOS transistor and a MOS transistor control circuit as described above, wherein a control terminal of the target MOS transistor is connected to an output terminal of the driving module 3 of the MOS transistor control circuit. MOS pipe control circuit includes level conversion module 1, gate logic module 2 and drive module 3, level conversion module 1 is used for converting the control signal of two at least control signal end inputs into the level signal of predetermineeing the voltage value, and with level signal output to gate logic module 2, gate logic module 2 is used for carrying out logic and operation according to a plurality of level signals and generates drive control signal and export to drive module 3, drive module 3 is used for the break-make through drive control signal control target MOS pipe, because at least two control signal pass through gate logic and operation back control target MOS pipe, so the control mode to MOS pipe is various, realize the break-make of multiple mode combination control MOS pipe, control MOS pipe in a flexible way.

The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.

Claims

1. A MOS transistor control circuit, comprising:

and the driving module is connected with the output end of the gate logic module, and the output end of the driving module is connected with the control end of the target MOS tube.

2. The MOS tube control circuit according to claim 1, wherein the level shift module comprises a sampling terminal shift unit and a control chip signal unit, the at least two control signal terminals comprise a first control signal terminal and a second control signal terminal, an input terminal of the sampling terminal shift unit is connected to the first control signal terminal, and an output terminal of the sampling terminal shift unit is connected to the first input terminal of the gate logic module; the input end of the control chip signal unit is connected with the second control signal end, and the output end of the control chip signal unit is connected with the second input end of the gate logic module.

3. The MOS transistor control circuit of claim 2, wherein the collector terminal conversion unit comprises a first resistor R1 having one terminal connected to the first control signal terminal, the other terminal of the first resistor R1 is connected to a cathode of a first zener diode Z1, an anode of the first zener diode Z1 is grounded, the first zener diode Z1 is connected in parallel with a second resistor R2, the other terminal of the first resistor R1 is further connected to a gate of a first field effect transistor Q1, a source of the first field effect transistor Q1 is grounded, a drain of the first field effect transistor Q1 is connected to an internal voltage terminal VDD through a third resistor R3, a drain of the first field effect transistor Q1 is further connected to a gate of a second field effect transistor Q2, a source of the second field effect transistor Q2 is connected to the internal voltage terminal VDD, a drain of the second field effect transistor Q2 is sequentially connected to a ground through a fourth resistor R4 and a fifth resistor R5, one end of the fourth resistor R4, which is connected with the fifth resistor R5, is also connected to a collection signal output end A _ DSG, which is connected with the first input end; the control chip signal unit comprises an MCU, the signal input end of the MCU is connected with the second control signal end, and the MCU signal output end M _ DSG of the MCU is connected with the second input end.

4. The MOS tube control circuit of claim 3, wherein the level shift module further comprises a controller signal shift unit and a switch signal shift unit, the at least two control signal terminals further comprise a third control signal terminal and a fourth control signal terminal, an input terminal of the controller signal shift unit is connected to the third control signal terminal, and an output terminal of the controller signal shift unit is connected to the third input terminal of the gate logic module; the input end of the switching signal conversion unit is connected with the fourth control signal end, and the output end of the switching signal conversion unit is connected with the fourth input end of the gate logic module.

5. The MOS tube control circuit of claim 4, wherein the controller signal converting unit comprises a sixth resistor R6 having one end connected to the third control signal end, the other end of the sixth resistor R6 is connected to a first input end of an optocoupler, a second input end of the optocoupler is connected to ground, a first output end of the optocoupler is connected to the internal voltage end VDD, a second output end of the optocoupler is connected to ground through a seventh resistor R7, a second output end of the optocoupler is connected to a controller signal output end CTRL, and the controller signal output end CTRL is connected to the third input end.

6. The MOS transistor control circuit of claim 5, wherein the switching signal converting unit includes a switch S1 having one end connected to the fourth control signal terminal, the other end of the switch S1 is connected to a cathode of a second zener diode Z2 through an eighth resistor R8, an anode of the second zener diode Z2 is grounded, the second zener diode Z2 is connected in parallel to a ninth resistor R9, a cathode of the second zener diode Z2 is further connected to a gate of a third FET Q3, a source of the third FET Q3 is grounded, a drain of the third FET Q3 is connected to the internal voltage terminal VDD through a tenth resistor R10, a drain of the third FET Q3 is further connected to a gate of a fourth FET Q4, a source of the fourth FET Q4 is connected to the internal voltage terminal, a drain of the fourth FET Q4 is grounded through an eleventh resistor R11 and a twelfth resistor R12 in sequence, one end of the eleventh resistor R11 connected to the twelfth resistor R12 is further connected to a switch signal output terminal SW, and the switch signal output terminal SW is connected to the fourth input terminal.

7. The MOS transistor control circuit of claim 6, wherein the gate logic module comprises a first gate logic chip U1, a first pin of the first gate logic chip U1 is connected as the first input terminal to the acquisition signal output terminal A _ DSG, a second pin of the first gate logic chip U1 is connected as the second input terminal to the MCU signal output terminal M _ DSG, a third pin of the first gate logic chip U1 is connected to ground, a fourth pin of the first gate logic chip U1 is connected to an input terminal of the driving module, a fifth pin of the first gate logic chip U1 is connected to the internal voltage terminal VDD, and a fifth pin of the first gate logic chip U1 is further connected to ground through a first capacitor C1.

8. The MOS transistor control circuit of claim 7, wherein the gate logic module comprises a second gate logic chip U2 and a third gate logic chip U3, a first pin of the second gate logic chip U2 is connected as the third input terminal to the controller signal output terminal CTRL, a second pin of the second gate logic chip U2 is connected as the fourth input terminal to the switch signal output terminal SW, a third pin of the second gate logic chip U2 is grounded, a fifth pin of the second gate logic chip U2 is connected to the internal voltage terminal VDD, and a fifth pin of the second gate logic chip U2 is further grounded through a second capacitor C2; the first pin of the third gate logic chip U3 is connected with the fourth pin of the first gate logic chip U1, the second pin of the third gate logic chip U3 is connected with the fourth pin of the second gate logic chip U2, the third pin of the third gate logic chip U3 is grounded, the fourth pin of the third gate logic chip U3 is connected with the input end of the driving module, the fifth pin of the third gate logic chip U3 is connected to the internal voltage end VDD, and the fifth pin of the third gate logic chip U3 is grounded through a third capacitor C3.

9. The MOS transistor control circuit of claim 1, wherein the driving module comprises a thirteenth resistor R13, one end of the thirteenth resistor R13 is connected to the output end of the gate logic module as the input end of the driving module, the other end of the thirteenth resistor R13 is connected to the gate of a fifth field effect transistor Q5, the source of the fifth field effect transistor Q5 is grounded, a fourteenth resistor R14 is connected between the gate and the source of the fifth field effect transistor Q5, the drain of the fifth field effect transistor Q5 is connected to a first voltage terminal VAE through a fifteenth resistor R15 and a sixteenth resistor R16 in turn, the first voltage terminal VAE is further connected to the emitter of a transistor Q6, the base of the transistor Q6 is connected to the line between the fifteenth resistor R15 and the sixteenth resistor R16, the collector of the transistor Q6 is connected to the anode of a diode D1, the cathode of the diode D1 is connected to a driving signal output terminal DSG _ MOS through a seventeenth resistor R17, and the driving signal output terminal DSG _ MOS is used for being connected to the control terminal of the target MOS transistor.

10. The MOS transistor control circuit of claim 9, wherein the driving module further includes an eighteenth resistor R18, one end of the eighteenth resistor R18 is connected as an input terminal of the driving module to the output terminal of the gate logic module, the other end of the eighteenth resistor R18 is connected to a gate of a sixth field-effect transistor Q7, a source of the sixth field-effect transistor Q7 is grounded, a nineteenth resistor R19 is connected between the gate and the source of the sixth field-effect transistor Q7, a drain of the sixth field-effect transistor Q7 is connected to a gate of a seventh field-effect transistor Q8, the gate of the seventh field-effect transistor Q8 is further connected to the first voltage terminal VAE through a twentieth resistor R20, a source of the seventh field-effect transistor Q8 is grounded, a twenty-first resistor R21 is connected between the gate and the source of the seventh field-effect transistor Q8, a drain of the seventh field-effect transistor Q8 is connected to the driving signal output terminal DSG _ MOS through a twelfth resistor R22, the driving signal output terminal DSG _ MOS is further grounded through a twenty-third resistor R23 and a fourth capacitor C4, respectively, the driving signal output terminal DSG _ MOS is further connected to the cathode of a third zener diode Z3, and the anode of the third zener diode Z3 is grounded.

11. The MOS tube control circuit of claim 10, wherein the driving module further comprises a fifth capacitor C5, the first voltage terminal VAE being connected to ground through the fifth capacitor C5.

12. A MOS transistor control apparatus, comprising a target MOS transistor and the MOS transistor control circuit according to any one of claims 1 to 11, wherein a control terminal of the target MOS transistor is connected to an output terminal of a driving module of the MOS transistor control circuit.