CN210807224U - Level conversion circuit - Google Patents
Level conversion circuit Download PDFInfo
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- CN210807224U CN210807224U CN201922113976.0U CN201922113976U CN210807224U CN 210807224 U CN210807224 U CN 210807224U CN 201922113976 U CN201922113976 U CN 201922113976U CN 210807224 U CN210807224 U CN 210807224U
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Abstract
The utility model discloses embodiment relates to electricity field, discloses a level shift circuit, and this level shift circuit includes: the device comprises a first level input end, a second level input end, an NPN type triode, a first resistor, a second resistor, a third resistor and a first level output end; one end of the first resistor is connected with the first level input end, and the other end of the first resistor is connected with an emitting electrode of the NPN type triode; one end of the second resistor is connected with the second level input end and one end of the third resistor, the other end of the second resistor is connected with the base electrode of the NPN type triode, and the other end of the third resistor is connected with the collector electrode of the NPN type triode and the first level output end. The utility model discloses embodiment provides a level shift circuit both can practice thrift PCB area occupied, again can reduce cost.
Description
Technical Field
The utility model relates to an electricity field, in particular to level shift circuit.
Background
Currently, there are two general methods for implementing level conversion: one is to realize level conversion by two triodes; one is to implement level conversion by using a chip. The first method uses two triodes, which occupies a large area of a Printed Circuit Board (PCB) and has high cost; the second method needs to be implemented by a chip, which is more costly.
SUMMERY OF THE UTILITY MODEL
An object of the embodiment of the utility model is to provide a level shift circuit, both can practice thrift PCB area occupied, again can reduce cost.
In order to solve the above technical problem, an embodiment of the present invention provides a level shift circuit, including: the device comprises a first level input end, a second level input end, an NPN type triode, a first resistor, a second resistor, a third resistor and a first level output end; one end of the first resistor is connected with the first level input end, and the other end of the first resistor is connected with an emitting electrode of the NPN type triode; one end of the second resistor is connected with the second level input end and one end of the third resistor, the other end of the second resistor is connected with the base electrode of the NPN type triode, and the other end of the third resistor is connected with the collector electrode of the NPN type triode and the first level output end.
Compared with the prior art, the embodiment of the utility model provides a level switching circuit, through changing the on and off state of NPN type triode, convert the input level into the output level effectively, reach the purpose of level conversion; because only one triode is used, the cost is low, and the occupied PCB area is small.
In addition, the level conversion circuit further comprises a capacitor, wherein one end of the capacitor is connected with the collector of the NPN type triode, and the other end of the capacitor is grounded. The capacitor is added in the level conversion circuit, so that pulses generated when the NPN type triode is conducted can be filtered, and the stability of the level conversion circuit during level conversion is improved.
In addition, the level conversion circuit further comprises a second level output end, and the second level output end is connected with an emitting electrode of the NPN type triode. The second level output end can enable the levels input by the first level input end and the second level input end to be utilized to output the levels so as to control the operation and stop of corresponding devices, and the utilization rate of the level conversion circuit is improved.
In addition, the input level of the first level input end is greater than that of the second level input end. The input level of the first level input end is greater than that of the second level input end, so that the NPN type triode can meet the cut-off condition when the first level input end inputs the level and meet the conduction condition when the first level input end stops inputting the level, and the level conversion is effectively realized.
In addition, the transmission rate of the NPN type triode is less than or equal to 10 MHz. The smaller the transmission rate of the NPN type triode, the longer the corresponding period, and in the process of level conversion, the smaller the influence of time delay on the level conversion circuit can be, and the more stable the level conversion effect is.
In addition, the resistance value of the third resistor is greater than or equal to the quotient of the resistance value of the second resistor and the amplification factor of the NPN type triode. The NPN type triode can meet the condition of saturated conduction when being conducted, the control of the first level input end to the level output by the first level output end is facilitated, and the efficiency of level conversion is improved.
In addition, the capacitance value of the capacitor is less than or equal to 50 pF. The capacitance value of the capacitor is less than or equal to 50pF, so that the capacitor can filter pulses and ensure the level conversion effect of the level conversion circuit.
In addition, the first level input end and the second level input end are both direct current input ends.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of a level shift circuit according to a first embodiment of the present invention;
fig. 2 is a schematic structural diagram of a level shift circuit according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a level shift circuit according to a third embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following will explain in detail each embodiment of the present invention with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
A first embodiment of the present invention relates to a level shift circuit, as shown in fig. 1, including: the circuit comprises a first level input terminal 10, a second level input terminal 20, a first level output terminal 30, an NPN type triode 40, a first resistor 50, a second resistor 60 and a third resistor 70.
One end of the first resistor 50 is connected to the first level input terminal 10, and the other end is connected to the emitter of the NPN-type triode 40; one end of the second resistor 60 is connected to the second level input terminal 20 and one end of the third resistor 70, the other end is connected to the base of the NPN transistor 40, and the other end of the third resistor 70 is connected to the collector of the NPN transistor 40 and the first level output terminal 30.
The input levels of the first level input terminal 10 and the second level input terminal 20 may be set according to actual needs, and the specific values are not limited in this embodiment. The third resistor 70 is a pull-up resistor, resistance values of the first resistor 50, the second resistor 60 and the third resistor 70 can be selected according to actual needs, optionally, the resistance value of the first resistor 50 is 100K ohms, and the resistance values of the second resistor 60 and the third resistor 70 are 4.7K ohms; on the premise of not considering power consumption, the resistance values of the second resistor 60 and the third resistor 70 may be 100K ohms, or may be other resistance values, which is not limited herein. The model of the NPN type triode can be selected according to actual needs, for example, the NPN type triode can be MMBT3904, and no specific limitation is made here.
Alternatively, the level input by the second level input terminal 20 may be kept unchanged, and the level input by the first level input terminal 10 is changed to switch the transistor between the on state and the off state, so that the level of the output of the first level output terminal 30 is changed, thereby achieving the purpose of level switching.
Specifically, if the level input by the first level input terminal 10 is higher than the level input by the second level input terminal 20, the level output by the first level output terminal 30 is the level input by the second level input terminal 20; if the level input from the first level input terminal 10 is lower than the level input from the second level input terminal 20, the level output from the first level output terminal 30 is equal to the level-R input from the second level input terminal 203*Ic(R3Is the resistance value, I, of the third resistor 70cThe current value at the collector of NPN transistor 40).
For example, when the input level of the second level input terminal 20 is 1.8V, if the level input by the first level input terminal 10 is higher than 1.8V, the base voltage of the NPN transistor 40 is lower than the emitter voltage, the emitter is in a reverse bias state, and the NPN transistor 40 is turned off; at this time, the output level of the first level output terminal 30 is equal to the level of the second level input terminal 20 and is 1.8V; if the level input from the first level input terminal 10 is lower than 1.8V, the base voltage of the NPN transistor 40 is higher than the emitter voltage, the emitter is in a forward bias state, the NPN transistor 40 is turned on, and the output level of the first level output terminal 30 is 1.8-R at this time3*Ic(ii) a In particular, if the level input by the first level input terminal 10 is 0, and the resistance value R3 of the third resistor 70 satisfies
When (R)2β is the resistance value of the second resistor 60, and is the amplification factor of the NPN transistor 40), at this time, the base voltage of the NPN transistor 40 is higher than the collector voltage, the collector is also in the forward bias state, and the state of saturation conduction is satisfied, and since the voltage drop between the collector and the emitter of the NPN transistor 40 is close to 0, the output level of the first level output terminal 30 is also close to 0.
It can be understood that the level input by the first level input terminal 10 may be relatively high and not meet the output requirement of the first level output terminal 30, and the level input by the first level input terminal 10 can be converted into the output level meeting the output requirement of the first level output terminal 30 by changing the on and off states of the NPN type triode 40, so as to achieve the purpose of level conversion.
Optionally, in the embodiment of the present invention, the input level of the first level input end 10 is greater than the input level of the second level input end 20, that is, the first level input end 10 and the second level input end 20 both adopt a power supply to obtain the input level, the level that the power supply can provide is constant, and the first level input end 10 can realize the input of the level and the input of the stop level through the closing and opening of the switch. The input level of the first level input terminal 10 is greater than the input level of the second level input terminal 20, so that the NPN type triode 40 can satisfy a cut-off condition when the first level input terminal 10 inputs a level and satisfy a conduction condition when the first level input terminal 10 stops inputting a level, thereby effectively achieving level conversion. Optionally, the first level input terminal 10 and the second level input terminal 20 are both direct current input terminals.
Optionally, the resistance value of the third resistor 70 is greater than or equal to the quotient of the resistance value of the second resistor 60 and the amplification factor of the NPN transistor, that is, the third resistor 70 is connected to the NPN transistor
Therefore, the NPN type triode 40 can meet the condition of saturation conduction when conducting, at this time, the voltage drop between the collector and the emitter of the NPN type triode 40 is about 0V, the level output by the first level output terminal 30 is approximately equal to the level input by the first level input terminal 10, which is more beneficial to the control of the first level input terminal 10 on the level output by the first level output terminal 30, and the efficiency of level conversion is improved.
Compared with the prior art, the level conversion circuit provided by the embodiment of the utility model effectively converts the input level into the output level by changing the on-off state of the triode, thereby achieving the purpose of level conversion; because only one triode is used, the cost is low, the occupied PCB area is small, and meanwhile, a substitute material can be easily found under the condition of material shortage.
A second embodiment of the present invention relates to a level shift circuit, and as shown in fig. 2, the second embodiment is substantially the same as the first embodiment, except that the level shift circuit of the embodiment of the present invention further includes a capacitor 80. It should be noted that, for features same as or corresponding to those of the foregoing embodiments, reference may be made to corresponding descriptions of the foregoing embodiments, which are not described in detail below.
One end of the capacitor 80 is connected to the collector of the NPN transistor 40, and the other end is grounded.
It can be understood that, at the moment when the NPN transistor 40 is turned on, there may be a transient pulse, and if the level input from the first level input terminal 10 is high, the level output from the first level output terminal 30 may be out of range, which may damage the device connected to the first level output terminal 30, so that by connecting one end of the capacitor 80 to the collector of the NPN transistor 40, that is, by also connecting the first level output terminal 30, it is possible to filter out the pulse that may occur, and stabilize the level output from the first level output terminal 30.
It should be noted that the capacitance value of the capacitor 80 cannot be too large, and the too large capacitance value causes a delay in level shifting of the level shifting circuit, which affects the level shifting effect. Optionally, the capacitance value of the capacitor 80 is less than or equal to 50pF, so that the level shifting effect of the level shifting circuit is guaranteed while the capacitor 80 filters the pulses.
Optionally, the transmission rate of the NPN transistor 40 is less than or equal to 10 MHz. It can be understood that the smaller the transmission rate of the NPN transistor 40, the longer the corresponding period, and the less the level shift circuit is affected by the time delay during the level shift, the more stable the level shift effect.
The capacitor is added in the level conversion circuit, so that pulses generated when the NPN type triode is conducted can be filtered, and the stability of the level conversion circuit during level conversion is improved.
A third embodiment of the present invention relates to a level shift circuit, and as shown in fig. 3, the third embodiment is substantially the same as the second embodiment, except that the level shift circuit of the embodiment of the present invention further includes a second level output terminal 90. It should be noted that, for features same as or corresponding to those of the foregoing embodiments, reference may be made to corresponding descriptions of the foregoing embodiments, which are not described in detail below.
The second level output terminal 90 is connected to the emitter of the NPN transistor 40.
It can be understood that the level shifting circuit turns on or off the NPN transistor 40 by changing the level input from the first level input terminal 10 for the purpose of level shifting. The emitter of the NPN transistor 40 is connected through the second level output terminal 90, so that the level input from the first level input terminal 10 can be used as an output when the NPN transistor 40 is switched between the on and off states.
For example, if the level input by the second level input terminal 20 is 1.8V, and when the level input by the first level input terminal 10 is higher than 1.8V, for example, 3.3V, the NPN transistor 40 is turned off, and the level output by the second level output terminal 90 is 3.3V; when the level input by the first level input terminal 10 is lower than 1.8V, for example, 0V, the level output by the second level output terminal 90 is 0V at this time. It can be understood that the level output by the first level output terminal is 1.8V (when the first level input terminal 10 is 3.3V) and about 0V (when the first level input terminal 10 is 0V and the saturation conduction condition is satisfied), that is, the level output by the first level output terminal 30 is switched between two values of 1.8V (high level) and 0V (low level), and the level output by the second level output terminal 90 is switched between two values of 3.3V (high level) and 0V (low level), so that the first level output terminal 30 and the second level output terminal 90 can both implement high-low level switching.
The second level output end can enable the levels input by the first level input end and the second level input end to be utilized to output the levels so as to control the operation and stop of corresponding devices, and the utilization rate of the level conversion circuit is improved.
It will be understood by those skilled in the art that the foregoing embodiments are specific examples of the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application.
Claims (8)
1. A level shift circuit, comprising: the device comprises a first level input end, a second level input end, an NPN type triode, a first resistor, a second resistor, a third resistor and a first level output end;
one end of the first resistor is connected with the first level input end, and the other end of the first resistor is connected with an emitting electrode of the NPN type triode;
one end of the second resistor is connected with the second level input end and one end of the third resistor, the other end of the second resistor is connected with the base electrode of the NPN type triode, and the other end of the third resistor is connected with the collector electrode of the NPN type triode and the first level output end.
2. The circuit of claim 1, further comprising a capacitor, wherein one end of the capacitor is connected to the collector of the NPN transistor, and the other end of the capacitor is grounded.
3. The circuit of claim 1, further comprising a second level output terminal connected to an emitter of the NPN transistor.
4. The circuit of claim 1, wherein the input level of the first level input terminal is greater than the input level of the second level input terminal.
5. The circuit of claim 1, wherein the transmission rate of the NPN transistor is less than or equal to 10 MHz.
6. The circuit of claim 1, wherein the third resistor has a resistance greater than or equal to a quotient of a resistance of the second resistor and an amplification factor of the NPN transistor.
7. The circuit of claim 2, wherein the capacitance of the capacitor is less than or equal to 50 pF.
8. The level shift circuit of any of claims 1-7, wherein the first level input and the second level input are both direct current inputs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201922113976.0U CN210807224U (en) | 2019-11-29 | 2019-11-29 | Level conversion circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201922113976.0U CN210807224U (en) | 2019-11-29 | 2019-11-29 | Level conversion circuit |
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| CN210807224U true CN210807224U (en) | 2020-06-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114326542A (en) * | 2022-01-18 | 2022-04-12 | 杭州晶华微电子股份有限公司 | Signal generating circuit for industrial hybrid control |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114326542A (en) * | 2022-01-18 | 2022-04-12 | 杭州晶华微电子股份有限公司 | Signal generating circuit for industrial hybrid control |
| CN114326542B (en) * | 2022-01-18 | 2023-12-05 | 杭州晶华微电子股份有限公司 | Industrial mixed control signal generation circuit |
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