CN216213393U

CN216213393U - Heat dissipation sheet and semiconductor circuit

Info

Publication number: CN216213393U
Application number: CN202122628655.1U
Authority: CN
Inventors: 冯宇翔; 张土明; 潘志坚; 谢荣才; 左安超
Original assignee: Guangdong Huixin Semiconductor Co Ltd
Current assignee: Guangdong Huixin Semiconductor Co Ltd
Priority date: 2021-10-29
Filing date: 2021-10-29
Publication date: 2022-04-05
Anticipated expiration: 2031-10-29

Abstract

The utility model relates to a heat sink and a semiconductor circuit, wherein the heat sink comprises a first surface and a second surface which are opposite; the first surface is used for welding combination with the power device; the second surface is provided with a plurality of grooves and is used for being welded and combined with the chip carrier; the semiconductor circuit comprises a chip carrier, a radiating fin, a power device and a driving chip; the heat sink is arranged between the chip carrier and the power device, and the second surface of the heat sink is combined with the chip carrier through solder. According to the technical scheme, the two opposite surfaces of the radiating fin are easy to distinguish, the production efficiency can be improved, the radiating efficiency of the power device can be improved, and when the radiating fin is welded, air bubbles can be discharged, the void ratio is reduced, the radiating fin is ensured to be effectively contacted with a chip carrier, the thermal resistance is reduced, and the heat capacity is improved.

Description

Heat dissipation sheet and semiconductor circuit

Technical Field

The utility model relates to a radiating fin and a semiconductor circuit, and belongs to the technical field of semiconductor circuit application.

Background

The semiconductor circuit is a power driving product combining power electronics and integrated circuit technology, and is widely applied to the field of power electronics, such as frequency converters of driving motors, various inverter voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like.

In some related art, in packaging a semiconductor circuit, a power device is directly soldered to a chip carrier such as a PCB board, a copper frame, or the like, in order to control costs. However, the semiconductor circuit package product manufactured by the manufacturing method, especially the product with the miniaturized design and the high-frequency design, is easy to have the situations of overhigh heat generation of a power device, overhigh local temperature rise, uneven heat generation of the product and uneven heat dissipation of the product when being applied; therefore, the power device is easy to lose efficacy, the work efficiency of the semiconductor circuit packaging product is low, the reliable operation of the power device is influenced, and the product service cycle of the semiconductor circuit packaging product is shortened.

In other related arts, a heat sink is added to enhance the heat dissipation efficiency of the power device when packaging the semiconductor circuit. However, the conventional heat sink is generally formed by stamping, when a stamping die is punched downwards, four corners of the heat sink are stressed and deformed, the middle of the pressure surface of the heat sink is concave, the corners of the pressure surface of the heat sink are warped, and the pressure surface of the heat sink is uneven; as a result, the heat sink is easily damaged when adhesively bonded to the power device.

SUMMERY OF THE UTILITY MODEL

The technical problem to be solved by the utility model is that the power device is easy to damage when the heat sink and the power device are welded and combined in the packaging process of the traditional semiconductor circuit.

The utility model particularly provides a heat sink which is suitable for a semiconductor package and comprises a first surface and a second surface which are opposite; the first surface is used for welding combination with a power device; the second surface is provided with a plurality of grooves and is used for being welded and combined with the chip carrier.

Optionally, the first surface is planar.

Optionally, the groove is a V-shaped groove.

Optionally, a plurality of the grooves are arranged on the second surface at intervals.

Optionally, the groove penetrates through the heat sink in a first direction, and forms groove openings at two opposite ends of the heat sink respectively; an included angle is formed between the groove walls on the two opposite sides of the groove, the included angle is alpha, and the alpha is more than or equal to 70 degrees and less than or equal to 110 degrees.

Optionally, each of the grooves extends along a first direction, and a plurality of the grooves are arranged along a second direction;

the first direction is a width direction of the heat dissipation sheet, and the second direction is a length direction of the heat dissipation sheet.

Optionally, the length of the radiating fin is R, and R is more than or equal to 4mm and less than or equal to 11 mm;

the width of the radiating fin is Y, and Y is more than or equal to 2mm and less than or equal to 8 mm;

the corner of the radiating fin is provided with a chamfer, the angle of the chamfer is K, and K is more than or equal to 2 degrees and less than or equal to 6 degrees;

the thickness of the radiating fin is H, and H is more than or equal to 0.5mm and less than or equal to 1.5 mm.

Specifically, the present invention provides a semiconductor circuit comprising:

a chip carrier;

the heat sink of the above aspect, a second surface of the heat sink being soldered to the chip carrier by a solder material;

the power device is arranged on one side of the heat radiating fin, which is far away from the chip carrier; the power device is welded with the first surface through a welding material; and the number of the first and second groups,

a driver chip disposed on the chip carrier; the driving chip is electrically connected with the power device.

Optionally, the power device includes a switching tube and a freewheeling diode;

the semiconductor circuit comprises a plurality of groups of power components, each group of power components comprises a radiating fin, a switch tube and a freewheeling diode, wherein the switch tube and the freewheeling diode are welded on the first surface of the radiating fin, the switch tube is electrically connected with the freewheeling diode through an electric connecting piece, and the switch tube is electrically connected with the driving chip through the electric connecting piece.

Optionally, the chip carrier includes a base, a pin, a circuit wiring layer, and a pad; the substrate comprises a mounting surface, the circuit wiring layer is arranged on the mounting surface, and the bonding pad is arranged on the circuit wiring layer;

the second surface of the heat sink is welded to the pad through a welding material;

the power device is electrically connected with the circuit wiring layer or the pin through an electric connector;

the semiconductor circuit further comprises a packaging body, the packaging body wraps the chip carrier, the heat radiating fin, the power device and the driving chip, and at least one part of the pin is exposed out of the packaging body;

the radiating fins are copper-based radiating fins or aluminum-based radiating fins;

the chip carrier is an IMS substrate, or a DBC frame, or a CIS frame.

The front side and the back side of the radiating fin are easy to distinguish, when the radiating fin is applied to a semiconductor circuit, the radiating efficiency of a power device can be improved, the production efficiency of the semiconductor circuit is improved, the second surface of the radiating fin is provided with a plurality of grooves, and bubbles are easier to discharge when the second surface is welded with a chip carrier by adopting a solder;

according to the semiconductor circuit, the radiating efficiency of the power device can be improved, the reliability of the power device is improved, and the service life of the power device is prolonged by configuring the radiating fins; in addition, the heat radiating fin is prevented from damaging the power device, the second surface of the heat radiating fin is provided with a plurality of grooves, so that the voidage between the heat radiating fin and the chip carrier can be effectively controlled, and the thermal resistance between the heat radiating fin and the chip carrier is reduced; the front and the back of the radiating fin can be distinguished conveniently, and the manufacturing efficiency is improved.

Drawings

FIG. 1 is a schematic view of a first surface of a heat sink in accordance with an embodiment of the present invention;

FIG. 2 is a schematic view of a second surface of a heat sink in accordance with an embodiment of the present invention;

FIG. 3 is a side partial schematic view of a heat sink in accordance with an embodiment of the present invention;

FIG. 4 is a schematic view of a manufacturing process of a heat sink according to an embodiment of the present invention (the heat sink is not formed with a groove);

FIG. 5 is a schematic structural diagram of a power module according to an embodiment of the present invention;

FIG. 6 is a schematic view of a heat sink according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a semiconductor circuit according to an embodiment of the present invention;

FIG. 8 is a second schematic diagram of a semiconductor circuit according to an embodiment of the present invention;

FIG. 9 is an electrical topology of a semiconductor circuit of an embodiment of the present invention;

FIG. 10 is a flow chart illustrating a semiconductor circuit according to an embodiment of the present invention.

Reference numerals:

10. a heat sink; 11. a first surface; 12. a second surface; 121. a groove; 1211. a trench wall; 122. a planar portion; 13. a corner portion; 20. a power device; 21. a switching tube; 22. a freewheeling diode; 30. a driving chip; 40. a chip carrier; 42. a circuit wiring layer; 43. a pin; 50. an electrical connection; 60. welding flux; 70. a package body;

001. a semiconductor circuit; 002. a driving chip; 003. a first triode; 004. a second triode; 005. a third triode; 006. a fourth triode; 007. a fifth triode; 008. a sixth triode; 009. and a high-frequency filter capacitor.

Detailed Description

It is to be noted that the embodiments and features of the embodiments may be combined with each other without conflict in structure or function. The present invention will be described in detail below with reference to examples.

The semiconductor circuit provided by the utility model is a circuit module which integrates a power switch device, a high-voltage driving circuit and the like together and is sealed and packaged on the outer surface, and is widely applied to the field of power electronics, such as the fields of frequency converters of driving motors, various inversion voltages, variable frequency speed regulation, metallurgical machinery, electric traction, variable frequency household appliances and the like. The semiconductor circuit herein may be referred to by various other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuit, Power semiconductor Module, Power Module, etc. In the following embodiments of the present invention, it is referred to as IPM or semiconductor circuit.

The existing IPM products, especially for miniaturized and high-frequency products, have the problems of uneven heat dissipation, limited working performance, low reliability of the power device 20, and limited service life of the module product.

At present, in the related art, the heat sink 10 is added in the IPM, but since the heat sink 10 is soft, when the heat sink 10 is manufactured by stamping, when the stamping punch is pressed downwards, stress on each part of the pressed surface of the heat sink 10 is uneven, which causes several corners 13 of the heat sink 10 to warp, when the pressed surface forms a concave surface and the surface is uneven, and when the pressed surface of the heat sink 10 is welded and combined with a chip, the bonding is not facilitated, and the corners 13 of the heat sink 10 are easy to damage the chip. Therefore, when manufacturing an IPM product, the front and back sides of the heat sink 10 must be distinguished by a screening machine, and then the chip bonding is performed to bond the chip and the non-pressure side of the heat sink 10 by welding, which results in relatively complicated process steps and low production efficiency.

In the present invention, the solder 60 refers to a soldering material, and the solder 60 may be a solder or a solder paste.

The utility model provides a radiating fin 10 and a manufacturing method thereof, the radiating fin 10 manufactured by the manufacturing method is convenient for distinguishing the front side and the back side, and when the radiating fin is applied to IPM, the steps of an IPM manufacturing process can be simplified, and the production efficiency is improved; when the heat sink 10 is applied to IPM, the contact area between the heat sink 10 and the chip carrier 40 can be increased, and the thermal resistance can be reduced.

As shown in fig. 1 to 4, in an embodiment of the method for manufacturing the heat sink 10 of the present invention, the method for manufacturing the heat sink 10 includes:

a first preparation step: providing a metal substrate;

a second preparation step: providing a stamping die; the lower pressing surface of the die cavity of the selected stamping die is provided with a plurality of convex parts which are used for extruding a groove 121 on the pressed surface of the metal substrate;

a stamping step: the stamping die is used for stamping the metal substrate, and under the stamping action of the outer edge of the die cavity of the stamping die, the metal substrate is loaded at the edge of the die cavity and is broken so as to form an independent metal sheet in the die cavity; the convex part of the pressing surface presses the pressed surface of the metal sheet, the pressed surface of the metal surface deforms and forms a plurality of grooves 121, and the heat sink 10 with the plurality of grooves 121 on the second surface 12 is obtained.

The metal substrate is made of a heat conducting material with good heat conducting performance, and can be a copper sheet, an aluminum sheet, a copper-based metal sheet, an aluminum-based metal sheet, a metal sheet plated with copper on the surface, a metal sheet plated with silver on the surface and the like. Since the material of the metal base sheet is softer than that of the press mold, the groove 121 can be automatically formed in the heat sink 10 when the press mold with the convex portion is pressed down.

In an embodiment of the method for manufacturing the heat sink 10, the method for manufacturing the heat sink 10 further includes, before the second preparation step, a press-die processing method of: and processing the lower pressing surface of the die cavity of the stamping die by adopting a photoetching process or a chemical etching process so as to process a plurality of convex parts on the lower pressing surface.

In this embodiment, the regions of the pressing surface where the protrusions are not required to be formed are removed by photolithography or etching, and only the regions where the protrusions are required to be formed are remained, so that a plurality of protrusions can be formed on the pressing surface. In the embodiment, a method for removing materials at the non-convex part position of the pressing surface to form the convex part is adopted, so that the rigidity of the convex part is ensured, and the stamping forming effect of the convex part on the metal substrate is ensured. In addition, when the stamping die is processed, the non-convex part area of the pressing surface is removed to reversely form the convex part, so that the processing and implementation are more convenient.

In other embodiments, the protrusions may be formed by adding material to the pressing surface by welding or the like.

In an embodiment of the manufacturing method of the heat sink 10, in the press die processing method: processing the pressing surface to form a plurality of V-shaped convex parts;

in the pressing step, the V-shaped convex portion of the pressing surface presses the pressure-receiving surface of the heat sink 10, and a plurality of V-shaped grooves 121 are formed in the pressure-receiving surface of the heat sink 10.

As shown in fig. 1-4, in an embodiment of the heat sink 10 of the present invention, the heat sink 10 includes a first surface 11 and a second surface 12 opposite to the first surface 11, the first surface 11 is a plane, and the second surface 12 is provided with a plurality of grooves 121;

the heat sink 10 is adapted to be applied to a semiconductor circuit and is adapted to be arranged between a power device 20 and a chip carrier 40, the first surface 11 being adapted to face the power device 20 and the second surface 12 being adapted to face the chip carrier 40;

the first surface 11 is for solder bonding with the power device 20 and the second surface 12 is for solder bonding with the chip carrier 40.

In this embodiment, the second surface 12 is designed by using the groove 121, and the first surface 11 and the second surface 12 are completely different in two faces, so that the distinction is very easy.

The radiating fin 10 is formed by processing in a stamping mode, wherein the first surface 11 is a non-stamping surface, the second surface 12 is a compression surface, and the compression surface is a surface contacted when a stamping die of a stamping device punches downwards; when the heat sink 10 is processed, the non-stamping surface is located on the side away from the stamping die, the stamping surface faces the stamping die, and the stamping die contacts the second surface 12 to press the groove 121 on the second surface 12.

The heat sink 10 of the present embodiment has at least the following advantages when applied to a semiconductor circuit:

when the semiconductor circuit is manufactured, the first surface 11 and the second surface 12 are completely different, the groove 121 of the second surface 12 has obvious characteristics, the front and the back of the heat sink 10 (facing the power device 20 as the front surface and facing away from the power device 20 as the back surface) can be distinguished more easily, complex screening and confirming operations are not needed, the heat sink 10 can be directly used, the process steps are simplified, the production time is saved, and the production efficiency is improved.

The second surface 12 of the heat sink 10 is provided with a plurality of grooves 121, so that when the second surface 12 is welded to the chip carrier 40 by using soft solder 60 such as solder paste, the void ratio can be effectively controlled;

compared with the flat second surface 12, the second surface 12 with the grooves 121 increases the surface roughness, and the contact area of the second surface 12 and the solder 60 is increased; the surface roughness is increased, the bonding strength of the second surface 12 and the solder 60 is increased, and the welding between the heat sink 10 and the chip carrier 40 is firmer; the contact area between the second surface 12 of the heat sink 10 and the solder 60 is increased, which is equivalent to the increase of the contact area between the heat sink 10 and the chip carrier 40, so that the contact between the heat sink 10 and the mounting surface of the chip carrier 40 can be better ensured, the thermal resistance between the heat sink 10 and the chip carrier 40 can be effectively reduced, the heat generated by the power device 20 can be more quickly conducted from the heat sink 10 to the heat sink 10 and then conducted out from the chip carrier 40, and the heat dissipation efficiency is improved;

the first surface 11 is designed to be smooth, so that the problem that the height of the power device 20 welded to the same heat sink 10 is inconsistent and uneven due to the unevenness of the first surface 11, and the power device 20 with higher height is cracked by a wire Bonding head of a wire Bonding machine when a wire jumper is bound (Bonding) can be avoided; the heat sink 10 is configured such that the first surface 11 is a plane, and the first surface 11 is parallel to the second surface 12 in the area where no recess is formed, so that when the heat sink 10 is applied to a semiconductor circuit, the probability of damage to the power device 20 can be reduced, and the power device 20 can be protected;

the first surface 11 is a plane, and when the power device 20 is welded to the heat sink 10, the corner part 13 of the power device 20 is prevented from being tilted to damage the power device 20, and the defect rate is reduced.

In one embodiment of the heat sink 10 of the present invention, as shown in fig. 3, the groove 121 is a V-shaped groove, the groove 121 includes two groove walls 1211, the two groove walls 1211 are connected at an end of the groove 121 close to the first surface 11 and form a tip, and the two groove walls 1211 are inclined, so as to provide a flow guide for the molten solder 60, facilitate the discharge of air bubbles in the molten solder 60, and reduce the void ratio in the solder 60.

Wherein, the end of the V-shaped groove can also be provided with a certain arc chamfer.

It should be noted that the included angle between the two groove walls 1211 of the V-shaped groove is not limited to an acute angle, and may be a right angle or an obtuse angle, as long as the two groove walls 1211 are joined at the end of the groove 121 close to the first surface 11, and the inclination directions of the two groove walls 1211 are opposite.

In other embodiments, the groove 121 may be a U-shaped groove.

In an embodiment of the heat sink 10 of the present invention, the plurality of grooves 121 are arranged at intervals on the second surface 12, that is, the second surface 12 includes planar portions 122 and the grooves 121, adjacent grooves 121 are connected by the planar portions 122, and the second surface 12 is configured as: the plane portion 122, the groove 121, and the plane portion 122 … … are arranged in this order.

The planar portions 122 are disposed between adjacent grooves 121 on the second surface 12 to prevent the grooves 121 from being connected to each other to form a tip, thereby preventing damage to the circuit wiring layer 42 on the chip carrier 40.

In an embodiment of the heat sink 10 of the present invention, the groove 121 penetrates the heat sink 10 in a length direction thereof, and forms groove openings at opposite ends of the heat sink 10, respectively; with such an arrangement, when the heat sink 10 is soldered to the chip carrier 40 by using the solder 60, the soft solder 60 can flow and reflow conveniently through the groove openings communicating at the two ends, air bubbles in the solder 60 can be removed through the groove openings at the two ends, the void ratio can be reduced, the effective combination of the heat sink 10 and the solder 60 can be ensured, and the thermal resistance between the heat sink 10 and the chip carrier 40 can be reduced.

In this embodiment, the groove walls 1211 on opposite sides of the groove 121 form an included angle, the groove walls 1211 on both sides also form an included angle at the opening of the groove, and the included angle is α, α is greater than or equal to 70 ° and less than or equal to 110 °. When the included angle is too small, it is not favorable for the solder 60 to be efficiently bonded to the heat sink 10, and when the included angle is too large, it is not favorable for clearly and directly distinguishing the first surface 11 from the second surface 12.

In the present embodiment, α is 90 °.

In other embodiments, α may also be 80 °, 100 °, 85 °, 95 °, etc.

In an embodiment of the heat sink 10 of the present invention, the grooves 121 are parallel to each other for easy manufacturing.

In this embodiment, each of the grooves 121 extends along a first direction, and the plurality of grooves 121 are arranged along a second direction.

In the present embodiment, the first direction is the width direction of the heat sink 10, and the second direction is the length direction of the heat sink 10.

Compared with the technical scheme that the first direction is the length direction of the heat sink 10, the technical scheme of the embodiment has the advantages that the length of the groove 121 is shorter, so that the solder 60 can flow more conveniently, bubbles in the solder 60 can be eliminated, and the void ratio can be reduced; moreover, more grooves 121 may be disposed at intervals on the second surface 12 of the heat spreader 10, so as to increase the contact area between the heat spreader 10 and the chip carrier 40, improve the heat dissipation performance, and facilitate the processing of the heat spreader 10.

In other embodiments, each of the grooves 121 may also extend along the length direction of the heat sink 10, and a plurality of the grooves 121 are arranged along the width direction of the heat sink 10.

In an embodiment of the heat sink 10 of the present invention, the length of the heat sink 10 is R, R is greater than or equal to 4mm and less than or equal to 11 mm;

the width of the radiating fin 10 is Y, and Y is more than or equal to 2mm and less than or equal to 8 mm;

the corner part 13 of the radiating fin 10 is provided with a chamfer angle, the angle of the chamfer angle is K, and K is more than or equal to 2 degrees and less than or equal to 6 degrees;

the thickness of the radiating fin 10 is H, and H is more than or equal to 0.5mm and less than or equal to 1.5 mm.

The corner part 13 of the heat sink 10 is designed with a chamfer, so that EMI signals generated at the right-angle tip of the corner part 13 of the heat sink 10 can be prevented from interfering a semiconductor circuit, and the soldering process is easier to solder and poor soldering can be avoided.

As shown in fig. 1 to 9, the present invention further provides a semiconductor circuit, which includes a chip carrier 40, the heat sink 10 in the above-mentioned embodiment, and electronic components, including a power device 20 and a driving chip 30;

the electronic component is arranged on the mounting surface of the chip carrier 40;

the power device 20 comprises a switching tube 21 and a freewheeling diode 22;

a heat sink 10 is arranged between the power device 20 and the chip carrier 40, a first surface 11 of the heat sink 10 faces the power device 20, a second surface 12 faces the chip carrier 40, the second surface 12 is welded and combined with the chip carrier 40 through a solder 60, and the power device 20 is welded and combined with the first surface 11 through the solder 60;

the driving chip 30 is electrically connected to the power device 20.

In one embodiment, as shown in fig. 7, the semiconductor circuit includes a plurality of sets of power components, each of which includes a heat sink 10, and a switch tube 21 and a freewheel diode 22 soldered to the first surface 11 of the heat sink 10, the switch tube 21 is electrically connected to the freewheel diode 22 via an electrical connector 50, and the switch tube 21 is electrically connected to the driver chip 30 via the electrical connector 50, as shown in fig. 6;

the power component is soldered to the chip carrier 40 through the second surface 12 of the heat sink 10.

The electrical connector 50 may be a bonding wire, a conductive metal bridge, or the like.

In a specific implementation of this embodiment:

the switch tube 21 is an IGBT (Insulated Gate Bipolar Transistor), and the freewheeling diode 22 is an FWD diode;

in each power module: the IGBT triode is soldered to the first surface 11 of the heat sink 10 by solder paste, and the FWD diode is soldered to the first surface 11 of the heat sink 10 by solder paste, thus completing the processing of the power module;

then, the plurality of power components are respectively soldered to the chip carrier 40 by solder paste, and when the power components are soldered, the second surface 12 of the heat sink 10 is bonded to the chip carrier 40 by solder paste.

In this embodiment, the chip carrier 40 is a substrate PCB.

In other embodiments, the switch tube 21 may also be a Metal Oxide Semiconductor (MOS) tube.

In one embodiment, the components are soldered by disposing solder material such as solder paste between the components, and soldering is performed in a high temperature environment, and the solder 60 is cured to complete the soldering.

In an embodiment of the semiconductor circuit of the present invention, the power device 20 includes a switching tube 21 and a freewheeling diode 22;

the semiconductor circuit comprises a plurality of groups of power components, each group of power components comprises a radiating fin 10, a switch tube 21 and a freewheeling diode 22, the switch tube 21 is electrically connected with the freewheeling diode 22 through an electric connector 50, and the switch tube 21 is electrically connected with a driving chip 30 through the electric connector 50;

power devices 20 within the same power assembly are soldered to the same heat sink 10.

In an embodiment of the semiconductor circuit of the present invention, chip carrier 40 includes a base, pins 43, a circuit wiring layer 42, and pads; the substrate comprises a mounting surface, a circuit wiring layer 42 is arranged on the mounting surface, and a bonding pad is arranged on the circuit wiring layer 42;

the second surface 12 of the heat sink 10 is soldered to the pad by a solder material;

the power device 20 is electrically connected to the circuit wiring layer 42 or the pin 43 through the electrical connector 50;

the semiconductor circuit further includes a package 70, the package 70 enclosing the chip carrier 40, the heat sink 10, the power device 20 and the driver chip 30, at least a portion of the leads 43 being exposed by the package 70;

the heat sink 10 is a copper-based heat sink 10 or an aluminum-based heat sink 10;

the chip carrier 40 is an IMS substrate, a DBC frame, a CIS frame, or the like.

In an embodiment of the semiconductor circuit 001 of the present invention, referring to fig. 9, an electrical topology diagram of the semiconductor circuit 001 is provided:

the semiconductor circuit 001 includes a drive circuit and an inverter unit, and the inverter unit includes an inverter circuit;

the driving circuit comprises a driving chip 002, and the driving chip 002 can be but not limited to an HVIC chip;

the inverter circuit comprises an upper bridge arm triode switch tube and a lower bridge arm triode; the triode can be but is not limited to an IGBT tube and an MOS tube;

the source electrode of the upper bridge arm triode is electrically connected with the drain electrode of the lower bridge arm triode,

the source electrode of the lower bridge arm triode is electrically connected with the pin;

the grid electrode of the upper bridge arm triode and the grid electrode of the lower bridge arm triode are both electrically connected with the driving chip 002.

Specifically, as shown in fig. 9, in the present embodiment, the inverter unit includes three inverter circuits, which are a first inverter circuit, a second inverter circuit and a third inverter circuit respectively; wherein the content of the first and second substances,

the first inverter circuit includes a first transistor 003 and a second transistor 004,

the second inverter circuit includes a third transistor 005 and a fourth transistor 006,

the third inverter circuit includes a fifth transistor 007 and a sixth transistor 008;

the first triode 003, the third triode 005 and the fifth triode 007 are all upper bridge arm triodes, and the second triode 004, the fourth triode 006 and the sixth triode 008 are all lower bridge arm triodes;

the drain electrode of the first triode 003 is electrically connected with the high-voltage input end P;

the source electrode of the first triode 003 is electrically connected with the drain electrode of the second triode 004, the source electrode of the third triode 005 is electrically connected with the drain electrode of the fourth triode 006, and the source electrode of the fifth triode 007 is electrically connected with the drain electrode of the sixth triode 008;

the source of the second triode 004 is electrically connected with the pin UN of the outer pin, the source of the fourth triode 006 is electrically connected with the pin VN of the outer pin, and the source of the sixth triode 008 is electrically connected with the pin WN of the outer pin.

As shown in fig. 9, the driving circuit further includes a high-frequency filter capacitor 009, and the high-frequency filter capacitor 009 is connected to VCC and COM, is located as close as possible to the output terminal of the driving chip 002, and functions to filter out a high-frequency signal.

As shown in fig. 10, 6, and 8, the present invention also provides a method for manufacturing a semiconductor circuit, including:

the feeding step of the radiating fins 10: placing the first surface 11 of the heat sink 10 in the above scheme in the tool with the first surface 11 of the heat sink 10 facing upwards;

and (5) solder 60 applying step: providing soft solder material to the first surface 11;

feeding the power device 20: sucking the power chip onto the soft soldering material;

a welding step: at the welding temperature, the power chip is combined with the radiating fin 10 through a soft welding material to obtain a power assembly;

a plate loading step: a chip carrier 40 is provided, and the heat sink 10 of the power module is soldered to the chip carrier 40 in a downward direction.

In an embodiment of a semiconductor circuit, the semiconductor circuit is fabricated by:

heat sink 10 IQC: when the heat dissipation fins 10 are fed, feeding inspection is performed, and after no batch defects are confirmed, the on-line production is carried out.

Tin coating of the heat sink 10: placing the tool with the confirmed radiating fins 10 on a production track for high-temperature wire welding;

the power device 20 is moved to the heat sink 10: sucking the power device 20 onto the solder of the heat sink 10 by a chip light irradiation apparatus (DA);

soldering patch welding: soft Solder 60 patch welding (Soft Solder Die Attach), abbreviated as SSD, is a process in which two different metals form an alloy at a temperature well below their respective melting points in a certain weight ratio; the soldering combination of the heat sink 10 and the power device 20 is realized by the eutectic soldering, which is a process of melting solder wires on the surface of the heat sink 10 uniformly at high temperature and then soldering the power device 20 to form a finished heat sink 10;

and (3) power component finished product: after the SSD is passed, the welding of the power assembly is completed;

warehousing: and placing the welded radiating fin 10 assembly in a tooling material box, waiting for the next SMT link, attaching the power assembly on a chip carrier 40, wherein the chip carrier 40 is a substrate or a frame, and then reflowing and reinforcing.

In the prior art, after the step of IQC of the heat sink 10, the method comprises the steps of screening before feeding: after the incoming material inspection is finished, the radiating fins 10 are poured onto screening equipment, the front side and the back side of the radiating fins are screened and confirmed through an automatic AOI screening machine, and then the radiating fins are sucked onto a tooling material box of the radiating fins 10 to be soldered; the step is a process step of the original scheme, and AOI screening and confirmation are not needed in the scheme.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the utility model and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the utility model.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A heat sink for a semiconductor circuit, comprising opposing first and second surfaces; the first surface is used for welding combination with a power device; the second surface is provided with a plurality of grooves and is used for being welded and combined with the chip carrier.

2. A heat sink as recited in claim 1, wherein the first surface is planar.

3. The heat sink of claim 1, wherein the groove is a V-groove.

4. The heat sink as recited in claim 1, wherein a plurality of the grooves are spaced apart from each other on the second surface.

5. A heat sink according to any one of claims 1-4, wherein the groove extends through the heat sink in a first direction and forms a groove opening at each of opposite ends of the heat sink; an included angle is formed between the groove walls on the two opposite sides of the groove, the included angle is alpha, and the alpha is more than or equal to 70 degrees and less than or equal to 110 degrees.

6. The fin according to any one of claims 1 to 4, wherein each of the grooves extends in a first direction, and a plurality of the grooves are arranged in a second direction;

7. A heat sink as claimed in claim 6, wherein the length of the heat sink is R, 4mm ≦ R ≦ 11 mm;

8. A semiconductor circuit, comprising:

a chip carrier;

the heat sink as claimed in any one of claims 1-7, wherein a second surface of the heat sink is soldered to the chip carrier by a solder material;

9. The semiconductor circuit according to claim 8, wherein the power device comprises a switching tube and a freewheeling diode;

10. The semiconductor circuit of claim 8, wherein the chip carrier comprises a base, a pin, a circuit wiring layer, and a pad; the substrate comprises a mounting surface, the circuit wiring layer is arranged on the mounting surface, and the bonding pad is arranged on the circuit wiring layer;

the chip carrier is an IMS substrate, or a DBC frame, or a CIS frame.