CN215729853U - Quantum chip and quantum computer - Google Patents
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- CN215729853U CN215729853U CN202122267316.5U CN202122267316U CN215729853U CN 215729853 U CN215729853 U CN 215729853U CN 202122267316 U CN202122267316 U CN 202122267316U CN 215729853 U CN215729853 U CN 215729853U
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Abstract
The application discloses quantum chip and quantum computer belongs to the quantum information field. The quantum chip comprises a plurality of quantum bits, wherein each quantum bit comprises a first capacitor plate and a first superconducting quantum interference device, the first capacitor plate is connected to the ground, one end of each first superconducting quantum interference device is connected with the first capacitor plate, and the other end of each first superconducting quantum interference device is connected with the ground; the first capacitor plate comprises a plurality of electrodes with the same intersection, the quantum bits at adjacent positions form coupling connection through one of the electrodes, and the first capacitor plate comprises a plurality of electrodes.
Description
Technical Field
The application belongs to the field of quantum information, particularly relates to the technical field of quantum computing, and particularly relates to a quantum chip and a quantum computer.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. The quantum computer is characterized by high running speed, strong information processing capability, wide application range and the like. Compared with a common computer, the more information processing amount is, the more beneficial the quantum computer to implement operation is, and the more accurate the operation can be ensured.
The superconducting quantum computing can prepare quantum bits on a substrate by utilizing a micro-nano processing technology, and has superior performances of integration, expandability and the like. In recent years, superconducting quantum computation is rapidly developed, a single capacitor to the ground and a superconducting quantum interference device with one end grounded and the other end connected with the capacitor are commonly adopted in the structure of the current qubit, the qubit of the structure is convenient for one-dimensional chain arrangement, the qubits at adjacent positions in the one-dimensional chain arrangement are coupled and connected through the capacitor, the qubits are arranged on a quantum chip in a one-dimensional chain manner, each qubit is only coupled with two adjacent qubits on the left and right, the connectivity between the qubits is not good, and the structure has certain limitation.
Summary of the invention
Aiming at the problem of poor connectivity among the qubits on the quantum chip in the prior art, the application provides the quantum chip and the quantum computer to solve the defects in the prior art, and the quantum chip and the quantum computer enable the number of the qubits of one qubit to establish coupling connection through the electrode of the first capacitor plate to be increased, so that the connectivity among the qubits on the quantum chip is improved.
One aspect of the present application provides a quantum chip, including:
a plurality of qubits including a first capacitive plate to ground and a first superconducting quantum interference device having one end connected to the first capacitive plate and another end connected to ground;
wherein the first capacitive plate comprises a plurality of electrodes having the same intersection, and the qubits in adjacent positions form a coupling connection via one of the plurality of electrodes.
In some embodiments of the present application, one end of the first superconducting quantum interference device is connected to the junction.
In some embodiments of the present application, the shape configuration of a plurality of the electrodes is the same.
In some embodiments of the present application, the first capacitive plate includes a first electrode, a second electrode, and a third electrode having a same intersection, or includes a first electrode, a second electrode, a third electrode, and a fourth electrode having a same intersection.
In some embodiments of the present application, the first superconducting quantum interference device comprises josephson junctions connected in parallel with each other, the josephson junctions being tunnel junctions, point junctions, or other structures exhibiting josephson effect.
In some embodiments of the present application, a coupling structure is further formed between two of the qubits in adjacent positions, the coupling structure being coupled to one of the plurality of electrodes of one of the qubits and to each of the plurality of electrodes of adjacent ones of the qubits.
In some embodiments of the present application, the coupling structure is tunable in frequency.
In some embodiments of the present application, the coupling structure includes a second capacitive plate to ground, a second superconducting quantum interference device connected at one end to the second capacitive plate and at another end to ground, and a flux adjustment line coupled to the second superconducting quantum interference device.
In some embodiments of the present application, the second capacitive plate includes a first portion, a second portion, and a third portion connecting the first portion and the second portion, and one of the plurality of electrodes of one qubit and one of the plurality of electrodes adjacent to the qubit are located on either side of the third portion and are both located between the first portion and the second portion.
Another aspect of the present application provides a quantum computer provided with at least a quantum chip as described above, and a manipulation and reading device connected to the quantum chip.
Compared with the prior art, the quantum chip provided by the application comprises a plurality of quantum bits, wherein each quantum bit comprises a first capacitor plate and a first superconducting quantum interference device, the first capacitor plate is connected to the ground, and one end of each first superconducting quantum interference device is connected with the first capacitor plate, and the other end of each first superconducting quantum interference device is connected with the ground; the first capacitor plate comprises a plurality of electrodes with the same intersection, the quantum bits at adjacent positions form coupling connection through one of the electrodes, and the number of the electrodes of the first capacitor plate is expanded, so that the number of the quantum bits of which one quantum bit establishes coupling connection through the electrode of the first capacitor plate is increased, the connectivity among the quantum bits on the quantum chip is improved, and the limitation caused by the structure in the prior art is overcome.
Drawings
FIG. 1 is a diagram illustrating a structure of a qubit on a quantum chip in the prior art;
FIG. 2 is a schematic structural diagram of a quantum chip provided in the present application;
fig. 3 is a schematic structural diagram of a qubit provided in the present application;
fig. 4 is a schematic structural diagram of another quantum chip provided in the present application;
FIG. 5 is a schematic diagram of another qubit structure provided in the present application;
fig. 6 is a schematic diagram of a coupling structure provided in the present application.
Description of reference numerals:
1-qubit, 2-coupling structure, 3-read resonator,
11-a first capacitive plate, 12-a first superconducting quantum interference device,
111-first electrode, 112-second electrode, 113-third electrode, 114-third electrode, 121-first josephson junction,
21-second capacitive plate, 22-second superconducting quantum interference device
211-first section, 212-second section, 213-third section, 221-second josephson junction.
Detailed Description
The following detailed description is merely illustrative and is not intended to limit the embodiments and/or the application or uses of the embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding "background" or "summary" sections or "detailed description" sections.
To further clarify the objects, aspects and advantages of embodiments of the present application, one or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced without these specific details in various instances, and that the various embodiments are incorporated by reference into each other without departing from the scope of the present disclosure.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In addition, it will be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and/or pattern, it can be directly on the other layer or substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" layers may be made based on the drawings.
According to different physical systems adopted for constructing the qubits, the qubits include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quanta, photons and the like in a physical implementation manner.
Superconducting quantum computing is the best solid quantum computing implementation method which is developed at present. Because the energy level structure of the superconducting quantum circuit can be regulated and controlled by an external electromagnetic signal, the controllability of the design customization of the circuit is strong. Meanwhile, the superconducting quantum circuit has the scalability which is incomparable with most quantum physical systems due to the existing mature integrated circuit technology. Currently, the structure of qubit usually employs a single capacitor to ground and a superconducting quantum interference device with one end grounded and the other end connected to the capacitor, and the capacitor is usually a cross-shaped parallel plate capacitor, as shown in fig. 1, a cross-shaped capacitor plate CqSurrounded by ground plane (GND), and cross-shaped capacitor plate CqA gap is arranged between the superconducting quantum interference device and a ground plane (GND), and one end of the superconducting quantum interference device is connected to the cross-shaped capacitor plate CqAnd the other end is connected to the ground plane (GND) due to the cross-shaped capacitor plate CqThe first end of the first dielectric layer is generally used for connecting a superconducting quantum interference device (squid), the second end of the first dielectric layer is used for coupling with the reading resonant cavity, certain space needs to be reserved near the first end and the second end for wiring, for example, space needs to be reserved near the first end for arranging xy signal lines and z signal lines, and a cross-shaped capacitor plate CqThe other two ends of the structure are used for being coupled with adjacent quantum bits, the quantum bits of the structure are convenient for one-dimensional chain arrangement, but the quantum bits which are in one-dimensional chain arrangement on the quantum chip are only coupled with two adjacent quantum bits on the left and right, the connectivity between the quantum bits is not good, and the structure has certain limitation.
Therefore, the quantum chip, the preparation method thereof and the quantum computer are provided in the application, so as to solve the defects in the prior art, the quantum bit structure is convenient for the array arrangement of the quantum bits, the quantum bits at the adjacent positions in the array arrangement of the quantum bits can form coupling, namely, any quantum bit can be coupled with a plurality of adjacent quantum bits to realize communication, and the expansion of the quantum bit number is realized.
Fig. 2 is a schematic structural diagram of a quantum chip provided in the present application.
Fig. 3 is a schematic structural diagram of a qubit provided in the present application.
Fig. 4 is a schematic structural diagram of another quantum chip provided in the present application.
Fig. 5 is a schematic structural diagram of another qubit provided in the present application.
Fig. 6 is a schematic diagram of a coupling structure provided in the present application.
Referring to fig. 2 to 6, one aspect of the present application provides a quantum chip, which includes:
a plurality of qubits 1, the qubits 1 comprising a first capacitive plate 11 to ground and a first superconducting quantum interference device 12 connected at one end to the first capacitive plate 11 and at another end to ground;
wherein the first capacitor plate 11 comprises a plurality of electrodes having the same intersection, and the qubits 1 in adjacent positions form a coupling connection via one of the plurality of electrodes.
In the embodiments provided herein, the ground may be a ground plane (GND) formed on the substrate, the qubit 1 is an electrical structure formed on the substrate, the first capacitive plate 11 includes a plurality of electrodes, and illustratively, the first capacitive plate 11 includes at least 3 electrodes having the same intersection, and this structure improves connectivity between the qubits on the quantum chip by extending the number of electrodes of the first capacitive plate 11, so that the number of qubits for establishing coupling connection between one qubit 1 and the electrodes of the first capacitive plate 11 is increased.
In some embodiments of the present application, one end of the first superconducting quantum interference device 12 is connected to the junction.
In some embodiments of the present application, the shape of the plurality of electrodes is configured identically, i.e. the physical structure of the plurality of electrodes is identical, such as the thickness of the electrodes on the substrate, the critical dimension, etc.
In some embodiments of the present application, the first capacitor plate 11 includes the first electrode 111, the second electrode 112 and the third electrode 113 having the same intersection, or the first capacitor plate 11 includes the first electrode 111, the second electrode 112, the third electrode 113 and the fourth electrode 114 having the same intersection, it is understood that the plurality of electrodes having the same intersection means that the plurality of electrodes of the first capacitor plate 11 converge at the same position.
In some embodiments of the present application, the first superconducting quantum interference devices 12 include josephson junctions connected in parallel with each other, for example, each of the first superconducting quantum interference devices 12 includes two first josephson junctions 121, and the first josephson junctions 121 may be tunnel junctions, point junctions, or other structures exhibiting josephson effect.
In some embodiments of the present application, a coupling structure 2 is further formed between two qubits 1 in adjacent positions, wherein the coupling structure 2 is coupled to one of the electrodes of one of the qubits 1 and to each of the electrodes of a plurality of adjacent qubits 1. In some embodiments, the coupling structure 2 may adopt a capacitor, a resonant cavity, or the like, or may adopt a frequency tunable coupling structure, for example, as shown in fig. 6, the frequency tunable coupling structure includes a second capacitor plate 21 and a second superconducting quantum interference device 22, one end of the second superconducting quantum interference device 22 is connected to the second capacitor plate 21, and the other end is connected to the ground plane (GND), thereby a capacitance to ground is formed between the second capacitor plate 21 and the ground plane (GND), the capacitance to ground is connected in parallel with the second superconducting quantum interference device 22, the second superconducting quantum interference device 22 is a superconducting ring structure composed of josephson junctions, and for example, the second superconducting quantum interference device 22 includes two second josephson junctions 221 connected in parallel. By adopting the coupling structure 2 in the form, the coupling strength between the adjacent quantum bits 1 can be conveniently regulated and controlled, and the execution of the double-quantum logic gate on a quantum chip can be conveniently realized. In some embodiments, the superconducting loop structure comprises at least three second josephson junctions 221, wherein two josephson junctions are connected in parallel to form a loop structure, and then the loop structure is connected in parallel with another josephson junction. The embodiment of the present application can change the frequency of the coupling structure 2 by changing the magnetic field generated by the current flowing through the josephson junction, so as to realize the indirect coupling of the qubits 1 at adjacent positions in the qubit array arrangement, and at the same time, facilitate the control of the coupling strength between the qubits 1 by using the coupling structure 2, and adjust the frequency of the coupling structure 2 by applying magnetic flux, for example, the magnetic flux of the second superconducting quantum interference device 22 can be adjusted by the magnetic flux adjusting line coupled with the second superconducting quantum interference device 22 to realize the frequency control of the coupling structure 2, that is, in some embodiments of the present application, the coupling structure 2 includes a second capacitive plate 21 to ground, a second superconducting quantum interference device 22 with one end connected with the second capacitive plate 21 and the other end connected with the ground, and a flux-modulating wire coupled to the second superconducting quantum interference device 22.
In some embodiments of the present application, the second capacitor plate 21 includes a first portion 211, a second portion 212, and a third portion 213 connecting the first portion 211 and the second portion 212, and one of the plurality of electrodes of one qubit and one of the plurality of electrodes adjacent to the qubit are located on both sides of the third portion 213 and between the first portion 211 and the second portion 212. Illustratively, one of the first electrode 111, the second electrode 112, and the third electrode 113 of one qubit 1 and one of the first electrode 111, the second electrode 112, and the third electrode 113 of an adjacent qubit 1 are respectively located on both sides of the third section 213 and are both located between the first section 211 and the second section 212.
Based on the quantum chip provided by the embodiment of the present application, the first capacitor plate 11, the second capacitor plate 21, the first superconducting quantum interference device 12, the second superconducting quantum interference device 22, and the ground plane (GND) may be formed on a substrate, qubits arranged in an array may be surrounded by the ground plane (GND), and the first capacitor plate 11 and the second capacitor plate 21 may be separated from the ground plane (GND) by a gap exposing a surface of the substrate. In the embodiment of the present application, the substrate may be a dielectric substrate such as silicon or sapphire, and in the embodiment of the present application, the qubit 1, the coupling structure 2, and the ground plane (GND) are formed on the silicon substrate. The first capacitor plate 11, the second capacitor plate 21, and the ground plane (GND) may be formed of a superconductor material exhibiting superconducting characteristics at a temperature equal to or lower than a critical temperature, for example, aluminum, niobium, titanium nitride, or the like, and the specific implementation is not limited thereto, and materials exhibiting superconducting characteristics at a temperature equal to or lower than a critical temperature may be used to form the first capacitor plate 11, the second capacitor plate 21, and the ground plane (GND).
In order to manufacture the quantum chip in the embodiment of the present application, the qubits 1 arranged in an array on the substrate require a plurality of layers to form the first and second superconducting quantum interference devices 12 and 22, in some embodiments, each of the first and second superconducting quantum interference devices 12 and 22 includes two josephson junctions connected in parallel, each of the josephson junctions is a laminated structure of a superconducting layer-an insulating layer-a superconducting layer, a first layer of superconductor material may be deposited to form a first superconducting layer of the josephson junction, and then oxidized at a partial region of the first superconducting layer to form an insulating layer, and a second layer of superconductor material may be deposited to form a second superconducting layer of the josephson junction, thereby obtaining a laminated structure of superconducting layer-insulating layer-superconducting layer. For example, in order to conveniently and synchronously prepare a plurality of josephson junctions on the quantum chip and reduce the process difficulty, the josephson junctions on the quantum chip are all of the homodromous structure, that is, the extending directions of the first superconducting layer, the insulating layer and the second superconducting layer of the plurality of josephson junctions are correspondingly the same, and the stacking sequence of the first superconducting layer, the insulating layer and the second superconducting layer of the plurality of josephson junctions is also the same.
In order to maximize the space reserved on the substrate to meet the requirement of wiring (structures such as a read resonant cavity and a control signal line), in some embodiments of the present application, one end of the first superconducting quantum interference device 12 is connected to the intersection of the electrodes of the first capacitor plate 11, and the other end is connected to a ground plane (GND).
In some embodiments of the present application, a reading resonant cavity 3 and a regulation signal line coupled to the qubit 1 are further formed on the substrate, and the regulation signal line includes a pulse regulation line and a first magnetic flux regulation line.
Another aspect of the present application provides a quantum computer provided with at least a quantum chip as described above, and a manipulation and reading device connected to the quantum chip.
The control and reading device adjusts the frequency of the qubit 1 to the working frequency by using the magnetic flux regulation and control signal on the first magnetic flux regulation line, at the moment, the quantum state regulation and control signal is applied through the pulse modulation line to carry out quantum state regulation and control on the qubit 1 in the initial state, and the reading resonant cavity 3 is adopted to read the quantum state of the regulated qubit 1. The steering and reading device determines the quantum state in which the qubit is located by interpreting a read feedback signal (a signal responsive to the read probe signal) output via a read signal transmission line by applying a read probe signal (e.g., a microwave signal having a frequency of 4-8 GHz) to the read signal transmission line coupled to the read resonant cavity 3.
Here, it should be noted that: the quantum chip in the quantum computer is similar to the structure and has the same beneficial effects as the quantum chip embodiment, and therefore, the description is omitted. For technical details that are not disclosed in the quantum computer embodiments of the present application, those skilled in the art should refer to the description of the quantum chip above for understanding, and for the sake of brevity, detailed description is omitted here.
The embodiment of the application also provides a preparation method of the quantum chip, the quantum chip comprises a plurality of quantum bits, and the preparation method comprises the following steps:
forming a first capacitor plate 11 of each qubit 1 on a substrate, wherein the first capacitor plate 11 comprises a plurality of electrodes with the same intersection, in this embodiment, the first capacitor plate 11 comprises at least 3 electrodes with the same intersection, and the qubits 1 in adjacent positions form a coupling connection through one of the plurality of electrodes; and
forming a first superconducting quantum interference device 12 on the substrate, wherein one end of the superconducting quantum interference device 12 is connected to the first capacitor plate 11, and the other end is connected to ground. Illustratively, one end of the first superconducting quantum interference device 12 is connected to the junction. Illustratively, the first capacitor plate 11 includes a first electrode 111, a second electrode 112, and a third electrode 113 having the same intersection, or includes a first electrode 111, a second electrode 112, a third electrode 113, and a fourth electrode 114 having the same intersection, and each of the electrodes has the same shape configuration.
Fabrication of a quantum chip provided by embodiments of the present application may require deposition of one or more materials, such as superconductors, dielectrics, and/or metals. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among others. A fabrication process for a quantum chip as described in embodiments herein may require removal of one or more materials from the device during the fabrication process. Depending on the material to be removed, the removal process may include, for example, a wet etching technique, a dry etching technique, or a lift-off (lift-off) process. The materials forming the circuit elements described herein may be patterned using known exposure (lithographical) techniques, such as photolithography or electron beam exposure.
The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.
Claims (10)
1. A quantum chip, comprising:
a plurality of qubits including a first capacitive plate to ground and a first superconducting quantum interference device having one end connected to the first capacitive plate and another end connected to ground;
wherein the first capacitive plate comprises a plurality of electrodes having the same intersection, and the qubits in adjacent positions form a coupling connection via one of the plurality of electrodes.
2. The quantum chip of claim 1, wherein an end of the first superconducting quantum interference device is connected to the junction.
3. The quantum chip of claim 1, wherein the electrodes are identically configured.
4. The quantum chip of any of claims 1-3, wherein the first capacitive plate comprises a first electrode, a second electrode, and a third electrode having the same intersection, or comprises a first electrode, a second electrode, a third electrode, and a fourth electrode having the same intersection.
5. The quantum chip of claim 4, wherein the first superconducting quantum interference device comprises Josephson junctions connected in parallel with each other, the Josephson junctions being tunnel junctions, point junctions, or other structures exhibiting Josephson effects.
6. The quantum chip of claim 1, wherein a coupling structure is further formed between two of the qubits in adjacent positions, the coupling structure being coupled to one of the plurality of electrodes of one of the qubits and to each of the plurality of electrodes of adjacent ones of the qubits.
7. The quantum chip of claim 6, wherein the frequency of the coupling structure is tunable.
8. The quantum chip of claim 7, wherein the coupling structure comprises a second capacitive plate to ground, a second superconducting quantum interference device connected at one end to the second capacitive plate and at another end to ground, and a flux adjustment line coupled to the second superconducting quantum interference device.
9. The quantum chip of claim 8, wherein the second capacitive plate comprises a first portion, a second portion, and a third portion connecting the first portion and the second portion,
and one of the plurality of electrodes of one said qubit and one of the plurality of electrodes of an adjacent said qubit are located on either side of the third section and are both located between the first section and the second section.
10. Quantum computer, characterized in that it is provided with at least a quantum chip according to claims 1-9, and a manipulation and reading device connected to the quantum chip.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202122267316.5U CN215729853U (en) | 2021-09-17 | 2021-09-17 | Quantum chip and quantum computer |
| PCT/CN2022/108653 WO2023006041A1 (en) | 2021-07-30 | 2022-07-28 | Quantum circuit, quantum chip, and quantum computer |
| EP22848646.0A EP4328809A1 (en) | 2021-07-30 | 2022-07-28 | Quantum circuit, quantum chip, and quantum computer |
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| CN202122267316.5U CN215729853U (en) | 2021-09-17 | 2021-09-17 | Quantum chip and quantum computer |
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| CN114819164A (en) * | 2022-04-12 | 2022-07-29 | 北京百度网讯科技有限公司 | Quantum chip structure, determination method, device, equipment and storage medium |
| CN115438795A (en) * | 2022-09-30 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Quantum chip and quantum computer |
| CN115438794A (en) * | 2022-09-30 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Quantum calculation circuit and quantum computer |
| WO2023006041A1 (en) * | 2021-07-30 | 2023-02-02 | 合肥本源量子计算科技有限责任公司 | Quantum circuit, quantum chip, and quantum computer |
| WO2024045930A1 (en) * | 2022-08-31 | 2024-03-07 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip and quantum computer |
| WO2024066730A1 (en) * | 2022-09-30 | 2024-04-04 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip, quantum computing circuit and quantum computer |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023006041A1 (en) * | 2021-07-30 | 2023-02-02 | 合肥本源量子计算科技有限责任公司 | Quantum circuit, quantum chip, and quantum computer |
| CN114819164A (en) * | 2022-04-12 | 2022-07-29 | 北京百度网讯科技有限公司 | Quantum chip structure, determination method, device, equipment and storage medium |
| CN114819164B (en) * | 2022-04-12 | 2023-09-01 | 北京百度网讯科技有限公司 | Quantum chip structure, determination method, device, equipment and storage medium |
| WO2024045930A1 (en) * | 2022-08-31 | 2024-03-07 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip and quantum computer |
| CN115438795A (en) * | 2022-09-30 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Quantum chip and quantum computer |
| CN115438794A (en) * | 2022-09-30 | 2022-12-06 | 合肥本源量子计算科技有限责任公司 | Quantum calculation circuit and quantum computer |
| CN115438795B (en) * | 2022-09-30 | 2023-08-08 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip and quantum computer |
| CN115438794B (en) * | 2022-09-30 | 2023-09-05 | 本源量子计算科技（合肥）股份有限公司 | Quantum computing circuit and quantum computer |
| WO2024066730A1 (en) * | 2022-09-30 | 2024-04-04 | 本源量子计算科技（合肥）股份有限公司 | Quantum chip, quantum computing circuit and quantum computer |
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