CN216286751U - Superconducting quantum chip and quantum computer - Google Patents
Superconducting quantum chip and quantum computer Download PDFInfo
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- CN216286751U CN216286751U CN202122053357.4U CN202122053357U CN216286751U CN 216286751 U CN216286751 U CN 216286751U CN 202122053357 U CN202122053357 U CN 202122053357U CN 216286751 U CN216286751 U CN 216286751U
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Abstract
The application discloses superconductive quantum chip belongs to quantum computing technology field, and it includes: the bit unit comprises a plurality of bit one-dimensional chains which are sequentially coupled and connected, wherein each bit one-dimensional chain comprises at least three qubits, and the adjacent qubits are coupled and connected; and the reading resonant cavity and the regulating and controlling circuit are coupled and connected with the qubit. This application has the inner space and the exterior space that can be used for forming to read the resonant cavity and regulate and control the circuit through the bit unit that bit one-dimensional chain formed, and inner space and exterior space size can be adjusted as required to when having solved among the prior art integrated extension qubit, be difficult to have enough spatial arrangement to correspond the problem of observing and controling the signal transmission line, help realizing the integrated extension large amount qubit on the basement.
Description
Technical Field
The application belongs to the field of quantum information, particularly relates to the technical field of quantum computing, and particularly relates to a superconducting quantum chip and a quantum computer.
Background
Quantum computers are physical devices that perform high-speed mathematical and logical operations, store and process quantum information in compliance with the laws of quantum mechanics. The quantum computer is characterized by high running speed, strong information processing capability, wide application range and the like. Compared with a common computer, the more information processing amount is, the more beneficial the quantum computer to implement operation is, and the more accurate the operation can be ensured.
The existing structure of the qubit usually adopts a single capacitor to the ground and a superconducting quantum interference device with one end grounded and the other end connected with the capacitor, and when the extended qubit is integrated on a substrate with limited area, the arrangement of the qubit also influences the arrangement of a reading resonant cavity and a measurement and control signal transmission line, for example, as the number of integrated qubits is increased, the substrate is difficult to have enough space to arrange the structures of the reading resonant cavity, the measurement and control signal transmission line and the like. With the development demand of computing power, more and more qubits are expanded and integrated on a quantum chip, which is an unavoidable trend, and how to reasonably arrange the qubits and arrange structures such as a read resonant cavity, a measurement and control signal transmission line, and the like, is urgently needed to be solved, so that a superconducting quantum chip structure is urgently needed to meet the demand of integrating and expanding a large number of qubits on a substrate.
SUMMERY OF THE UTILITY MODEL
The application provides a superconducting quantum chip and a quantum computer, aiming at the problem that enough space arrangement is difficult to correspond to structures such as a reading resonant cavity, a measurement and control signal transmission line and the like when the extended quantum bit is integrated in the prior art, and provides a superconducting quantum chip structure to meet the requirement of integrating and extending a large number of quantum bits on a substrate.
An aspect of an embodiment of the present application provides a superconducting quantum chip, including:
the bit unit comprises a plurality of bit one-dimensional chains which are sequentially coupled end to end, each bit one-dimensional chain comprises at least three qubits, and the adjacent qubits are coupled; and
the quantum bit array comprises a reading resonant cavity and a regulating circuit, wherein the reading resonant cavity is positioned in the internal space or the external space of the bit unit, at least part of the regulating circuit is positioned in the internal space or the external space of the bit unit, and the reading resonant cavity and the regulating circuit are coupled and connected with the quantum bit.
The superconducting quantum chip as described above, wherein the read resonant cavities coupled to the qubits in the same bit one-dimensional chain are distributed on the same side of the same bit one-dimensional chain.
The superconducting quantum chip as described above, wherein the read resonators are all located in the inner space.
The superconducting quantum chip as described above, wherein a plurality of the bit one-dimensional chains form a quadrangle, a pentagon or a hexagon.
The superconducting quantum chip as described above, wherein:
the first part of the regulating circuit is positioned on the first substrate;
the bit cell, the read resonant cavity, and a second portion of the steering line are located on a second substrate and the first portion is coupled to the qubit and the first portion and the second portion are electrically connected.
The superconducting quantum chip as described above, wherein the second substrate has a through hole formed thereon, and the second portion is located within the through hole.
The superconducting quantum chip as described above, wherein a coupling structure is further formed between two said qubits in adjacent positions, and the frequency of the coupling structure is tunable.
The superconducting quantum chip as described above, wherein the coupling structure comprises a capacitance to ground, and a superconducting quantum interference device in parallel with the capacitance.
The superconducting quantum chip as described above, wherein the superconducting quantum interference device comprises josephson junctions connected in parallel, the josephson junctions being tunnel junctions, point junctions, or other structures exhibiting josephson effect.
Another aspect of an embodiment of the present application provides a quantum computer provided with at least a superconducting quantum chip as described above.
Compared with the prior art, the bit unit in the superconducting quantum chip provided by the embodiment of the application comprises a plurality of bit one-dimensional chains which are sequentially coupled end to end, wherein each bit one-dimensional chain comprises at least three qubits which are adjacent to each other, a reading resonant cavity which is located in the inner space or the outer space of the bit unit, and at least part of a regulating and controlling circuit which is located in the inner space or the outer space of the bit unit, and the reading resonant cavity and the regulating and controlling circuit are coupled and connected with the qubits. Therefore, the superconducting quantum chip provided by the embodiment of the application can adjust the size of the internal space and the external space of the bit unit through the number and/or the physical size of the qubits included in the bit one-dimensional chain, so that a larger space can be reserved, and the design and the arrangement of structures such as a resonant cavity, a measurement and control signal transmission line and the like can be conveniently read.
Drawings
Fig. 1 is a schematic distribution diagram of components of a superconducting quantum chip according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a superconducting quantum chip according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of the first chip 2 in fig. 2;
FIG. 4 is a schematic structural diagram of the second chip 3 in FIG. 2;
fig. 5 is a schematic structural diagram of a frequency-tunable coupling structure 35 according to an embodiment of the present disclosure.
Description of reference numerals:
1-superconducting quantum chip, 11-first bit one-dimensional chain, 12-second bit one-dimensional chain, 13-third bit one-dimensional chain, 14-fourth bit one-dimensional chain,
2-first chip, 21-first substrate, 22-first modulation circuit, 23-modulation connection, 24-first reading circuit, 25-reading connection,
3-a second chip, 31-a second substrate, 32-a qubit, 33-a second modulation circuit, 34-a read resonator, 35-a coupling structure, 36-a second read circuit, 37-a third read circuit, 351-a capacitor, 352-a superconducting quantum interference device, 353-a magnetic flux modulation signal line.
Detailed Description
The following detailed description is merely illustrative and is not intended to limit the embodiments and/or the application or uses of the embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding "background" or "summary" sections or "detailed description" sections.
To further clarify the objects, aspects and advantages of embodiments of the present application, one or more embodiments are now described with reference to the drawings, wherein like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced without these specific details in various instances, and that the various embodiments are incorporated by reference into each other without departing from the scope of the present disclosure.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
According to different physical systems adopted for constructing the qubits, the qubits include superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological quanta, photons and the like in a physical implementation manner.
The superconducting quantum circuit is the best solid quantum computing implementation method at present. Because the energy level structure of the superconducting quantum circuit can be regulated and controlled by an external electromagnetic signal, the controllability of the design customization of the circuit is strong. Meanwhile, due to the existing mature integrated circuit process, the quantum chip based on the superconducting quantum circuit has the scalability which is incomparable with most quantum physical systems.
Fig. 1 is a schematic distribution diagram of components of a superconducting quantum chip according to an embodiment of the present disclosure.
Fig. 2 is a schematic structural diagram of a superconducting quantum chip according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of the first chip 2 in fig. 2.
Fig. 4 is a schematic structural diagram of the second chip 3 in fig. 2.
The superconducting quantum chip 1 in fig. 2 includes a first chip 2 and a second chip 3 on the first chip 2, and for the sake of mutual distinction, a portion of the component on the first chip 2 covered and shielded by the second chip 3 in fig. 2 is illustrated by a dotted line.
Referring to fig. 1, and as shown in conjunction with fig. 2, 3 and 4, embodiments of the present application provide a superconducting quantum chip 1 comprising:
a bit unit, including a plurality of bit one-dimensional chains coupled end to end in sequence, for example, the bit unit in the superconducting quantum chip 1 includes a first bit one-dimensional chain 11, a second bit one-dimensional chain 12, a third bit one-dimensional chain 13, and a fourth bit one-dimensional chain 14, where the first bit one-dimensional chain 11, the second bit one-dimensional chain 12, the third bit one-dimensional chain 13, and the fourth bit one-dimensional chain 14 are coupled end to end in sequence to form a quadrilateral, and the number of the bit one-dimensional chains is not limited to this, in a specific implementation, the number of the bit one-dimensional chains may also be three, five, six, and so on, each bit one-dimensional chain includes at least three qubits 32, and adjacent qubits 32 are coupled and connected, it can be understood that the bit one-dimensional chains are formed by arranging the qubits 32 along a one-dimensional direction, and a closed structure formed by sequentially coupling and connecting the plurality of the bit one-dimensional chains end to end is the bit unit, the bit unit can be prepared on the surface of a substrate by utilizing the existing integrated circuit process, the substrate can adopt a dielectric substrate such as silicon or sapphire, the surface of the substrate where the bit unit is positioned is divided into an inner space and an outer space, and the structure of the quantum bit 32 can adopt a capacitor to the ground and a superconducting quantum interference device with one end grounded and the other end connected with the capacitor; and
a modulation circuit and a reading resonant cavity 34, where the reading resonant cavity 34 is located in an internal space or an external space of the bit cell, at least a part of the modulation circuit is located in the internal space or the external space of the bit cell, and both the modulation circuit and the reading resonant cavity 34 are coupled to the qubit 32.
Therefore, the surface of the substrate (silicon or sapphire dielectric substrate) where the bit unit is located is divided into an internal space a and an external space, the size of the internal space a is related to the number of qubits 32 included in the bit one-dimensional chain and/or the physical size of the qubits, when the superconducting quantum chip is designed and manufactured, the sizes of the internal space a and the external space can be adjusted according to the arrangement requirements of components (for example, a regulating circuit and a reading resonant cavity 34) so that the reading resonant cavity 34 is located in the internal space or the external space of the bit unit, the regulating circuit is at least partially located in the internal space or the external space of the bit unit, and the regulating circuit and the reading resonant cavity 34 are both coupled with the qubits 32.
In conjunction with the above description, those skilled in the art will understand that: compared with the prior art, the bit unit in the superconducting quantum chip 1 provided by the embodiment of the present application includes a plurality of bit one-dimensional chains sequentially coupled end to end, where the bit one-dimensional chain includes at least three qubits 32, and the qubits 32 are coupled and connected adjacently, a reading resonant cavity 34 located in an internal space or an external space of the bit unit, and at least a part of a regulation and control circuit located in the internal space or the external space of the bit unit, and the reading resonant cavity 34 and the regulation and control circuit are coupled and connected with the qubits 32. Thus, with the superconducting quantum chip 1 provided in the embodiment of the present application, the size of the internal space and the external space of the bit unit can be adjusted by the number and/or the physical size of the qubits 32 included in the one-dimensional chain of the bits, for example, the size of the internal space and the external space of the bit unit can be adjusted by adjusting the extension length of the capacitor in the qubit 32 between adjacent qubits 32, the extension length is the physical size of the capacitor along the one-dimensional direction in which the qubits 32 are arranged in the one-dimensional chain of the bits, and the extension width is the physical size of the capacitor perpendicular to the one-dimensional direction in which the qubits 32 are arranged in the one-dimensional chain of the bits, it can be understood that, in order to obtain a certain internal space and external space, the ratio of the extension length to the extension width can be defined, for example, the ratio of the extension length to the extension width is 5: 1 or more, thereby a larger space can be reserved, the design and arrangement of structures such as the resonant cavity 34 and the measurement and control signal transmission line (for example, a regulation and control line, a reading line and the like) can be conveniently read, for example, the resonant cavity 34 and the regulation and control line can be formed in the internal space and the external space and coupled with the qubit 32, the problem that the structures such as the resonant cavity 34 and the measurement and control signal transmission line are difficult to be arranged in enough space when the extended qubits are integrated in the prior art is solved, and the integrated extension of a large number of qubits on the substrate is facilitated.
In some embodiments of the present application, the reading resonant cavities 34 correspondingly coupled to the qubits 32 in the same one-dimensional chain of bits are distributed on the same side of the one-dimensional chain of bits, that is, the reading resonant cavities 34 corresponding to a plurality of qubits 32 in each one-dimensional chain of bits are distributed on the same side of the one-dimensional chain of bits, for example, as shown in fig. 1 and 2, the reading resonant cavities 34 corresponding to three qubits 32 in the second one-dimensional chain of bits are all arranged above the second one-dimensional chain of bits, and it can be understood that the reading resonant cavities 34 distributed on the same side may share one reading line to save space and facilitate wiring. In other embodiments of the present application, the read resonators 34 are located in the inner space such that all read resonators 34 in the same bitcell may share a read line.
In some embodiments of the present application, a plurality of bit one-dimensional chains coupled and connected in sequence in the bit cells form a quadrangle, a pentagon, or a hexagon, and the quadrangle, the pentagon, or the hexagon may be implemented as a basic unit on a surface array of a substrate (e.g., silicon, sapphire, etc.) to realize an integration and expansion of a large number of qubits on the substrate.
In some embodiments of the present application, the modulation lines include a first portion, which is a first modulation line 22 on a first substrate 21, and a second portion, which is a second modulation line 33 on a second substrate 31, and the bit cell and the read cavity 34 are also located on the second substrate 31, both the first substrate 21 and the second substrate 31 may be dielectric substrates such as silicon or sapphire, and the second control line 33 is coupled to the quantum bit 32, and the first control line 22 and the second control line 33 are electrically connected, for example, the first control circuit 22 is electrically connected to a control connection portion 23 on the first substrate 21, the control connection portion 23 may be a pad, a solder joint, or the like, the second control line 33 is electrically connected to the control connection 23, i.e. the first control line 22 and the second control line 33 are electrically connected. In the embodiment provided in the present application, the superconducting quantum chip 1 includes a first chip 2 and a second chip 3, and components collectively arranged on one substrate in the related art are divided to be arranged on the first substrate 21 and the second substrate 31, respectively.
In some embodiments of the present application, the first substrate 21 is formed with a through hole, which is, for example, a through silicon via formed on the silicon substrate by a TSV process, and the second portion of the modulation circuit (see the second modulation circuit 33 in fig. 3) is located in the through hole. As an implementation example, the second portion of the regulating circuit may be formed by filling a superconducting medium material in the through hole by using a 3D printing and filling process, and in particular, the manner of implementing through hole metallization is not limited thereto.
In some embodiments of the present application, the read lines include a first read line 24, a second read line 36 and a third read line 37, the first read line 24 is formed on a surface of the first substrate 21, the second read line 36 is formed on a surface of the second substrate 31, the second read line 36 is coupled to the corresponding read resonant cavity 34, the second substrate 31 further has a second through hole formed thereon, the third read line 37 is located in the second through hole, the first read line 24 and the second read line 36 are electrically connected through the third read line 37, illustratively, the first read line 24 is electrically connected to the read connection 25 located on the first substrate 21, the read connection 25 may be a solder pad, a pad, or the like, the third read line 37 electrically connected to the read connection 25 is prepared when metallization is implemented in the second through hole, thereby achieving electrical connection of the first read line 24, the second read line 36, and the third read line 37. As an implementation example, the third reading line 37 may be formed by filling a superconducting medium material in the second through hole by using a 3D printing and filling process, and in implementation, the manner of implementing metallization of the second through hole is not limited thereto.
In the embodiment provided by the present application, a coupling structure 35 is further formed between two adjacent quantum bits 32, the coupling structure 35 is coupled with both the two adjacent quantum bits 32 to realize the coupling connection between the two quantum bits 32, and the coupling structure 35 may be a structure with a fixed frequency, such as a capacitor or a resonant cavity, or a structure with a tunable frequency. Fig. 5 is a schematic structural diagram of a frequency-adjustable coupling structure 35 provided in this embodiment, adjacent quantum bits 32 are coupled and connected through the frequency-tunable coupling structure 35, and the frequency-tunable coupling structure 35 facilitates adjustment and control of coupling strength between the adjacent quantum bits 32, and facilitates implementation of a dual quantum logic gate. For example, two of the qubits 32 in adjacent positions are denoted as qubit q1 and qubit q2, respectively, the coupling structure 35 couples with qubit q1 and qubit q2, respectively, resulting in an indirect coupling between qubit q1 and qubit q2, and the coupling strength between qubit q1 and qubit q2 can be adjusted by adjusting the frequency of the coupling structure 35.
In the embodiment of the present application, when the qubits 32 are coupled and connected by using the frequency-adjustable coupling structure 35 to realize indirect coupling between two adjacent qubits 32, in order to ensure that the coupling structure 35 is not excited to an excited state, the coupling strength between the qubits 32 and the coupling structure 35, and the frequency of the qubits 32 and the frequency of the coupling structure 35 satisfy the following relationship:
wherein, ω isjIs the frequency, ω, of the quantum bit 32CIs the frequency, g, of the coupling structure 35jIs the coupling strength between the qubit 32 and the coupling structure 35.
In some embodiments of the present application, the coupling structure 35 includes, as an example of a frequency tunable coupling structure 35, a capacitor 351 connected to ground, and a superconducting quantum interference device 352 and a flux modulating signal line 353 connected in parallel with the capacitor. In some embodiments, the superconducting quantum interference device 352 comprises josephson junctions connected in parallel, in some examples, the superconducting quantum interference device 352 comprises at least two josephson junctions connected in parallel, and the frequency of the coupling structure 35 can be adjusted by applying magnetic flux through the flux modulation signal line 353. In some examples, to obtain an asymmetric configuration of the superconducting quantum interference device 352 such that the frequency spectrum of coupling structure 35 has at least two flux insensitive points, the number of josephson junctions in the superconducting quantum interference device 352 is an odd number. The josephson junction is a tunnel junction, a point contact, or other structure exhibiting josephson effect.
Similarly, qubit 32 (e.g., qubit q1 and qubit q2) includes a capacitor connected to ground at one end, and a superconducting quantum interferometer connected in parallel with the capacitor, the superconducting quantum interferometer including at least two josephson junctions connected in parallel, it being noted that the superconducting quantum interferometer in qubit 32 is structurally identical to superconducting quantum interference device 353 in frequency-tunable coupling structure 35, and for ease of description of the embodiments, the present application distinguishes between the two by name, in order to obtain an asymmetric structure of the superconducting quantum interferometer in qubit 32 such that the frequency spectrum of qubit 32 has at least two flux-insensitive points, and the number of josephson junctions in the superconducting quantum interferometer can also be chosen to be an odd number. The frequency of the qubit can be changed by applying a magnetic flux to qubit q1 and qubit q2 such that the applied magnetic flux directly affects the josephson energy of the qubit, and thus the frequency of the qubit can be conveniently adjusted by adjusting the magnetic flux through the superconducting quantum interference device. In the frequency tunable coupling structure 35, the frequency of the coupling structure 35 can be changed by changing the magnetic field generated by the current flowing through the josephson junction in the superconducting quantum interference device 352. Based on the method, the indirect coupling of the qubits q1 and q2 at adjacent positions can be realized, and a foundation is laid for realizing the double-quantum logic gate.
The fabrication process of a superconducting quantum chip provided by the embodiments of the present application may require deposition of one or more materials, such as a superconductor, a dielectric, and/or a metal. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, among others. A fabrication process for a superconducting quantum chip provided by embodiments of the present application may require removal of one or more materials from a device during a fabrication process. Depending on the material to be removed, the removal process may include, for example, a wet etching technique, a dry etching technique, or a lift-off (lift-off) process. The materials forming the circuit elements described herein may be patterned using known exposure (lithographical) techniques, such as photolithography or electron beam exposure.
Embodiments of the present application also provide a quantum computer, which is at least provided with the superconducting quantum chip as described above.
Here, it should be noted that: the quantum chip in the superconducting quantum computer has a similar structure to the above structure, and has the same beneficial effects as the above embodiments of the superconducting quantum chip, and therefore, the description thereof is omitted. For technical details not disclosed in the embodiments of the superconducting quantum computer of the present application, those skilled in the art should refer to the description of the superconducting structure above for understanding, and for the sake of brevity, will not be described again here.
The quantum computer provided by the embodiment of the application is a superconducting system, the quantum computer is provided with a control and reading device connected with the superconducting quantum chip, and the regulation and control circuit 33 described by the embodiment of the application comprises a first magnetic flux modulation line and a pulse modulation line. The control and reading device adjusts the frequency of the qubit 32 to the working frequency by using the flux control signal on the first flux modulation line, and at this time, the quantum state control signal is applied through the pulse modulation line to perform quantum state control on the qubit 32 in the initial state, and the reading resonant cavity 34 is used for reading the quantum state of the qubit 32 after control. The steering and reading device determines the quantum state in which the qubit is located by interpreting a read feedback signal (a signal responsive to the read probe signal) output via a read line by applying a read probe signal (e.g., a microwave signal having a frequency of 4-8 GHz) to the read line coupled to the read resonant cavity 34.
The construction, features and functions of the present application are described in detail in the embodiments illustrated in the drawings, which are only preferred embodiments of the present application, but the present application is not limited by the drawings, and all equivalent embodiments that can be modified or changed according to the idea of the present application are within the scope of the present application without departing from the spirit of the present application.
Claims (10)
1. A superconducting quantum chip, comprising:
the bit unit comprises a plurality of bit one-dimensional chains which are sequentially coupled end to end, each bit one-dimensional chain comprises at least three qubits, and the adjacent qubits are coupled; and
the quantum bit array comprises a reading resonant cavity and a regulating circuit, wherein the reading resonant cavity is positioned in the internal space or the external space of the bit unit, at least part of the regulating circuit is positioned in the internal space or the external space of the bit unit, and the reading resonant cavity and the regulating circuit are coupled and connected with the quantum bit.
2. The superconducting quantum chip of claim 1, wherein the reading resonant cavities coupled to the qubits in a same bit one-dimensional chain are distributed on a same side of the same bit one-dimensional chain.
3. A superconducting quantum chip according to claim 1 or 2 wherein the read resonators are both located in the inner space.
4. The superconducting quantum chip of claim 1, wherein a plurality of the bit one-dimensional chains form a quadrilateral, a pentagon, or a hexagon.
5. The superconducting quantum chip of claim 1, 2 or 4,
the first part of the regulating circuit is positioned on the first substrate;
the bit cell, the read resonant cavity, and a second portion of the steering line are located on a second substrate and the first portion is coupled to the qubit and the second portion is electrically connected to the first portion.
6. A superconducting quantum chip according to claim 5 wherein the second substrate has a through-hole formed therein, the second portion being located within the through-hole.
7. The superconducting quantum chip of claim 1, wherein a coupling structure is further formed between two of the qubits in adjacent positions, and wherein the coupling structure is tunable in frequency.
8. The superconducting quantum chip of claim 7, wherein the coupling structure comprises a capacitance to ground, and a superconducting quantum interference device in parallel with the capacitance.
9. The superconducting quantum chip of claim 8, wherein the superconducting quantum interference device comprises josephson junctions in parallel with each other, the josephson junctions being tunnel junctions or point contacts.
10. A quantum computer, characterized in that it is provided with at least a superconducting quantum chip according to claims 1-9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115511096A (en) * | 2022-11-24 | 2022-12-23 | 合肥本源量子计算科技有限责任公司 | Quantum bit structure and quantum chip |
| WO2023226598A1 (en) * | 2022-05-27 | 2023-11-30 | 本源量子计算科技（合肥）股份有限公司 | Reading circuit, reading method and quantum computer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023226598A1 (en) * | 2022-05-27 | 2023-11-30 | 本源量子计算科技（合肥）股份有限公司 | Reading circuit, reading method and quantum computer |
| CN115511096A (en) * | 2022-11-24 | 2022-12-23 | 合肥本源量子计算科技有限责任公司 | Quantum bit structure and quantum chip |
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