WO2024045930A1 - Quantum chip and quantum computer - Google Patents

Abstract

Provided are a quantum chip and a quantum computer. The quantum chip comprises: a superconducting quantum bit circuit, the superconducting quantum bit circuit forming a first part circuit surrounding a first area and a second part circuit surrounding a second area; and a magnetic flux regulation and control signal line coupled with the superconducting quantum bit circuit, induced currents in opposite directions being obtained in the first part circuit and the second part circuit by means of a regulation and control signal applied by the magnetic flux regulation and control signal line. The quantum chip provided by the present application helps to suppress the impact of noises in regulating and controlling magnetic fluxes on regulation and control of quantum bits.

Description

Quantum chips and quantum computers

This application requires the priority of the Chinese patent application with the application number 202211061364.1 and the application name "Superconducting Qubit Structure and Quantum Computer" submitted to the China Patent Office on August 31, 2022. It is required to be submitted on September 22, 2022. Priority is granted to the Chinese Patent Office with application number 202211158061.1 and the application title "Quantum Chip and Quantum Computer". The entire contents of these patents are incorporated into this application by reference.

Technical field

The present application relates to the field of computing technology, and more specifically, to a quantum chip and a quantum computer.

Background technique

Quantum chip is the core component of quantum computer. The basic idea of constructing a quantum chip using a superconducting physical system is: a squid formed by connecting Josephson junctions in parallel is connected in parallel with a capacitor plate. The superconducting qubit circuit formed based on this parallel structure serves as the basic unit for performing quantum calculations on the quantum chip. —Qubits. Qubits can be controlled by applying external electromagnetic signals. Among them, the magnetic flux of squid can be controlled by applying a signal to the magnetic flux control signal line (Z-control line) on the quantum chip to complete the control of the qubit frequency, thereby realizing a series of qubits. operate. At present, when quantum chips of related technologies perform quantum calculations, the qubits are very sensitive to the noise of the magnetic flux control, and their frequency is easily affected by the noise and deviates from the ideal position, thereby affecting the accuracy of qubit control.

Contents of the invention

This application provides a quantum chip and a quantum computer. Each aspect involved in this application is introduced below.

In a first aspect, a quantum chip is provided, including: a superconducting qubit circuit forming a first part of the circuit surrounding the first region and a second part of the circuit surrounding the second region; and, with the The superconducting qubit circuit is coupled with a magnetic flux control signal line, and the control signal applied by the magnetic flux control signal line obtains induced currents in opposite directions in the first part of the circuit and the second part of the circuit.

Optionally, the superconducting qubit circuit includes: a capacitor plate; and a first Josephson junction and a second Josephson junction, the first Josephson junction and the second Josephson junction are connected in parallel, and the One end of the first Josephson junction and one end of the second Josephson junction are both connected to the capacitor plate, the other end of the first Josephson junction and the other end of the second Josephson junction are interconnected, and Ground.

Optionally, the superconducting qubit circuit includes a first electrical connection structure, and the other end of the first Josephson junction and the other end of the second Josephson junction are interconnected through the first electrical connection structure, And the first electrical connection structure intersects with the capacitor plate in a non-contact manner.

Optionally, the superconducting qubit circuit includes a first electrical connection structure and a second electrical connection structure, and one end of the first Josephson junction and one end of the second Josephson junction are connected through the first electrical connection. Structural connection, the other end of the first Josephson junction and the other end of the second Josephson junction are connected through the second electrical connection structure, and the second electrical connection structure and the first electrical connection structure Non-contact crossover.

Optionally, the superconducting qubit circuit includes: a first capacitor plate and a second capacitor plate; and a first Josephson junction and a second Josephson junction, one end of the first Josephson junction and the The second Josephson knot has one end connected to all The first capacitor plate is connected, and the other end of the first Josephson junction and the other end of the second Josephson junction are both connected to the second capacitor plate.

Optionally, the first capacitor plate and the second capacitor plate are arranged separately.

Optionally, the first capacitor plate and the second capacitor plate intersect in a non-contact manner.

Optionally, the second capacitor plate surrounds the first capacitor plate, and the first region and the second region are located between the second capacitor plate and the first capacitor plate. .

Optionally, the first capacitor plate and the second capacitor plate are symmetrically distributed along the connection line of the first Josephson junction and the second Josephson junction.

Optionally, the geometric center of the first capacitor plate overlaps the geometric center of the second capacitor plate.

Optionally, the ground capacitance C ₀₁ of the first capacitor plate and the ground capacitance C ₀₂ of the second capacitor plate satisfy the following relationship: 100C ₀₁ ≤ C ₀₂ , or 100C ₀₂ ≤ _{C 01} .

Optionally, the second capacitor plate is an annular membrane.

Optionally, a capacitor arm for coupling is formed on the second capacitor plate.

Optionally, the first capacitor plate is an annular membrane or a circular membrane.

Optionally, the first capacitor plate surrounds the magnetic flux control signal line.

Optionally, the superconducting qubit circuit includes: a first Josephson junction and a second Josephson junction; a first capacitor plate and a second capacitor plate, the first capacitor plate and the second capacitor The plates are independently located at both ends of the first Josephson junction; and, a third capacitor plate and a fourth capacitor plate, the third capacitor plate and the fourth capacitor plate are independently located at Both ends of the second Josephson junction; and there is no contact between the first capacitor plate and the fourth capacitor plate, and between the second capacitor plate and the third capacitor plate. cross electrical connections.

Optionally, the magnetic flux control signal line and the superconducting qubit circuit are formed on the same surface, and the magnetic flux control signal line is located on one side of the superconducting qubit circuit.

Optionally, the magnetic flux control signal line and the superconducting qubit circuit are formed on different surfaces.

Optionally, the magnetic flux control signal line includes a coil.

Optionally, the coil includes a first coil and a second coil, and the first coil and the second coil are arranged alternately, and the current directions of the first coil and the second coil are opposite.

A second aspect provides a quantum computer provided with the quantum chip described in the first aspect.

The quantum chip provided by this application includes a superconducting qubit circuit and a magnetic flux control signal line coupled with the superconducting qubit circuit, and the superconducting qubit circuit forms a first part of the circuit surrounding the first region and a second part of the circuit surrounding the first region. The second part of the circuit in the area; the control signal applied through the magnetic flux control signal line generates corresponding magnetic flux in the first area and the second area, and then obtains induced currents in opposite directions in the first part of the circuit and the second part of the circuit. , the opposite induced currents cancel each other to a certain extent, reducing the impact of noise on the Josephson junction energy, thereby reducing the impact of noise on the qubit frequency, which in turn helps reduce the deviation of the qubit frequency and ensures the operational accuracy of the qubit.

Description of drawings

Figure 1 is a schematic structural diagram of a qubit on a quantum chip in related technology;

Figure 2 is a schematic diagram of a quantum chip provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of the first implementation example of a quantum chip using a single capacitor plate in this application;

Figure 4 is a schematic structural diagram of a second implementation example of a quantum chip using a single capacitor plate in this application;

Figure 5 is a schematic structural diagram of a third implementation example of a quantum chip using a single capacitor plate in this application;

Figure 6 is a schematic structural diagram of the first implementation example of a quantum chip using two capacitor plates in this application;

Figure 7 is a schematic structural diagram of a second implementation example of a quantum chip using two capacitor plates in this application;

Figure 8 is a schematic structural diagram of a third implementation example of a quantum chip using two capacitor plates in this application;

Figure 9 is a schematic structural diagram of a fourth implementation example of a quantum chip using two capacitor plates in this application;

Figure 10 is a schematic structural diagram of the fifth implementation example of a quantum chip using two capacitor plates in this application;

Figure 11 is a schematic structural diagram of the sixth implementation example of a quantum chip using two capacitor plates in this application;

Figure 12 is a schematic structural diagram of the seventh implementation example of a quantum chip using two capacitor plates in this application;

Figure 13 is a schematic diagram of the implementation structure of a quantum chip using four capacitor plates in this application;

Figure 14 is a schematic structural diagram of an embodiment of the magnetic flux control signal line of the present application.

Explanation of reference symbols:

11-First Josephson knot, 12-Second Josephson knot,

21-the first capacitor plate, 22-the second capacitor plate, 220-the capacitor arm, 23-the third capacitor plate, 24-the fourth capacitor plate,

31-first electrical connection structure, 32-second electrical connection structure,

4-Magnetic flux control signal line, 41-first coil, 42-second coil, 43-transfer point,

5-Pulse control signal line.

Detailed ways

The technical solutions in this application will be described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and cannot be construed as limiting the present application.

In order to make the objectives, technical solutions and advantages of the embodiments of the present application more clear, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used to refer to similar components throughout. In the following description, for the purpose of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It will be apparent, however, that in various circumstances one or more embodiments may be practiced without these specific details and that the various embodiments may be combined and referenced with each other provided they are not inconsistent with each other.

It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances so that the embodiments of the application described herein can be practiced in sequences other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus that encompasses a series of steps or units and need not be limited to those explicitly listed. Those steps or elements may instead include other steps or elements not expressly listed or inherent to the process, method, product or apparatus.

In addition, it will be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and/or pattern, it can be directly on another layer or structure. on the substrate, and/or intervening layers may also be present. In addition, it will be understood that when a layer is referred to as being "under" another layer, it can be directly under the other layer, and/or one or more intervening layers may also be present. In addition, references to "on" and "under" each layer may be made based on the drawings.

According to the different physical systems used to construct qubits, the physical implementation methods of qubits include superconducting physical systems, semiconductor quantum dot physical systems, ion traps, diamond vacancies, topological quantum, photons, etc. Superconducting physics system It is currently the fastest and best way to implement solid-state quantum computing. The energy level structure of superconducting qubit circuits based on superconducting physical systems can be controlled by external electromagnetic signals, and the design and customization of the circuits are highly controllable. At the same time, thanks to the existing mature integrated circuit technology, the superconducting physics system has scalability that is unmatched by most quantum physics systems.

In the superconducting physics system, Transmons is a commonly used qubit structure. As shown in Figure 1, the qubit includes a capacitor, and a superconducting quantum interference device squid with one end connected to ground and the other end connected to the capacitor. Among them, squid The equivalent critical current I _c is adjusted by the external magnetic field Φ _e . The capacitor is often a cross-shaped parallel plate capacitor, as shown in Figure 1. The cross-shaped capacitor plate C _q is surrounded by the ground plane GND, and there is a gap between the cross-shaped capacitor plate and the ground plane GND. One end of the superconducting quantum interference device squid Connect to the cross-shaped capacitive plate, and the other end is connected to the ground plane GND. Since the first end of the cross-shaped capacitive plate is used to connect the superconducting quantum interference device squid, the second end is used to couple with the reading resonant cavity, and the first end and A certain space needs to be reserved near the second end for wiring. For example, space needs to be reserved near the first end for the pulse control signal line and the magnetic flux control signal line (Z-control line). In addition, the cross-shaped capacitor plate Both ends can be used to couple to adjacent qubits.

According to the calculation formula of qubit frequency It can be seen that the qubit frequency ω ₁₀ is related to the electrostatic energy E _C of the capacitor and the energy E _J of the squid. The energy E _J of the squid changes with the external magnetic field. Therefore, the control of the qubit frequency can be completed by the response of the energy E _J of the squid to changes in the external magnetic field. adjust. The magnetic flux control signal line (Z-control line) is a structure that controls the external magnetic field Φ _e . It is generally arranged next to the squid. The current applied to the magnetic flux control signal line (Z-control line) is used to generate the external magnetic field Φ _e . The external magnetic field passing through the squid region causes changes in the qubit frequency of the squid region. The magnetic flux penetrating the squid loop is affected by factors such as the magnitude of the magnetic field generated by the electrical signal applied to the flux control signal line, the mutual inductance strength M between the flux control signal line and the squid loop, and magnetic flux noise. Magnetic flux noise is the inherent noise caused by current fluctuations in the magnetic flux control signal or the magnetic flux noise caused by the additional signals carried by the magnetic flux control signal. The magnetic flux noise will cause the qubit frequency to fluctuate and deviate.

In order to suppress magnetic flux noise, the current applied to the magnetic flux control signal line (Z-control line) is usually required to have high accuracy. However, this method requires high signal control and is difficult to suppress inherent noise.

In order to solve the problem that when a quantum chip of related technologies performs quantum calculations, the qubit frequency is easily affected by magnetic flux noise, causing the qubit frequency to deviate from the ideal position and affecting the accuracy of qubit control, embodiments of the present application provide a quantum chip and a quantum computer. , to reduce the impact of magnetic flux noise on qubit control.

Figure 2 is a schematic diagram of a quantum chip provided by an embodiment of the present application.

Referring to Figure 2, a quantum chip provided by an embodiment of the present application includes a superconducting qubit circuit, and a magnetic flux control signal line coupled with the superconducting qubit circuit, wherein: the superconducting qubit circuit A first partial circuit surrounding the first area and a second partial circuit surrounding the second area are formed, and the control signal applied by the magnetic flux control signal line obtains induced currents in opposite directions in the first partial circuit and the second partial circuit.

The superconducting qubit circuit in the embodiment of the present application is a thin film circuit structure, which can be directly prepared and formed on the substrate using a semiconductor process. Combined with the diagram of Figure 2, in the embodiment of the present application, when the qubit adjusts the frequency in response to the external magnetic field generated by the current signal, the magnetic flux regulates the role of the current signal I+i (where i is the noise signal) transmitted by the signal line. Under , corresponding magnetic fluxes are generated in the first area and the second area respectively, the noise signal i generates an induced current i ₁ in the first part of the circuit, and an induced current i ₂ is generated in the second part of the circuit, and the induced currents i ₁ and The direction of i ₂ is opposite, and the opposite induced currents i ₁ and i ₂ cancel each other to a certain extent, which reduces the impact of noise on the energy of the equivalent Josephson junction of squid, thereby reducing the impact of noise on the frequency of the qubit, with Helps reduce the deviation of qubit frequency and improves the accuracy of qubit operation. In the embodiments of this application, the improvement of the stability of the qubit frequency helps to improve the performance of the qubit. Decoherence time. It should be noted that Figure 2 illustrates the directions of the induced currents generated by the noise signal i in the first part of the circuit and the second part of the circuit respectively. The induced current generated by the noise signal i in the superconducting qubit circuit is composed of the induced current i ₁ and The result after the interaction of i ₂ .

Embodiments of the present application are further described below with reference to FIGS. 3 to 14 .

Embodiment 1: An embodiment of a quantum chip using a single capacitor plate

Figures 3 to 5 are schematic diagrams of the implementation structure of a quantum chip using a single capacitor plate in this application. Q ₁ and Q ₂ represent two qubits located on the quantum chip. The use of a single capacitor plate will be further described below in conjunction with Figures 3 to 5 Example of a quantum chip on the board.

In some embodiments of the present application, the superconducting qubit circuit includes a first capacitor plate 21, and a first Josephson junction 11 and a second Josephson junction 12, wherein the first Josephson junction 11 and The second Josephson junction 12 is connected in parallel, and one end of the first Josephson junction 11 and one end of the second Josephson junction 12 are connected to the first capacitor plate 21 . The other end of the junction and the other end of the second Josephson junction are interconnected and connected to the ground plane GND. In this embodiment, the bottom superconducting electrode and/or the top superconducting electrode of the Josephson junction itself can be directly used for connection, or an additionally formed electrical connection structure can be used for connection. The connection form is not limited, as long as the above-mentioned first The superconducting qubit circuit formed by connecting the capacitor plate 21, the first Josephson junction 11, and the second Josephson junction 12 only needs to form a first part of the circuit surrounding the first region and a second part of the circuit surrounding the second region.

As shown in FIG. 3 , in order to form a superconducting qubit circuit with a first part of the circuit surrounding the first region and a second part of the circuit surrounding the second region, in some examples, the superconducting qubit circuit includes a first circuit Connection structure 31, the first electrical connection structure 31 electrically and physically connects the other end of the first Josephson junction 11 and the other end of the second Josephson junction 12, wherein the first Josephson junction The other end of the junction 11 is directly connected to the ground plane GND, and the first electrical connection structure 31 intersects with the first capacitor plate 21 in a non-contact manner. In this embodiment, one end of the first Josephson junction 11 and one end of the second Josephson junction 12 are electrically and physically connected to the first capacitor plate 21 . The non-contact intersection described in this article means that the projection of the extended trajectory of the two electrical structures on the substrate surface has an intersection point, and the two electrical structures above the intersection point are filled with some dielectric to reduce or block the gap between the two electrical structures. influence on signal transmission.

As shown in FIG. 4 , in order to form a superconducting qubit circuit with a first part of the circuit surrounding the first region and a second part of the circuit surrounding the second region, in other examples, the superconducting qubit circuit includes a first part of the circuit. The electrical connection structure 31 and the second electrical connection structure 32, wherein the first electrical connection structure 31 electrically and physically contacts and connects one end of the first Josephson junction 11 and one end of the second Josephson junction 12, Keep the first Josephson junction 11 and the second Josephson junction 12 to be electrically connected to the first capacitor plate 21 , and the second electrical connection structure 32 is electrically and physically connected to the first The other end of the Josephson junction 11 and the other end of the second Josephson junction 12 keep both the first Josephson junction 11 and the second Josephson junction 12 connected to the ground plane GND, and the second The electrical connection structure 32 intersects the first electrical connection structure 31 in a non-contact manner. Specifically, one end of the first Josephson junction 11 can be directly electrically and physically connected to the first capacitor plate 21 , and one end of the second Josephson junction 12 can be connected to the first capacitor plate 21 through the first electrical connection structure 31 . The capacitor plate 21 is electrically and physically connected, the other end of the first Josephson junction 11 is directly connected to the ground, and the other end of the second Josephson junction 12 is common with the other end of the second Josephson junction 12 through the second electrical connection structure 32 Connect the ground plane GND.

The implementation of the quantum chip using a single capacitor plate is not limited to the above. As shown in FIG. 5 , when the present application is implemented, the first capacitor plate 21 can also be surrounded by the ground plane GND, and the first capacitor plate 21 is surrounded by the ground plane GND. 21 and ground There is a gap between the plane GND, the first Josephson junction 11 and the second Josephson junction 12 are distributed in the gap on both sides of the first capacitor plate 21, and the first Josephson junction 11 and the One end of the second Josephson junction 12 is electrically and physically connected to the first capacitor plate 21 , and the other end is electrically and physically connected to the ground plane GND.

Embodiment 2: An embodiment of a quantum chip using two capacitor plates

Figures 6 to 12 are schematic diagrams of the implementation structure of a quantum chip using two capacitor plates in this application. Q ₁ and Q ₂ represent two qubits located on the quantum chip. The use of two qubits will be further described below in conjunction with Figures 6 to 12 An embodiment of a quantum chip with capacitor plates.

In other embodiments of the present application, the superconducting qubit circuit includes a first capacitor plate 21 and a second capacitor plate 22, and a first Josephson junction 11 and a second Josephson junction 12, wherein, The first Josephson junction 11 and the second Josephson junction 12 are connected in parallel, and both one end of the first Josephson junction 11 and one end of the second Josephson junction 12 are connected to the first capacitor. The plates 21 are connected, and the other end of the first Josephson junction 11 and the other end of the second Josephson junction 12 are both connected to the second capacitor plate 22 . In this embodiment, the bottom superconducting electrode and/or the top superconducting electrode of the Josephson junction itself can be directly used for connection, or an additionally formed electrical connection structure can be used for connection. The connection form is not limited, as long as the above-mentioned first The superconducting qubit circuit formed by connecting the capacitor plate 21 and the second capacitor plate 22 and the first Josephson junction 11 and the second Josephson junction 12 forms a first part of the circuit surrounding the first region and a circuit surrounding the second region. The second part of the circuit is enough.

In some examples, in order to form a superconducting qubit circuit with a first part of the circuit surrounding the first region and a second part of the circuit surrounding the second region, the first capacitor plate 21 and the second capacitor plate are used 22 non-contact crossover forms. The non-contact intersection described in this example means that the projections of the extension tracks of the first capacitor plate 21 and the second capacitor plate 22 on the substrate surface have an intersection point, and the first capacitor above the intersection point A certain dielectric is filled between the plate 21 and the second capacitor plate 22 to reduce or block the influence of signal transmission between the two electrical structures. During specific implementation, the first capacitor plate 21 and the second capacitor plate 22 can be formed on two surfaces with different heights. The difference in height can be realized by using grooves formed on the surface of the substrate. For example, the first capacitor plate 21 can be formed on two surfaces with different heights. The plate 21 is formed below the groove, and the second capacitor plate 22 is formed on the surface of the substrate and spans both sides of the groove. During specific implementation, the first capacitor plate 21 and the second capacitor plate 22 can also be formed on one surface, and one bridge is used to bridge the other at the intersection of the tracks.

In other examples, in order to form a superconducting qubit circuit with a first part of the circuit surrounding the first region and a second part of the circuit surrounding the second region, the second capacitance plate 22 surrounds the first capacitance plate. 21 and the first region and the second region are located between the second capacitor plate 22 and the first capacitor plate 21 , as shown in FIGS. 6 to 12 . Specifically, as shown in FIG. 6 , the first capacitor plate 21 and the second capacitor plate 22 are separated, and the second capacitor plate 22 surrounds the first capacitor plate 21 , and the first Josephson junction The first end of 11 is connected to the first capacitor plate 21, the second end of the first Josephson junction 11 is connected to the second capacitor plate 22, and the first end of the second Josephson junction 12 The second end of the second Josephson junction 12 is connected to the first capacitor plate 21 , the second end of the second Josephson junction 12 is connected to the second capacitor plate 22 , and a magnetic flux regulating device is arranged near the second capacitor plate 22 Signal line 4 and pulse control signal line 5.

In order to facilitate the description of the embodiments of this application, Q ₁ and Q ₂ are used to represent each qubit formed on the substrate in Figure 6 , where each qubit represented by the first qubit Q ₁ and the second qubit Q ₂ Both include a first capacitor plate 21 and a second capacitor plate 22. The first capacitor plate 21 and the second capacitor plate 22 are not directly connected to the ground plane GND, but There is a suitable gap between the first capacitor plate 21 and the ground plane GND. The physical size of the gap is designed and determined according to the performance parameters of the quantum chip. It should be noted that the capacitor C ₀₁ is formed between the first capacitor plate 21 and the ground plane GND. A capacitance C ₀₂ is formed between the two capacitor plates 22 and the ground plane GND, and a capacitance C ₁₂ is formed between the first capacitor plate 21 and the second capacitor plate 22 . The capacitance C 01 and the capacitance C ₀₁ can be determined based on the performance parameters of the quantum chip. The values of C ₀₂ and capacitor C ₁₂ are then calculated to determine the physical sizes of the first capacitor plate 21 and the second capacitor plate 22 .

In the embodiment of the present application, the first Josephson junction 11 and the second Josephson junction 12 divide the first capacitor plate 21 and the second capacitor plate 22 surrounding the first capacitor plate 21 to form two parts of the circuit. As shown in Figure 6, the upper area surrounded by the four is the first area, and the lower area surrounded by the four is the second area. When the current I is used to regulate the magnetic flux to control the frequency of the qubit, the current that brings in the magnetic flux noise The fluctuation of i generates a changing magnetic field in the qubit circuit area, which forms induced currents i ₁ and i ₂ in opposite directions in the circuit surrounding the first area and the circuit surrounding the second area respectively. The opposite induced currents can form a certain This degree of cancellation reduces the impact of noise on the deviation of the qubit frequency, thereby helping to control the frequency of the qubit at an ideal position. Therefore, the embodiments of the present application help to suppress the impact of magnetic flux noise on the operation accuracy of qubits, and control the frequency of qubits more accurately to a position that is insensitive to magnetic flux.

In some embodiments of the present application, at least one of the first capacitor plate 21 and the second capacitor plate 22 may be an annular film, as shown in FIGS. 6 to 12 . During specific implementation, the first capacitor plate 21 and the second capacitor plate 22 are not limited to the above shapes, as long as the second capacitor plate 22 can surround the first capacitor plate 21, such as As shown in Figure 7 and Figure 8. In other embodiments of the present application, the first capacitor plate 21 may also be a circular film, as shown in FIGS. 6 and 8 . It can be understood that annular films and circular films are thin film electrical structures with an annular or circular pattern formed on a substrate. The quantum chip in the embodiment of the present application can directly use mature semiconductor processes to deposit superconducting materials. Obtained by patterning, etc., the deposited thickness can be micron or nanoscale, and the superconducting material exhibits superconducting at a temperature equal to or lower than the critical temperature, such as about 10-100 millikelvin (mK) or about 4mK. Materials with special properties, such as aluminum, niobium, tantalum or titanium nitride, etc., are not limited to these types in specific implementations. Materials that exhibit superconducting properties at a temperature equal to or lower than the critical temperature can be used to form the thin film electrode. Structure, for example, one or more of aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN) and niobium titanium nitride (NbTiN).

Combined with Figure 6 and compared with Figure 7 and Figure 8, in order to further facilitate the coupling between qubits, or to form coupling with other electrical components on the quantum chip, in some embodiments of the present application, the second A capacitor arm 220 for coupling is formed on the capacitor plate 22. The capacitor arm 220 can be coupled with the adjacent magnetic flux control signal line 4 and/or the pulse control signal line 5, and can also be used to promote the realization of Q ₁ and Q Coupling between ₂ , or coupling with a circuit structure such as a reading resonant cavity.

In the embodiment of the quantum chip using two capacitor plates, when the first capacitor plate 21 is an annular film, the magnetic flux control signal line 4 can be arranged in a form surrounded by the first capacitor plate 21, It should be noted that the first capacitor plate 21 is not limited to an annular film. As long as there is a vacant area surrounded by the first capacitor plate 21 on the substrate, a mature semiconductor process can be directly used to form a signal transmission line. A part of the signal transmission line is formed in the vacant area, that is, is surrounded by the first capacitor plate 21 , so that it can serve as the magnetic flux control signal line 4 . In one embodiment, the magnetic flux control signal line 4 includes at least 1 turn of coil. As shown in Figure 9, the two ends of the coil can be electrically connected to the signal transmission line on the other surface of the substrate through a TSV-based superconducting pillar. Physically connected, a signal transmission line is used to transmit the magnetic flux control signal from the other surface of the substrate to the coil to achieve magnetic flux control of the qubit.

For example, as shown in FIG. 10 and FIG. 11 , the magnetic flux control signal line 4 may include a first coil 41 and The second coil 42, and the first coil 41 and the second coil 42 are arranged alternately, and the current directions of the first coil 41 and the second coil 42 are opposite, so as to facilitate the adjustment of mutual inductance intensity and magnetic field flux. The first coil 41 and the second coil 42 may be formed by winding two relatively independent transmission lines respectively (as shown in Figure 10), or they may be formed by winding the same transmission line in different directions (as shown in Figure 11). ).

As shown in FIG. 12 , in some examples, the magnetic flux control signal line 4 includes a first coil 41 and a second coil 42 connected in series and with opposite winding directions, and the entire second coil 42 is located on the within the entire first coil 41 . It can be understood that the magnetic flux control signal line 4 includes two parts connected in series, one part forming the first coil 41 and the other part forming the second coil 42 . In view of the phenomenon that the central magnetic field is strong and the peripheral magnetic field is weak when the overall winding direction of the coil is consistent, this phenomenon can easily cause the magnetic field of the squid structure of each qubit on the quantum chip to be uneven. In the embodiment of the present application, two coils with opposite winding directions are arranged in series, and the entirety of the second coil 42 is located inside the entirety of the first coil 41. This can relatively weaken the central magnetic field and strengthen the peripheral annular magnetic field, which is helpful. To achieve a certain degree of uniformity, or to achieve acceptable uniformity in a desired area.

It can be understood that in the embodiment of the present application, the first coil 41 and the second coil 42 connected in series and with opposite winding directions can also be the above-mentioned thin film circuits, and the first coil 41 and the second coil 42 can be formed by photolithography. , electroplating and other processes introduced above are simultaneously prepared and formed.

As shown in FIG. 12 , the magnetic flux control signal line 4 formed on the substrate includes a transfer point 43 . The transfer point 43 divides the signal line into two parts, one part forming the first coil 41 and the other part The second coil 42 is formed, the winding direction of the signal line in the first coil 41 is opposite to the winding direction of the signal line in the second coil 42, and the first coil 41 and the second coil 42 are connected in series at the transfer point 43 .

In other embodiments of the present application, the first capacitor plate 21 and the second capacitor plate 22 are both connected along the first Josephson junction 11 and the second Josephson junction 12 . Symmetrically distributed, that is, the film patterns of the first capacitor plate 21 and the second capacitor plate 22 are axially symmetrical. In other embodiments of the present application, the geometric center of the first capacitor plate 21 and the geometric center of the second capacitor plate 22 are at the same position. It should be noted that the specific implementation is not limited thereto. The geometric shapes of the first capacitor plate 21 and the second capacitor plate 22 are relative to the first Josephson junction 11 and the second Josephson junction. The distribution of junction 12 affects the magnitude of the induced currents of the two loops. During specific implementation, the geometric shapes of the first capacitor plate 21 and the second capacitor plate 22 can be adjusted according to the relative magnitudes of the induced currents of the two loops, and The positions are distributed relative to the first Josephson junction 11 and the second Josephson junction 12 .

In other embodiments of the present application, the ground capacitance C ₀₁ of the first capacitor plate 21 and the ground capacitance C 02 of the second capacitor plate ₂₂ satisfy the following relationship: 100C ₀₁ <C ₀₂ or 100C ₀₂ <C ₀₁ . according to The corresponding equivalent bit capacitance in the superconducting qubit circuit is C _q ≈ C ₁₂ + C ₀₁ , or C _q ≈ _{C 12} + C ₀₂ , where C ₁₂ is the first capacitor plate 21 and the first capacitor plate 21 . The capacitance value formed by the capacitance effect between the two capacitor plates 22 . Therefore, the parameters of one capacitor plate can be fixed and the other capacitor plate can be flexibly designed. This needs to be considered when using one of the capacitor plates to couple with other electrical component structures. For example, when using one of the capacitor plates to couple with a reading resonant cavity located on an opposite surface, it needs to be determined based on the coupling parameters. Therefore, the degree of flexibility in design is very high. important.

It should be noted that in the embodiment of the present application, the structural form of the superconducting qubit circuit formed with a first partial circuit surrounding the first region and a second partial circuit surrounding the second region may not be limited to the above description.

In order to facilitate understanding, Embodiment 2 will now be described from another perspective. It should be understood that in the following description, the superconducting qubit structure is equivalent to the quantum chip in the second embodiment above, and the first capacitor plate is equivalent to the first capacitor in the second embodiment above. The capacitor plate and the second capacitor plate are equivalent to the second capacitor plate in the second embodiment.

Referring to FIG. 6 , an embodiment of the present application provides a superconducting qubit structure, including a first capacitor plate 21 and a first capacitor plate 22 , as well as a first Josephson junction 11 and a second Josephson junction 12 . Wherein, the first capacitor plate 21 and the second capacitor plate are separated by 2, and the first capacitor plate 22 surrounds the first capacitor plate 21, and the first Josephson junction 11 and the second Josephson junction 12 are One end is connected to the first capacitor plate 21 , and the other end is connected to the first capacitor plate 22 . The superconducting qubit structure in the embodiment of the present application is a thin film circuit structure formed on a substrate, and can be prepared and formed using a semiconductor process. The first capacitor plate 21 is formed in the first region of the substrate, and the first capacitor plate 22 is formed Correspondingly, the second area is separated from the first area, and the second area surrounds the first area.

As shown in FIG. 6 , the first end of the first Josephson junction 11 is connected to the first capacitor plate 21 , and the second end of the first Josephson junction 11 is connected to the first capacitor plate 22 . The first end of the second Josephson junction 12 is connected to the first capacitor plate 21 , the second end of the second Josephson junction 12 is connected to the first capacitor plate 22 , and on the first capacitor plate A magnetic flux control signal line 4 and a pulse control signal line 5 are arranged near 22 . In order to facilitate the description of the embodiments of this application, Q ₁ and Q ₂ are used to represent each superconducting qubit structure formed on the substrate in Figure 6 , where the superconducting qubit structure Q ₁ and the superconducting qubit structure Q ₂ represent Each qubit of includes a first capacitor plate 21 and a second capacitor plate 1. The first capacitor plate 21 and the second capacitor plate 1 are not directly connected to the ground plane (GND), but have a The appropriate gap and the physical size of the gap are designed and determined according to the performance parameters of the quantum chip. It should be noted that the capacitance C 01 is formed between the first capacitor plate 21 and the ground plane (GND), and the capacitor C ₀₁ is formed between the first capacitor plate 21 and the ground plane. (GND), and a capacitor C ₁₂ is formed between the first capacitor plate _{21 and the second capacitor plate 12. The values of capacitor C 01 ,} capacitor C ₀₂ and capacitor C ₁₂ can be calculated and determined according to the performance parameters of the quantum chip. Then, the physical sizes of the first capacitor plate 21 and the first capacitor plate 22 are calculated and determined. And the physical size of the capacitor arm 220 and the spacing between Q ₁ and Q ₂ can be determined according to parameter requirements such as the coupling emphasis of Q ₁ and Q ₂ .

In order to solve the problem that the qubit structure in the related art is extremely susceptible to the influence of magnetic flux noise, causing the qubit frequency to deviate from the ideal position, in the superconducting qubit structure provided in the embodiment of the present application, the first Josephson junction 11 and the second One end of the Josephson junction 12 is connected to the first capacitor plate 21 and the other end is connected to the first capacitor plate 22 , thereby connecting the first capacitor plate 21 and the first capacitor plate 22 surrounding the first capacitor plate 21 Two loops are formed by division. As shown in FIG. 6 , one loop is formed by the first Josephson junction 11 and the second Josephson junction 12 as well as the upper part of the first capacitor plate 21 and the upper part of the first capacitor plate 22 . The other loop is formed by the first Josephson junction 11 and the second Josephson junction 12 . The loop is formed by the first Josephson junction 11 and the second Josephson junction 12 and the lower parts of the first capacitive plate 21 and the first capacitive plate 22 . Referring to the magnetic flux control diagram in Figure 6, when the current I is used to regulate the magnetic flux to control the frequency of the qubit, the current noise i brought into the magnetic flux noise generates a magnetic field in one direction in the area of the qubit circuit, and then in the two loops Induced currents i ₁ and i ₂ are formed in opposite directions. The opposite induced currents can offset to a certain extent, which reduces the impact of noise on the deviation of the qubit frequency, thus helping to control the frequency of the qubit at the ideal position. . Therefore, the superconducting qubit structure provided by the embodiments of the present application helps to suppress the impact of magnetic flux noise on the operational accuracy of the qubit, and more accurately controls the frequency of the qubit at a position that is insensitive to magnetic flux.

In some embodiments of the present application, at least one of the first capacitor plate 21 and the first capacitor plate 22 may be an annular film, as shown in FIG. 8 . During specific implementation, the first capacitor plate 21 and the first capacitor plate 22 are not limited to the above shapes, as long as the first capacitor plate 22 can surround the first capacitor plate 21, as shown in Figure 7 . In other embodiments of the present application, the first capacitor plate 21 may also be a circular film, as shown in Figures 9, 10, 11 and 12. It can be understood that annular films and circular films are thin film electrical structures with an annular or circular pattern formed on a substrate. The superconducting qubit structure of the embodiment of the present application can be obtained by depositing, patterning, etc. the superconducting material directly using mature semiconductor processes. The thickness of the deposition can be micron or nanometer, and the superconducting material can be at or below the critical level. At a temperature of about 10-100 millikelvin (mK) or about 4K, materials that exhibit superconducting properties, such as aluminum, niobium, tantalum or titanium nitride, etc., the specific implementation is not limited to these types, Materials that exhibit superconducting properties at temperatures equal to or lower than the critical temperature can be used to form the thin film electrical structure, for example, aluminum (Al), niobium (Nb), niobium nitride (NbN), titanium nitride (TiN) ) and one or more of niobium titanium nitride (NbTiN).

Combined with Figure 6 and compared with Figure 8, in order to further facilitate the coupling between qubits, or to form coupling with other electrical components on the quantum chip, in some embodiments of the present application, the first capacitor plate 22 A capacitor arm 220 for coupling is formed on the capacitor arm 220. The capacitor arm 220 is coupled to the adjacent magnetic flux control signal line 4 and/or the pulse control signal line 6, and can also be used to promote the coupling between Q ₁ and Q ₂ . Or coupling with circuit structures such as read resonant cavities.

In some embodiments of the present application, the superconducting qubit structure also includes a magnetic flux control signal line 4. As shown in FIGS. 9 to 12, the first capacitor plate 21 surrounds the magnetic flux control signal line 4. , it should be noted that a mature semiconductor process can be directly used to form a signal transmission line, and a part of the signal transmission line is surrounded by the first capacitor plate 21 as the magnetic flux control signal line 4 . In one embodiment, the magnetic flux control signal line 4 includes at least 1 turn of coil. As shown in Figure 9, the two ends of the coil can be electrically connected to the signal transmission line on the other surface of the substrate through a TSV-based superconducting pillar. Physically connected, a signal transmission line is used to transmit the magnetic flux control signal from the other surface of the substrate to the coil to achieve magnetic flux control of the qubit. For example, as shown in FIG. 10 and FIG. 11 , the magnetic flux control signal line 4 may include a first coil 41 and a second coil 42 , and the first coil 41 and the second coil 42 are arranged alternately, The current directions of the first coil 41 and the second coil 42 are opposite. The first coil 41 and the second coil 42 may be formed by two relatively independent transmission lines wound along different directions (as shown in FIG. 10 ), or they may be formed by the same transmission line wound along different directions (as shown in FIG. 10 ). As shown in Figure 11), it is easy to adjust the mutual inductance intensity and magnetic field flux.

As shown in FIG. 12 , in some examples, the magnetic flux control signal line 4 includes a first coil 41 and a second coil 42 connected in series and with opposite winding directions, and the entire second coil 42 is located on the within the entire first coil 41 . It can be understood that the magnetic flux control signal line 4 includes two parts connected in series, one part forming the first coil 41 and the other part forming the second coil 42 . In view of the fact that when the overall winding direction of the coil is consistent, the central magnetic field is strong and the peripheral magnetic field is weak, which can easily cause the magnetic field of the squid structure of each qubit on the quantum chip to be uneven. In this embodiment, the two winding directions are opposite. Some coils are arranged in series and adopt the form of the entire second coil 42 being located inside the entire first coil 41, which can relatively weaken the central magnetic field and strengthen the peripheral annular magnetic field, helping to achieve a certain degree of uniformity, or when desired. area to achieve acceptable uniformity. It can be understood that in the embodiment of the present application, the first coil 41 and the second coil 42 connected in series and with opposite winding directions can also be the above-mentioned thin film circuits, and the first coil 41 and the second coil 42 can be formed by photolithography. , electroplating and other processes introduced above are simultaneously prepared and formed. As shown in FIG. 12 , the magnetic flux control signal line 4 formed on the substrate includes a transfer point. The transfer point 43 divides the signal line into two parts, one part forming the first coil 41 and the other part forming the first coil 41 . In the second coil 42 , the winding direction of the signal line in the first coil 41 is opposite to the winding direction of the signal line in the second coil 42 , and the first coil 41 and the second coil 42 are connected in series at the transfer point 43 .

In other embodiments of the present application, the first capacitor plate 21 and the first capacitor plate 22 are symmetrical along the connection line of the first Josephson junction 11 and the second Josephson junction 12 The distribution, that is, the film patterns of the first capacitor plate 21 and the first capacitor plate 22 are in an axially symmetrical form. In other embodiments of the present application, the geometric center of the first capacitor plate 21 is at the same position as the geometric center of the first capacitor plate 22 . It should be noted that the specific The application is not limited to this. The geometry of the first capacitor plate 21 and the first capacitor plate 22 and the distribution relative to the first Josephson junction 11 and the second Josephson junction 12 affect the two loops. The size of the induced current. During specific implementation, the geometric shapes of the first capacitive plate 21 and the first capacitive plate 22 and their relative positions relative to the first Josephson junction 11 can be adjusted according to the relative sizes of the induced currents of the two loops. and the second Josephson junction 12 distributed positions.

In other embodiments of the present application, the ground capacitance C ₀₁ of the first capacitor plate 21 and the ground capacitance C 02 of the first capacitor plate ₂₂ satisfy the following relationship: 100C ₀₁ ≤ _{C 02} , or 100C ₀₂₂ ≤C ₀₁ . according to The corresponding equivalent bit capacitance in the qubit circuit is C _q ≈C ₁₂ +C ₀₁ , or C _q ≈C ₁₂ +C ₀₂ . Therefore, the parameters of one capacitive plate can be fixed and another capacitive plate can be designed flexibly. This needs to be considered when using one of the capacitive plates to couple with other electrical component structures. For example, when using one of the capacitive plates to couple with a read resonant cavity located on a different surface, it needs to be determined based on the coupling parameters. Therefore, the degree of flexible design is very important.

The function of the read resonant cavity in the quantum chip is to read the information of the qubits, for example, by reading the information of the qubits in a non-destructive reading manner. In some embodiments, the read resonant cavity can be arranged on the capacitor arm 220 The adjacent position forms a coupling with the capacitive arm. In other embodiments of the present application, the qubit circuit is formed on the first surface (for example, the top surface) of the substrate, the first capacitor plate 21 is an annular film, and an area surrounded by the annular film is formed. Coupling capacitor, the read resonant cavity is formed on the second surface (for example, the bottom surface) of the substrate, one end of the read resonant cavity is connected to the coupling capacitor through a dielectric element, and the other end is connected to the read signal line, the dielectric The element penetrates the first surface (eg, top surface) and the second surface (eg, bottom surface) of the substrate and is electrically and physically connected to the coupling capacitor and one end of the read chamber. The dielectric elements may be formed by photolithography, electroplating, etc., and patterned accordingly. In some embodiments, the first capacitive plate 21 is not limited to an annular film, and one end of the reading resonant cavity can also be directly coupled to the first capacitive plate 21 through a dielectric element.

Embodiment 3: An embodiment of a quantum chip using four capacitor plates

Figure 13 is a schematic structural diagram of a quantum chip using four capacitor plates in this application. Q ₁ and Q ₂ represent two qubits located on the quantum chip.

As shown in FIG. 13 , in an embodiment of the present application, the superconducting qubit circuit includes a first Josephson junction 11 and a second Josephson junction 12 , a first capacitor plate 21 and a second capacitor plate 22 , and a third capacitor plate 23 and a fourth capacitor plate 24, wherein the first capacitor plate 21 and the second capacitor plate 22 are independently located at both ends of the first Josephson junction 11 , the third plate 23 and the fourth plate 24 are independently located at both ends of the second Josephson junction 12 , and the first capacitor plate 21 and the fourth capacitor plate 24 non-contact cross-electrical connection between the second capacitor plate 22 and the third capacitor plate 23 . It can be understood that the non-contact cross electrical connection can be formed using the electrical connection structure described above.

The method embodiment of the present application is described in detail above with reference to FIGS. 1 to 13 , and the device embodiment of the present application is described in detail below with reference to FIG. 14 . It should be understood that the description of the method embodiments corresponds to the description of the device embodiments. Therefore, the parts not described in detail can be referred to the previous method embodiments.

Figure 14 is a schematic structural diagram of an embodiment of the magnetic flux control signal line of the present application.

As shown in FIG. 14 , in the quantum chip provided by the embodiment of the present application, the magnetic flux control signal line 4 and the superconducting qubit circuit can be formed on the same surface or on different surfaces. When the magnetic flux control signal line and the superconducting qubit circuit are formed on the same surface, the magnetic flux control signal line may also be located on one side of the superconducting qubit circuit. When the magnetic flux control signal line and the superconducting qubit circuit are formed on different surfaces, the magnetic flux control signal line and the superconducting qubit circuit can be independently formed on the top surface of the same substrate. The surface and the bottom surface may also be formed on the bottom surface of one substrate and the other on the top surface of another substrate, and the bottom surface of one substrate faces the top surface of the other substrate. In some embodiments, the flux control signal line 4 includes a coil. Exemplarily, the coils include a first coil 41 and a second coil 42, and the first coil 41 and the second coil 42 are arranged alternately. The currents of the first coil 41 and the second coil 42 are In the opposite direction.

Embodiments of the present application also provide a quantum computer. The quantum computer includes a quantum chip, and the quantum chip is provided with at least the superconducting qubit structure described in the embodiments of the present application.

It should be pointed out here that the quantum chip in the above quantum computer is similar to the above structure and has the same beneficial effects as the above quantum chip embodiment, so no further description is given. For technical details not disclosed in the embodiments of the quantum computer of this application, those skilled in the art should refer to the description of the above quantum chip embodiments to understand them. To save space, they will not be described again here.

The fabrication of a quantum chip provided by embodiments of the present application may require deposition of one or more materials, such as superconductors, dielectrics and/or metals. Depending on the materials selected, these materials may be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (eg, evaporation or sputtering), or epitaxial techniques, as well as other deposition processes. The fabrication process of the quantum chip described in the embodiments of this application may require the removal of one or more materials from the device during the manufacturing process. Depending on the material to be removed, the removal process may include, for example, wet etching techniques, dry etching techniques, or lift-off processes. Materials forming circuit elements described herein may be patterned using known lithographic techniques (eg, photolithography or electron beam exposure).

The structure, features and effects of the present application have been described in detail based on the embodiments shown in the drawings. The above descriptions are only preferred embodiments of the present application. However, the scope of implementation of the present application is not limited by the drawings. Any changes made to the concept of this application, or modifications to equivalent embodiments with equivalent changes, shall be within the protection scope of this application as long as they do not exceed the spirit covered by the description and drawings.

It should be understood that the terms "system" and "network" may be used interchangeably in this application. In addition, the terms used in this application are only used to explain specific embodiments of the application and are not intended to limit the application. The terms “first”, “second”, “third” and “fourth” in the description, claims and drawings of this application are used to distinguish different objects, rather than to describe a specific sequence. . Furthermore, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

In the embodiment of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B only based on A. B can also be determined based on A and/or other information.

In the embodiments of this application, the term "correspondence" can mean that there is a direct correspondence or indirect correspondence between the two, or it can also mean that there is an association between the two, or it can also mean indicating and being instructed, configuring and being configured, etc. relation.

The term "and/or" in the embodiment of this application is only an association relationship describing associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A exists alone, and A and B exist simultaneously. , there are three situations of B alone. In addition, the character "/" in this article generally indicates that the related objects are an "or" relationship.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. In another point, the coupling or direct coupling or communication connection between each other shown or discussed may be through some interfaces, devices or units. Continuous coupling or communication connection, which may be electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, each unit can exist physically alone, or two or more units can be integrated into one unit.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, e.g., the computer instructions may be transferred from a website, computer, server, or data center Transmission to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that can be read by a computer or a data storage device such as a server or data center integrated with one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVD)) or semiconductor media (e.g., solid state disks (SSD) )wait.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (21)

1. A quantum chip is characterized by including:

   A superconducting qubit circuit forming a first portion of the circuit surrounding the first region and a second portion of the circuit surrounding the second region; and,

   A magnetic flux control signal line is coupled to the superconducting qubit circuit. The control signal applied by the magnetic flux control signal line obtains induced currents in opposite directions in the first part of the circuit and the second part of the circuit.
2. The quantum chip according to claim 1, characterized in that the superconducting qubit circuit includes:

   capacitor plates; and

   The first Josephson knot and the second Josephson knot, the first Josephson knot and the second Josephson knot are connected in parallel, and one end of the first Josephson knot and one end of the second Josephson knot are both Connected to the capacitor plate, the other end of the first Josephson junction and the other end of the second Josephson junction are interconnected and grounded.
3. The quantum chip according to claim 2, wherein the superconducting qubit circuit includes a first electrical connection structure, and the other end of the first Josephson junction and the other end of the second Josephson junction pass through The first electrical connection structures are interconnected, and the first electrical connection structures intersect with the capacitor plate in a non-contact manner.
4. The quantum chip according to claim 2 or 3, characterized in that the superconducting qubit circuit includes a first electrical connection structure and a second electrical connection structure, one end of the first Josephson junction and the second One end of the Josephson junction is connected through the first electrical connection structure, the other end of the first Josephson junction and the other end of the second Josephson junction are connected through the second electrical connection structure, and the third The two electrical connection structures intersect with the first electrical connection structure in a non-contact manner.
5. The quantum chip according to claim 1, characterized in that the superconducting qubit circuit includes:

   first capacitor plate and second capacitor plate; and

   A first Josephson junction and a second Josephson junction. One end of the first Josephson junction and one end of the second Josephson junction are both connected to the first capacitor plate, and the first Josephson junction The other end of the second Josephson junction and the other end of the second Josephson junction are both connected to the second capacitor plate.
6. The quantum chip according to claim 5, characterized in that the first capacitor plate and the second capacitor plate are arranged separately.
7. The quantum chip according to claim 5 or 6, characterized in that the first capacitor plate and the second capacitor plate intersect in a non-contact manner.
8. The quantum chip according to any one of claims 5 to 7, characterized in that the second capacitor plate surrounds the first capacitor plate, and the first region and the second region are located at between the second capacitor plate and the first capacitor plate.
9. The quantum chip according to any one of claims 5 to 8, characterized in that the first capacitor plate and the second capacitor plate are formed along the first Josephson junction and the second Josephson junction. The connection lines of the forest knot are all symmetrically distributed.
10. The quantum chip according to any one of claims 5 to 9, characterized in that the geometric center of the first capacitor plate overlaps the geometric center of the second capacitor plate.
11. The quantum chip according to any one of claims 5 to 10, characterized in that the ground capacitance C ₀₁ of the first capacitor plate and the ground capacitance C ₀₂ of the second capacitor plate satisfy the following relationship : 100C ₀₁ ≤ C ₀₂ , or 100C ₀₂ ≤ _{C 01} .
12. The quantum chip according to any one of claims 5 to 11, characterized in that the second capacitor plate It is an annular membrane.
13. The quantum chip according to any one of claims 5 to 12, characterized in that a capacitor arm for coupling is formed on the second capacitor plate.
14. The quantum chip according to any one of claims 5 to 13, characterized in that the first capacitor plate is an annular film or a circular film.
15. The quantum chip according to any one of claims 5 to 14, characterized in that the first capacitor plate surrounds the magnetic flux control signal line.
16. The quantum chip according to claim 1, characterized in that the superconducting qubit circuit includes:

    First Josephson Knot and Second Josephson Knot;

    A first capacitor plate and a second capacitor plate, the first capacitor plate and the second capacitor plate are independently located at both ends of the first Josephson junction; and,

    A third capacitor plate and a fourth capacitor plate, the third capacitor plate and the fourth capacitor plate are independently located at both ends of the second Josephson junction;

    And there is a non-contact cross electrical connection between the first capacitor plate and the fourth capacitor plate, and between the second capacitor plate and the third capacitor plate.
17. The quantum chip according to any one of claims 1 to 16, characterized in that the magnetic flux control signal line and the superconducting qubit circuit are formed on the same surface, and the magnetic flux control signal line is located on the same surface. One side of the superconducting qubit circuit.
18. The quantum chip according to any one of claims 1 to 17, characterized in that the magnetic flux control signal line and the superconducting qubit circuit are formed on different surfaces.
19. The quantum chip according to any one of claims 1 to 18, characterized in that the magnetic flux control signal line includes a coil.
20. The quantum chip according to any one of claims 1 to 19, wherein the coil includes a first coil and a second coil, and the first coil and the second coil are arranged alternately, and the third coil The current directions of one coil and the second coil are opposite.
21. A quantum computer, characterized in that the quantum computer is equipped with the quantum chip according to any one of claims 1-20.