CN215729467U - Biasing circuit structure applied to various voltages - Google Patents

Abstract

The utility model provides a bias circuit structure applied to various voltages, which belongs to the technical field of electronic circuits and comprises a first current reference module and a second current reference module, wherein the first current reference module changes along with the voltage of a power supply; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; the output end of the first current reference module and the output end of the second current reference module are in a parallel connection structure, and the output end of the first current reference module and the output end of the second current reference module which are connected in parallel are used as the output end of the bias circuit structure. The utility model realizes that the bias current has certain correlation with the voltage, and the change is small along with the temperature change and is insensitive to the temperature.

Description

Biasing circuit structure applied to various voltages

Technical Field

The utility model belongs to the technical field of electronic circuits, and particularly relates to a biasing circuit structure applied to various voltages.

Background

Any circuit system needs to work at a stable working point, which is called as a static working point in the utility model. Such a module is required in the circuitry to provide a bias current or bias voltage. For example, cascode transistors in a cascode structure need voltage bias to ensure operation in an amplification region, the operational amplifier and the comparator need a tail current of a PTAT to bias a static operating point, and a bias circuit including a start-up circuit is also needed to avoid a zero state when a reference voltage source is started. In the chip circuit design, the reference source is related to the success or failure of the integrated circuit design, the power supply voltage provided by an external power supply system is often taken from an adapter, not only contains noise, but also is difficult to provide a reference for a chip with special needs, so the reference source can only be generated by a chip internal circuit.

The reference sources are mainly a current source and a voltage source. In integrated circuits, the most common voltage reference is the Bandgap reference Bandgap, which can provide a high precision voltage of around 1.25V. At present, many researches on Bandgap are carried out, the technology is mature, and after technical compensation, the temperature coefficient in the temperature range of-45 ℃ to 125 ℃ can be 3 ppm/DEG C when the power supply voltage range is wide. Therefore, Bandgap can be made insensitive to power supply and voltage. The current reference is also one of the most commonly used modules in integrated circuit design, and for the current reference, the current reference is mostly obtained by dividing a Bandgap voltage reference by a resistor with an accurate resistance value and then is mirrored into each module through a current mirror, so that the obtained current can introduce a temperature coefficient, and the reference is sensitive to temperature. Two bias circuits which are independent from and related to a power supply are commonly used, the bias circuit related to the power supply introduces a resistor in the circuit, and the resistor has a first-order temperature coefficient, and a second-order temperature coefficient or even a higher-order temperature coefficient, so that the bias voltage output by the circuit is greatly influenced by temperature, and the temperature curve of the bias voltage may not meet the requirements in the circuit design. The bias circuit independent of the power supply can adapt to a wider power supply voltage input range. However, the circuit structure also has a temperature coefficient, and cannot achieve a zero temperature coefficient.

SUMMERY OF THE UTILITY MODEL

Aiming at the defects in the prior art, the bias circuit structure applied to various voltages provided by the utility model realizes that the bias current and the voltage have certain correlation, and the change is small along with the temperature change and is insensitive to the temperature.

In order to achieve the above purpose, the utility model adopts the technical scheme that:

the scheme provides a biasing circuit structure applied to various voltages, which comprises a first current reference module changing along with the power supply voltage and a second current reference module not changing along with the power supply voltage; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; the output end of the first current reference module and the output end of the second current reference module are in a parallel connection structure, and the output end of the first current reference module and the output end of the second current reference module which are connected in parallel are used as the output end of the bias circuit structure.

Further, the first current reference module comprises a resistor R1, a capacitor C1, PMOS field effect transistors MP1 and MP2 and NMOS field effect transistors MN1 and MN 2;

one end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is connected with the drain electrode of the NMOS field effect transistor MN1, the gate of the NMOS field effect transistor MN1 is respectively connected with the drain of the NMOS field effect transistor MN1 and the gate of the NMOS field effect transistor MN2, the source electrode of the NMOS field effect transistor MN1 is grounded, the source electrode of the NMOS field effect transistor MN2 is grounded, the drain electrode of the NMOS field effect transistor MN2 is connected with the drain electrode of the PMOS field effect transistor MP1, the source electrode of the PMOS field effect transistor MP1 is connected with a power supply, the grid electrode of the PMOS field effect transistor MP1 is respectively connected with one end of a capacitor C1, the grid electrode of the PMOS field effect transistor MP2 and the drain electrode of an NMOS field effect transistor MN2, the other end of the capacitor C1 is connected with a power supply, the drain electrode of the PMOS field effect transistor MP2 is the output end of the first current reference module, and the source electrode of the PMOS field effect transistor MP2 is connected with a power supply.

Still further, the second current reference module includes a start-up circuit unit and a core reference unit connected to the start-up circuit unit.

Still further, the starting circuit unit comprises a resistor R2, a PMOS field effect transistor MP3 and NMOS field effect transistors MN3 and MN 4;

the source electrode of PMOS field effect transistor MP3 is connected with the power supply, the grid electrode of PMOS field effect transistor MP3 is connected with the one end of resistance R2, resistance R2's other end ground connection, PMOS field effect transistor MP 3's drain electrode respectively with NMOS field effect transistor MN 4's grid and NMOS field effect transistor MN 3's drain electrode is connected, NMOS field effect transistor MN 3's source electrode ground connection, NMOS field effect transistor MN 4's source electrode ground connection, NMOS field effect transistor MN 4's drain electrode and NMOS field effect transistor MN 3's grid all with the core reference cell is connected.

Still further, the core reference unit comprises a capacitor C2, a resistor R3, PMOS field effect transistors MP4-MP9 and NMOS field effect transistors MN5-MN 11;

the source electrode of the PMOS field effect transistor MP4 is connected with a power supply, the grid electrode of the PMOS field effect transistor MP4 is respectively connected with the drain electrode of the NMOS field effect transistor MN4, the grid electrode of the PMOS field effect transistor MP5, the grid electrode of the PMOS field effect transistor MP6 and the grid electrode of the PMOS field effect transistor MP7, the drain electrode of the PMOS field effect transistor MP4 is respectively connected with the drain electrode of the NMOS field effect transistor MN5, the grid electrode of the NMOS field effect transistor MN3, the grid electrode of the NMOS field effect transistor MN5, the grid electrode of the NMOS field effect transistor MN6 and the grid electrode of the NMOS field effect transistor MN8, the source electrode of the NMOS field effect transistor MN5 is grounded, the source electrode of the NMOS field effect transistor MN6 is connected with the drain electrode of the NMOS field effect transistor MN7, the source electrode of the NMOS field effect transistor MN8 is connected with the drain electrode of the NMOS field effect transistor MN9, the source electrode of the PMOS field effect transistor MP5 is connected with a power supply, and the drain electrode of the PMOS field effect transistor MP5 is respectively connected with the drain electrode of the NMOS field effect transistor MN6, the grid electrode of the NMOS field effect transistor MN7 and the grid electrode of the NMOS field effect transistor MN9, the source of the NMOS field effect transistor MN7 is grounded, the source of the NMOS field effect transistor MN9 is connected with one end of the resistor R3, the other end of the resistor R3 is grounded, the source of the PMOS field effect transistor MP6 is connected with a power supply, the drain of the PMOS field effect transistor MP6 is connected with the drain of the NMOS field effect transistor MN8, the source of the NMOS field effect transistor MN8 is connected with the drain of the NMOS field effect transistor MN9, the source of the PMOS field effect transistor MP7 is connected with the power supply, the drain of the PMOS field effect transistor MP7 is connected with the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN 6329 respectively, the source of the NMOS field effect transistor MN10 is grounded, the source of the NMOS field effect transistor MP 42 is grounded, the drain of the NMOS field effect transistor MP 11 is connected with the drain of the PMOS field effect transistor MP8, the source of the PMOS field effect transistor MP8 is connected with the power supply, the gate of the PMOS field effect transistor MP5 is connected with the gate of the PMOS field effect transistor MN 3923 and the capacitor 5857324, the other end of the capacitor C2 is connected with a power supply, the source electrode of the PMOS field-effect transistor MP9 is connected with the power supply, and the drain electrode of the PMOS field-effect transistor MP9 is the output end of the second current reference module and is connected with the drain electrode of the PMOS field-effect transistor MP2 in parallel.

Still further, the PMOS fet MP5 and the PMOS fet MP6 are current mirrors; the NMOS field effect transistor MN6, the NMOS field effect transistor MN7, the NMOS field effect transistor MN8 and the NMOS field effect transistor M9 are of a cascode structure.

The utility model has the beneficial effects that:

(1) the utility model provides a bias circuit structure applied to various voltages, which adopts a novel current reference combination structure and mainly aims at some special circuit requirements, namely wide power supply voltage and requirement that internal bias current has certain correlation with the power supply voltage and has good temperature coefficient. Under the condition of various power supply voltages, the utility model not only can ensure certain relativity to the power supply, but also can ensure certain temperature characteristics, and the implementation scheme is simple.

(2) The first current reference module generates a current which varies with the power supply voltage, i.e. the current is sensitive to the power supply voltage and is a negative temperature coefficient current due to the temperature coefficient of the resistor. The second current reference module generates a path of current which is not changed along with the power supply voltage, namely, the current is insensitive to the power supply voltage and has a positive temperature coefficient.

(3) In application, different power supply voltage sensitivities are needed, and the Multiplier of the MOS tube can be adjusted to realize the purpose.

Drawings

Fig. 1 is a schematic circuit diagram of a first current reference module according to the present invention.

Fig. 2 is a schematic circuit diagram of a second current reference module according to the present invention.

FIG. 3 is a diagram illustrating the temperature profile of the present embodiment.

Detailed Description

The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the utility model as defined and defined in the appended claims, and all changes that come within the meaning and range of equivalency of the claims are to be embraced therein.

Examples

The bias circuit refers to a circuit capable of providing stable and accurate voltage bias or current bias when a manufacturing process, a system supply voltage, and an external temperature change, and is widely applied to various electronic circuits, including an analog circuit, a digital-analog hybrid circuit, a pure digital circuit, and the like. The utility model provides a bias circuit applied to various voltages, which adopts a novel combined structure, realizes that the bias current and the voltage have certain correlation aiming at some special circuits, and has small change along with the temperature change and is insensitive to the temperature. As shown in fig. 1-2, the circuit comprises a first current reference module which changes with the power supply voltage and a second current reference module which does not change with the power supply voltage; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; the output end of the first current reference module and the output end of the second current reference module are in a parallel connection structure, and the output end of the first current reference module and the output end of the second current reference module which are connected in parallel are used as the output end of the bias circuit structure.

As shown in fig. 1, the first current reference module includes a resistor R1, a capacitor C1, PMOS fets MP1 and MP2, and NMOS fets MN1 and MN 2; one end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is connected with the drain electrode of the NMOS field effect transistor MN1, the gate of the NMOS field effect transistor MN1 is respectively connected with the drain of the NMOS field effect transistor MN1 and the gate of the NMOS field effect transistor MN2, the source electrode of the NMOS field effect transistor MN1 is grounded, the source electrode of the NMOS field effect transistor MN2 is grounded, the drain electrode of the NMOS field effect transistor MN2 is connected with the drain electrode of the PMOS field effect transistor MP1, the source electrode of the PMOS field effect transistor MP1 is connected with a power supply, the grid electrode of the PMOS field effect transistor MP1 is respectively connected with one end of a capacitor C1, the grid electrode of the PMOS field effect transistor MP2 and the drain electrode of an NMOS field effect transistor MN2, the other end of the capacitor C1 is connected with a power supply, the drain electrode of the PMOS field effect transistor MP2 is the output end of the first current reference module, and the source electrode of the PMOS field effect transistor MP2 is connected with a power supply.

In this embodiment, the first current reference module is designed to generate a negative Temperature Coefficient (TCR) current, which is used to describe the resistance variation with temperature:

wherein the content of the first and second substances,

the rate of change of resistance to temperature is shown, and R represents resistance.

Resistance current I in the first current reference block:

wherein, I_NTCRepresenting the resistor current in the first current reference module, VCC representing the supply voltage, VGS_MN1The gate-source voltage of the NMOS field effect transistor MN1 is shown, and R1 shows a resistor.

Partial derivative of resistance current I in the first current reference module with respect to temperature:

wherein the content of the first and second substances,

representing a first current reference module resistance current I_NTCRegarding the coefficient of deviation of the current temperature, R and R1 both represent resistance, T represents temperature, VGS_MN1Represents the gate-source voltage of the NMOS fet MN1, VCC represents the supply voltage, TCR represents the temperature coefficient,

the temperature coefficient of the current is calculated by representing the change rate of the resistance along with the temperature.

Calculating the temperature coefficient of the current:

wherein the content of the first and second substances,

representing a first current reference module resistance current I_NTCRegarding the coefficient of deviation of the current temperature, R and R1 both represent resistance, T represents temperature, VGS_MN1Represents the gate-source voltage of the NMOS fet MN1, VCC represents the supply voltage, TCR represents the temperature coefficient,

indicating the rate of change of resistance with temperature.

As shown in fig. 2, the second current reference module includes a start-up circuit unit and a core reference unit connected to the start-up circuit unit.

As shown in fig. 2, the start-up circuit unit includes a resistor R2, a PMOS fet MP3, and NMOS fets MN3 and MN 4; the source electrode of PMOS field effect transistor MP3 is connected with the power supply, the grid electrode of PMOS field effect transistor MP3 is connected with the one end of resistance R2, resistance R2's other end ground connection, PMOS field effect transistor MP 3's drain electrode respectively with NMOS field effect transistor MN 4's grid and NMOS field effect transistor MN 3's drain electrode is connected, NMOS field effect transistor MN 3's source electrode ground connection, NMOS field effect transistor MN 4's source electrode ground connection, NMOS field effect transistor MN 4's drain electrode and NMOS field effect transistor MN 3's grid all with the core reference cell is connected.

In this embodiment, since the second current reference module is a self-biased structure, and the structure has a degenerate state, the circuit cannot be self-started, and therefore a start-up circuit needs to be added. In power supply electrification, no current flows through a core reference part, the gate end voltage of an NMOS field effect transistor MN3 is low, an NMOS field effect transistor MN3 is in a closed state, the gate end of a PMOS field effect transistor MP3 is grounded through a resistor, the PMOS field effect transistor MP3 is immediately turned on at the moment, the gate end voltage of the NMOS field effect transistor MN4 is high, an NMOS field effect transistor MN4 is turned on at the moment, the gate end voltages of the PMOS field effect transistors MP5 and MP6 are pulled low after the NMOS field effect transistor MN4 is turned on, the PMOS field effect transistors MP5 and MP6 are turned on at the moment, the current is extracted from a power supply, and the core reference part is normally started. At this time, the gate voltage of the NMOS field effect transistor MN3 rises and exceeds the threshold voltage of the NMOS field effect transistor MN3, the NMOS field effect transistor MN4 is turned on, the gate voltage of the NMOS field effect transistor MN4 is pulled low, and the start-up circuit stops working.

As shown in fig. 2, the core reference cell includes a capacitor C2, a resistor R3, PMOS fets MP4-MP9, and NMOS fets MN5-MN 11; the source electrode of the PMOS field effect transistor MP4 is connected with a power supply, the grid electrode of the PMOS field effect transistor MP4 is respectively connected with the drain electrode of the NMOS field effect transistor MN4, the grid electrode of the PMOS field effect transistor MP5, the grid electrode of the PMOS field effect transistor MP6 and the grid electrode of the PMOS field effect transistor MP7, the drain electrode of the PMOS field effect transistor MP4 is respectively connected with the drain electrode of the NMOS field effect transistor MN5, the grid electrode of the NMOS field effect transistor MN3, the grid electrode of the NMOS field effect transistor MN5, the grid electrode of the NMOS field effect transistor MN6 and the grid electrode of the NMOS field effect transistor MN8, the source electrode of the NMOS field effect transistor MN5 is grounded, the source electrode of the NMOS field effect transistor MN6 is connected with the drain electrode of the NMOS field effect transistor MN7, the source electrode of the NMOS field effect transistor MN8 is connected with the drain electrode of the NMOS field effect transistor MN9, the source electrode of the PMOS field effect transistor MP5 is connected with a power supply, and the drain electrode of the PMOS field effect transistor MP5 is respectively connected with the drain electrode of the NMOS field effect transistor MN6, the grid electrode of the NMOS field effect transistor MN7 and the grid electrode of the NMOS field effect transistor MN9, the source of the NMOS field effect transistor MN7 is grounded, the source of the NMOS field effect transistor MN9 is connected with one end of the resistor R3, the other end of the resistor R3 is grounded, the source of the PMOS field effect transistor MP6 is connected with a power supply, the drain of the PMOS field effect transistor MP6 is connected with the drain of the NMOS field effect transistor MN8, the source of the NMOS field effect transistor MN8 is connected with the drain of the NMOS field effect transistor MN9, the source of the PMOS field effect transistor MP7 is connected with the power supply, the drain of the PMOS field effect transistor MP7 is connected with the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN 6329 respectively, the source of the NMOS field effect transistor MN10 is grounded, the source of the NMOS field effect transistor MP 42 is grounded, the drain of the NMOS field effect transistor MP 11 is connected with the drain of the PMOS field effect transistor MP8, the source of the PMOS field effect transistor MP8 is connected with the power supply, the gate of the PMOS field effect transistor MP5 is connected with the gate of the PMOS field effect transistor MN 3923 and the capacitor 5857324, the other end of the capacitor C2 is connected with a power supply, the source electrode of the PMOS field-effect transistor MP9 is connected with the power supply, and the drain electrode of the PMOS field-effect transistor MP9 is the output end of the second current reference module and is connected with the drain electrode of the PMOS field-effect transistor MP2 in parallel.

In this embodiment, the PMOS fet MP5 and the PMOS fet MP6 are current mirrors; the NMOS field effect transistors MN7 and MN9 flow the same current by adopting a mode of upper-level current mirror.

In this embodiment, the NMOS fet MN6, the NMOS fet MN7, the NMOS fet MN8, and the NMOS fet M9 are cascode structures, which can suppress the channel length modulation effect, and thus the currents flowing through the NMOS fets MN7 and MN9 are more matched.

In this embodiment, the gate-source voltage expression of the NMOS fet MN7 is as follows:

wherein, VGS_MN7Denotes the gate-source voltage of the NMOS field effect transistor MN7, VT denotes the threshold voltage of the NMOS field effect transistor, beta_MN7Representing the gain factor of the NMOS fet MN 7.

The expression of the gate-source voltage of the NMOS field effect transistor MN9 is as follows:

wherein, VGS_MN9Represents the gate-source voltage, beta, of the NMOS field effect transistor MN7_MN9Representing the gain factor of the NMOS fet MN 9.

The current of the second current reference module can be solved:

wherein, I_PTCRepresenting the current of the second current reference module, R3 representing the resistance, β_MN7Denotes the gain factor, β, of the NMOS field effect transistor MN7_MN9Representing the gain factor of the NMOS fet MN 9.

In this embodiment, the first current reference module generates a current that varies with the power supply voltage and is a negative temperature coefficient current. The second current reference module generates a current which is not changed along with the power supply voltage and is a current with a positive temperature coefficient. The utility model combines two paths of current into one path of current, thus obtaining the current with insensitive power supply and insensitive temperature.

In this embodiment, the first current reference block is a simple current reference, the current on the mirror resistor R1 of the MOS transistor is used, the MOS transistor has the same width-to-length ratio, and the current gain of the circuit can be adjusted by changing the Multiplier values of MN1 and MN 2.

In this embodiment, the current gain can be adjusted by changing the Multiplier values of MN1 and MN2 in the first current reference block by changing the resistance values of the resistors R1 and R3 to generate a current different from the example (e.g., 14.475 microamperes for a current at 25 degrees celsius and 5 volts for a power supply).

In this embodiment, the circuit is simulated, as shown in fig. 3, the temperature range is set to-40 ℃ to 105 ℃, it can be seen that the temperature coefficient of the PTC is 9.86n A/° c, the temperature coefficient of the NTC is-10.2 n A/° c, and the temperature coefficient of the resultant current is-0.96 n A/° c.

Claims (6)

1. A bias circuit structure applied to various voltages is characterized by comprising a first current reference module which changes with the supply voltage and a second current reference module which does not change with the supply voltage; the output end of the first current reference module is a current reference NTC with a negative temperature coefficient, and the output end of the second current reference module is a current reference PTC with a positive temperature coefficient; the output end of the first current reference module and the output end of the second current reference module are in a parallel connection structure, and the output end of the first current reference module and the output end of the second current reference module which are connected in parallel are used as the output end of the bias circuit structure.

2. The structure of claim 1, wherein the first current reference block comprises a resistor R1, a capacitor C1, PMOS FETs MP1 and MP2 and NMOS FETs MN1 and MN 2;

one end of the resistor R1 is connected with a power supply, the other end of the resistor R1 is connected with the drain electrode of the NMOS field effect transistor MN1, the gate of the NMOS field effect transistor MN1 is respectively connected with the drain of the NMOS field effect transistor MN1 and the gate of the NMOS field effect transistor MN2, the source electrode of the NMOS field effect transistor MN1 is grounded, the source electrode of the NMOS field effect transistor MN2 is grounded, the drain electrode of the NMOS field effect transistor MN2 is connected with the drain electrode of the PMOS field effect transistor MP1, the source electrode of the PMOS field effect transistor MP1 is connected with a power supply, the grid electrode of the PMOS field effect transistor MP1 is respectively connected with one end of a capacitor C1, the grid electrode of the PMOS field effect transistor MP2 and the drain electrode of an NMOS field effect transistor MN2, the other end of the capacitor C1 is connected with a power supply, the drain electrode of the PMOS field effect transistor MP2 is the output end of the first current reference module, and the source electrode of the PMOS field effect transistor MP2 is connected with a power supply.

3. The bias circuit structure applied to multiple voltages according to claim 2, wherein the second current reference module comprises a start-up circuit unit and a core reference unit connected to the start-up circuit unit.

4. The structure of the bias circuit applied to various voltages of claim 3, wherein the start-up circuit unit comprises a resistor R2, a PMOS FET MP3, and NMOS FETs MN3 and MN 4;

the source electrode of PMOS field effect transistor MP3 is connected with the power supply, the grid electrode of PMOS field effect transistor MP3 is connected with the one end of resistance R2, resistance R2's other end ground connection, PMOS field effect transistor MP 3's drain electrode respectively with NMOS field effect transistor MN 4's grid and NMOS field effect transistor MN 3's drain electrode is connected, NMOS field effect transistor MN 3's source electrode ground connection, NMOS field effect transistor MN 4's source electrode ground connection, NMOS field effect transistor MN 4's drain electrode and NMOS field effect transistor MN 3's grid all with the core reference cell is connected.

5. The structure of claim 4, wherein the core reference cell comprises a capacitor C2, a resistor R3, PMOS FETs MP4-MP9 and NMOS FETs MN5-MN 11;

the source electrode of the PMOS field effect transistor MP4 is connected with a power supply, the grid electrode of the PMOS field effect transistor MP4 is respectively connected with the drain electrode of the NMOS field effect transistor MN4, the grid electrode of the PMOS field effect transistor MP5, the grid electrode of the PMOS field effect transistor MP6 and the grid electrode of the PMOS field effect transistor MP7, the drain electrode of the PMOS field effect transistor MP4 is respectively connected with the drain electrode of the NMOS field effect transistor MN5, the grid electrode of the NMOS field effect transistor MN3, the grid electrode of the NMOS field effect transistor MN5, the grid electrode of the NMOS field effect transistor MN6 and the grid electrode of the NMOS field effect transistor MN8, the source electrode of the NMOS field effect transistor MN5 is grounded, the source electrode of the NMOS field effect transistor MN6 is connected with the drain electrode of the NMOS field effect transistor MN7, the source electrode of the NMOS field effect transistor MN8 is connected with the drain electrode of the NMOS field effect transistor MN9, the source electrode of the PMOS field effect transistor MP5 is connected with a power supply, and the drain electrode of the PMOS field effect transistor MP5 is respectively connected with the drain electrode of the NMOS field effect transistor MN6, the grid electrode of the NMOS field effect transistor MN7 and the grid electrode of the NMOS field effect transistor MN9, the source of the NMOS field effect transistor MN7 is grounded, the source of the NMOS field effect transistor MN9 is connected with one end of the resistor R3, the other end of the resistor R3 is grounded, the source of the PMOS field effect transistor MP6 is connected with a power supply, the drain of the PMOS field effect transistor MP6 is connected with the drain of the NMOS field effect transistor MN8, the source of the NMOS field effect transistor MN8 is connected with the drain of the NMOS field effect transistor MN9, the source of the PMOS field effect transistor MP7 is connected with the power supply, the drain of the PMOS field effect transistor MP7 is connected with the drain of the NMOS field effect transistor MN10, the gate of the NMOS field effect transistor MN10 and the gate of the NMOS field effect transistor MN 6329 respectively, the source of the NMOS field effect transistor MN10 is grounded, the source of the NMOS field effect transistor MP 42 is grounded, the drain of the NMOS field effect transistor MP 11 is connected with the drain of the PMOS field effect transistor MP8, the source of the PMOS field effect transistor MP8 is connected with the power supply, the gate of the PMOS field effect transistor MP5 is connected with the gate of the PMOS field effect transistor MN 3923 and the capacitor 5857324, the other end of the capacitor C2 is connected with a power supply, the source electrode of the PMOS field-effect transistor MP9 is connected with the power supply, and the drain electrode of the PMOS field-effect transistor MP9 is the output end of the second current reference module and is connected with the drain electrode of the PMOS field-effect transistor MP2 in parallel.

6. The structure of bias circuit applied to various voltages according to claim 5, wherein said PMOS FET MP5 and PMOS FET MP6 are current mirrors; the NMOS field effect transistor MN6, the NMOS field effect transistor MN7, the NMOS field effect transistor MN8 and the NMOS field effect transistor M9 are of a cascode structure.

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