CN214122812U

CN214122812U - Reference voltage source integrated device with base current compensation

Info

Publication number: CN214122812U
Application number: CN202120465173.6U
Authority: CN
Inventors: 周号
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2021-03-04
Filing date: 2021-03-04
Publication date: 2021-09-03
Anticipated expiration: 2031-03-04

Abstract

The present disclosure provides a reference voltage source integrated device with base current compensation, including: the base of the reference voltage generation module is used for outputting reference voltage; the base current compensation module generates base compensation current and outputs the base compensation current to the base of the reference voltage generation module so as to offset the base current of the base of the reference voltage source generation module, so that the reference voltage generation module outputs compensated reference voltage; and the reference voltage output module comprises a voltage adjusting submodule which can increase the compensated reference voltage to a preset voltage.

Description

Reference voltage source integrated device with base current compensation

Technical Field

The disclosure belongs to the technical field of reference voltage sources, and particularly relates to a reference voltage source integrated device with base current compensation.

Background

Reference voltage sources are widely used in integrated devices (e.g., integrated circuit chips) because they are capable of generating accurate and stable reference voltages.

However, the reference voltage source in the prior art still has the problem of low precision due to the influence of external factors of the voltage source or circuit structure.

SUMMERY OF THE UTILITY MODEL

To address at least one of the above technical problems, the present disclosure provides a reference voltage source integrated device with base current compensation.

The reference voltage source integrated device with base current compensation is realized by the following technical scheme.

A reference voltage source integrated device with base current compensation comprises:

a reference voltage generating module, a base of which is used for outputting a reference voltage; a base current compensation module, wherein the base current compensation module generates a base compensation current and outputs the base compensation current to the base of the reference voltage generation module to offset the base current of the base of the reference voltage source generation module, so that the reference voltage generation module outputs a compensated reference voltage; and the reference voltage output module comprises a voltage adjusting submodule which can increase the compensated reference voltage to a preset voltage.

According to at least one embodiment of the present disclosure, the reference voltage source integrated device with base current compensation includes a third resistor, a fourth resistor, and a first buffer, a first end of the third resistor is connected to ground, a second end of the third resistor is connected to a first end of the fourth resistor, a second end of the fourth resistor is connected to a first end of the first buffer, a second end of the first buffer is connected to a device voltage end of the reference voltage source integrated device, a second end of the third resistor is connected to a base of the reference voltage generation module, and a second end of the fourth resistor outputs the predetermined voltage.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the predetermined voltage can be adjusted by a ratio of the third resistor to the fourth resistor.

The integrated device of reference voltage source with base current compensation according to at least one embodiment of the present disclosure, the base current compensation module comprises a first current mirror image module, a second current mirror image module and a first compensation triode, the first current mirror module mirrors a bias current of the reference voltage integrated device to M times, m is a natural number which is more than or equal to 1, so that the emitter current of the first compensation triode is M times of the bias current and the base current of the first compensation triode is M IPTAT/Beta, the Beta is a current amplification coefficient of the first compensation triode, the second current mirror module mirrors the base current of the first compensation triode, the mirror image is M IPTAT/Beta, and the base current is output to the base of the reference voltage generation module as the base compensation current.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of this disclosure, base current compensation module includes first current mirror module, second current mirror module and first compensation triode, first current mirror module mirrors the bias current IPTAT of reference voltage integrated device for twice, 2 IPTAT makes the emitter current of first compensation triode be twice of bias current and the base current of first compensation triode is 2 IPTAT/Beta, wherein Beta is the current amplification coefficient of first compensation triode, second current mirror module mirrors the base current of first compensation triode, mirrors for 2 IPTAT/Beta, as the base compensation current is exported to the base of reference voltage generation module.

According to at least one embodiment of the present disclosure, the first current mirror module includes a third N-type field effect transistor and a fourth N-type field effect transistor, a first end of the third N-type field effect transistor is grounded, a first end of the fourth N-type field effect transistor is grounded, a control end of the third N-type field effect transistor is connected to a control end of the fourth N-type field effect transistor, a second end of the third N-type field effect transistor is connected to a control end of the third N-type field effect transistor, a second end of the third N-type field effect transistor inputs a bias current, and a second end of the fourth N-type field effect transistor is connected to an emitter of the first compensation triode.

The integrated device of reference voltage source with base current compensation according to at least one embodiment of the present disclosure, the second current mirror module comprises a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor, the first end of the eighth P-type field effect transistor is connected with the base electrode of the first compensation triode, the second end of the eighth P-type field effect transistor is connected with the first end of the tenth P-type field effect transistor, the second end of the tenth P-type field effect transistor is connected with the device voltage end of the reference voltage source integrated device, the second end of the ninth P-type field effect transistor is connected with the device voltage end of the reference voltage source integrated device, a first end of the ninth P-type field effect transistor is connected with a second end of a seventh P-type field effect transistor, and a first end of the seventh P-type field effect transistor is connected with a base electrode of the reference voltage generation module;

the control end of the seventh P-type field effect transistor is connected with the control end of the eighth P-type field effect transistor, and the control end of the ninth P-type field effect transistor is connected with the control end of the tenth P-type field effect transistor;

and the first end of the eighth P-type field effect transistor is connected with the control end of the tenth P-type field effect transistor.

According to the reference voltage source integrated device with the base current compensation, the ratio of the channel width-length ratio of the third N-type field effect transistor to the channel width-length ratio of the fourth N-type field effect transistor is 1: 2.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the channel area width-to-length ratio of the seventh P-type field effect transistor is the same as the channel width-to-length ratio of the eighth P-type field effect transistor, and the channel width-to-length ratio of the ninth P-type field effect transistor is the same as the channel width-to-length ratio of the tenth P-type field effect transistor.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the base current compensation module further includes a second buffer, a first end of the second buffer is connected to the collector of the first compensation triode, a second end of the second buffer is connected to a device voltage end of the reference voltage source integrated device, and a control end of the second buffer is connected to a control end of the first buffer.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the base current compensation module further includes a third current mirror module, which mirrors the bias current of the reference voltage generation module to input the bias current to the first current mirror module, so that the first current mirror module mirrors the bias current of the reference voltage integrated device to twice.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the reference voltage generating module includes a first P-type field effect transistor, a second P-type field effect transistor, a fourth P-type field effect transistor, a fifth P-type field effect transistor, a bias resistor, a first N-type field effect transistor, a second N-type field effect transistor, a first triode, a second triode, a first resistor, and a second resistor;

the second end of the fourth P-type field effect transistor is connected with the device voltage end of the reference voltage source integrated device, the first end of the fourth P-type field effect transistor is connected with the second end of the first P-type field effect transistor, the first end of the first P-type field effect transistor is connected with the second end of the bias resistor, the first end of the bias resistor is connected with the second end of the first N-type field effect transistor, the first end of the first N-type field effect transistor is connected with the collector of the first triode, the emitter of the first triode is connected with the second end of the first resistor, the first end of the first resistor is connected with the second end of the second resistor, and the first end of the second resistor is grounded;

the second end of the fifth P-type field effect transistor is connected with the device voltage end of the reference voltage source integrated device, the first end of the fifth P-type field effect transistor is connected with the second end of the second P-type field effect transistor, the first end of the second P-type field effect transistor is connected with the second end of the second N-type field effect transistor, the first end of the second N-type field effect transistor is connected with the collector electrode of the second triode, and the emitter electrode of the second triode is connected with the second end of the second resistor;

the control end of the fourth P-type field effect transistor is connected with the control end of the fifth P-type field effect transistor;

the control end of the fourth P-type field effect transistor is connected with the first end of the first P-type field effect transistor;

the control end of the first P-type field effect transistor is connected with the control end of the second P-type field effect transistor;

the control end of the first P-type field effect transistor is connected with the second end of the first N-type field effect transistor;

the second end of the second N-type field effect transistor is connected with the control end of the second N-type field effect transistor;

and the base electrode of the first triode is connected with the base electrode of the second triode.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the third current mirror module includes a third P-type field effect transistor and a sixth P-type field effect transistor, a second end of the sixth P-type field effect transistor is connected to a device voltage end of the reference voltage source integrated device, a first end of the sixth P-type field effect transistor is connected to a second end of the third P-type field effect transistor, and a first end of the third P-type field effect transistor is connected to a second end of a third N-type field effect transistor of the first current mirror module.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the channel width-to-length ratios of the fourth P-type field effect transistor, the fifth P-type field effect transistor and the sixth P-type field effect transistor are the same.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the channel width-to-length ratios of the first P-type field effect transistor, the second P-type field effect transistor and the third P-type field effect transistor are the same.

According to the reference voltage source integrated device with the base current compensation, the channel width-length ratio of the first N-type field effect transistor is the same as that of the second N-type field effect transistor.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the emitter area ratio of the first triode to the second triode is N: 1 and N is a natural number.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the first current mirror module includes a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor, and a fifth resistor;

the first end of the third N-type field effect transistor is grounded, the first end of the fourth N-type field effect transistor is grounded, and the control end of the third N-type field effect transistor is connected with the control end of the fourth N-type field effect transistor;

the second end of the third N-type field effect transistor is connected with the first end of the fifth N-type field effect transistor, and the second end of the fourth N-type field effect transistor is connected with the first end of the sixth N-type field effect transistor; the control end of the fifth N-type field effect transistor is connected with the control end of the sixth N-type field effect transistor;

the control end of the third N-type field effect transistor is connected with the second end of the fifth N-type field effect transistor;

the first end of the fifth resistor is connected with the second end of the fifth N-type field effect transistor;

the second end of the fifth resistor is connected with the control end of the fifth N-type field effect transistor;

and a second end of the fifth resistor is used for inputting a bias current, and a second end of the sixth N-type field effect transistor is connected with an emitting electrode of the first compensation triode.

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the second current mirror module includes a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor, and a tenth P-type field effect transistor;

the second current mirror module further comprises a third buffer and an operational amplifier, a second end of the third buffer is connected with a first end of the eighth P-type field effect transistor, a first end of the third buffer is connected with a base electrode of the first compensation triode, an output end of the operational amplifier OP is connected with a control end of the third buffer, a positive phase input end of the operational amplifier OP is connected with a first end of the seventh P-type field effect transistor, and a reverse input end of the operational amplifier OP is connected with a first end of the third buffer;

a first end of the eighth P-type field effect transistor is connected with a second end of the third buffer, a second end of the eighth P-type field effect transistor is connected with a first end of the tenth P-type field effect transistor, a second end of the tenth P-type field effect transistor is connected with a device voltage end of the reference voltage source integrated device, a second end of the ninth P-type field effect transistor is connected with a device voltage end of the reference voltage source integrated device, a first end of the ninth P-type field effect transistor is connected with a second end of the seventh P-type field effect transistor, and a first end of the seventh P-type field effect transistor is connected with a base of the reference voltage generation module;

According to the reference voltage source integrated device with base current compensation of at least one embodiment of the present disclosure, the third current mirror module includes a third P-type field effect transistor and a sixth P-type field effect transistor, a second end of the sixth P-type field effect transistor is connected to a device voltage end of the reference voltage source integrated device, a first end of the sixth P-type field effect transistor is connected to a second end of the third P-type field effect transistor, and a first end of the third P-type field effect transistor is connected to a second end of a fifth resistor of the first current mirror module.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic circuit diagram of a reference voltage source integrated device with base current compensation according to an embodiment of the present disclosure.

Fig. 2 is a schematic circuit diagram of a reference voltage source integrated device with base current compensation according to yet another embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

The integrated device 10 of reference voltage source with base current compensation according to an embodiment of the present disclosure includes: a reference voltage generating module 100, wherein a base B of the reference voltage generating module 100 is used for outputting a reference voltage; a base current compensation module 200, wherein the base current compensation module 200 generates a base compensation current and outputs the base compensation current to the base B of the reference voltage generation module 100 to offset the base current of the base B of the reference voltage source generation module 100, so that the reference voltage generation module 100 outputs a compensated reference voltage VREF1 (for example, 1.24V); and a reference voltage output module 300, the reference voltage output module 300 including a voltage adjustment sub-module (including MNbuf1, R3, R4) capable of raising the compensated reference voltage to a predetermined voltage VREF.

The reference voltage generating module 100 may adopt a reference source core module in the prior art.

It will be understood by those skilled in the art that the integrated device 10 with base current compensation can be a stand-alone integrated device (e.g., an integrated circuit chip) or can be part of another integrated device (e.g., an integrated circuit chip).

The integrated device 10 of the reference voltage source according to the above embodiment generates the base compensation current through the base current compensation module 200 to cancel the base current of the base B of the reference voltage source generation module 100, so that the error caused by the base current is eliminated.

The integrated device 10 of the reference voltage source of the above embodiment realizes the output of an arbitrary voltage by the reference voltage output module 300 including the voltage adjustment submodule (including MNbuf1, R3, R4).

Fig. 1 is a schematic circuit diagram of a reference voltage source integrated device 10 with base current compensation according to a preferred embodiment of the present disclosure.

As shown in fig. 1, preferably, the reference voltage output module 300 includes a third resistor R3, a fourth resistor R4, and a first buffer MNbuf1, a first end of the third resistor R3 is connected to the ground Vss, a second end of the third resistor R3 is connected to a first end of the fourth resistor R4, a second end of the fourth resistor R4 is connected to a first end of the first buffer MNbuf1, a second end of the first buffer is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, a second end of the third resistor R3 is connected to the base B of the reference voltage generation module 100, and a second end of the fourth resistor R4 outputs a predetermined voltage.

The first buffer MNbuf1 is an N-type field effect transistor.

With the reference voltage source integrated device 10 of the above embodiment, the predetermined voltage can be adjusted by the ratio of the third resistor R3 to the fourth resistor R4.

The third resistor and the fourth resistor may be both resistance value adjustable resistors.

In the above embodiment, preferably, the base current compensation module 200 of the reference voltage source integrated device 10 includes a first current mirror module, a second current mirror module, and a first compensation transistor Qcomp, the first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device 10 to M times, that is, M × IPTAT, M is a natural number greater than or equal to 1, so that the emitter current of the first compensation transistor Qcomp is M times the bias current and the base current of the first compensation transistor Qcomp is M × IPTAT/Beta, where Beta is a current amplification factor of the first compensation transistor Qcomp, and the second current mirror module mirrors the base current of the first compensation transistor Qcomp, mirrored to M × at/Beta, and outputs the mirrored base current to the base B of the reference voltage generation module 100 as the base compensation current.

In the above embodiment, it is more preferable that the base current compensation module 200 includes a first current mirror module, a second current mirror module, and a first compensation transistor Qcomp, the first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device to two times, i.e., 2 IPTAT, so that the emitter current of the first compensation transistor Qcomp is two times the bias current and the base current of the first compensation transistor Qcomp is 2 IPTAT/Beta, where Beta is a current amplification factor of the first compensation transistor Qcomp, and the second current mirror module mirrors the base current of the first compensation transistor Qcomp to 2 IPTAT/Beta, and outputs the mirrored base current to the base B of the reference voltage generation module 100 as the base compensation current.

Preferably, the first current mirror module of the reference voltage source integrated device 10 includes a third N-type fet MN3 and a fourth N-type fet MN4, a first end of the third N-type fet MN3 is grounded, a first end of the fourth N-type fet MN4 is grounded, a control end of the third N-type fet MN3 is connected to a control end of the fourth N-type fet MN4, a second end of the third N-type fet MN3 is connected to a control end of the third N-type fet MN3, a second end of the third N-type fet MN3 inputs the bias current IPTAT, and a second end of the fourth N-type fet MN4 is connected to an emitter of the first compensation transistor Qcomp.

Preferably, the second current mirror module of the reference voltage source integrated device 10 includes a seventh P-type fet MP7, an eighth P-type fet MP8, a ninth P-type fet MP9 and a tenth P-type fet MP10, a first end of the eighth P-type fet MP8 is connected to the base of the first compensation transistor Qcomp, a second end of the eighth P-type fet MP8 is connected to a first end of the tenth P-type fet MP10, a second end of the tenth P-type fet MP10 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, a second end of the ninth P-type fet MP9 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, a first end of the ninth P-type fet MP9 is connected to a second end of the seventh P-type fet MP7, and a first end of the seventh P-type fet MP7 is connected to the base B of the reference voltage generating module 100;

the control end of the seventh P-type field effect transistor MP7 is connected with the control end of the eighth P-type field effect transistor MP8, and the control end of the ninth P-type field effect transistor MP9 is connected with the control end of the tenth P-type field effect transistor MP 10;

the first end of the eighth P-type fet MP8 is connected to the control end of the tenth P-type fet MP 10.

According to the preferred embodiment of the present disclosure, the ratio of the channel width-to-length ratio of the third N-type field effect transistor MN3 to the channel width-to-length ratio of the fourth N-type field effect transistor MN4 of the reference voltage source integrated device with base current compensation 10 is 1: 2.

Preferably, the channel area length ratio of the seventh P-type fet MP7 is the same as the channel area length ratio of the eighth P-type fet MP8, and the channel area length ratio of the ninth P-type fet MP9 is the same as the channel area length ratio of the tenth P-type fet MP 10.

In the above embodiment, preferably, the base current compensation module 200 of the reference voltage source integrated device 10 further includes a second buffer MNbuf2, a first terminal of the second buffer MNbuf2 is connected to the collector of the first compensation transistor Qcomp, a second terminal of the second buffer MNbuf2 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, and a control terminal of the second buffer MNbuf2 is connected to the control terminal of the first buffer MNbuf 1.

Wherein the second buffer is an N-type field effect transistor.

For the reference voltage source integrated device 10 with base current compensation of the above embodiment, the base current compensation module 200 further includes a third current mirror module, which mirrors the bias current IPTAT of the reference voltage generation module 100 to input the bias current IPTAT to the first current mirror module, so that the first current mirror module mirrors the bias current IPTAT of the reference voltage integrated device to twice.

For the integrated device 10 with base current compensation of the reference voltage source of the above embodiment, the reference voltage generating module 100 includes a first P-type fet MP1, a second P-type fet MP2, a fourth P-type fet MP4, a fifth P-type fet MP5, a bias resistor Rb, a first N-type fet MN1, a second N-type fet MN2, a first triode Q1, a second triode Q2, a first resistor R1, and a second resistor R2;

a second end of the fourth P-type field effect transistor MP4 is connected to the device voltage end VDD of the reference voltage source integrated device 10, a first end of the fourth P-type field effect transistor MP4 is connected to a second end of the first P-type field effect transistor MP1, a first end of the first P-type field effect transistor MP1 is connected to a second end of the bias resistor Rb, a first end of the bias resistor Rb is connected to a second end of the first N-type field effect transistor MN1, a first end of the first N-type field effect transistor MN1 is connected to the collector C of the first triode Q1, an emitter of the first triode Q1 is connected to a second end of the first resistor R1, a first end of the first resistor R1 is connected to a second end of the second resistor R2, and a first end of the second resistor R2 is grounded;

a second end of the fifth P-type field effect transistor MP5 is connected to the device voltage end VDD of the reference voltage source integrated device 10, a first end of the fifth P-type field effect transistor MP5 is connected to a second end of the second P-type field effect transistor MP2, a first end of the second P-type field effect transistor MP2 is connected to a second end of the second N-type field effect transistor MN2, a first end of the second N-type field effect transistor MN2 is connected to the collector C of the second triode Q2, and the emitter E of the second triode Q2 is connected to the second end of the second resistor R2;

the control end of the fourth P-type field effect transistor MP4 is connected with the control end of the fifth P-type field effect transistor MP 5;

the control end of the fourth P-type field effect transistor MP4 is connected with the first end of the first P-type field effect transistor MP 1;

the control end of the first P-type field effect transistor MP1 is connected with the control end of the second P-type field effect transistor MP 2;

the control end of the first P-type field effect transistor MP1 is connected with the second end of the first N-type field effect transistor MN 1;

the second end of the second N-type field effect transistor MN2 is connected with the control end of the second N-type field effect transistor MN 2;

the base of the first transistor Q1 is connected to the base of the second transistor Q2.

Preferably, the third current mirror module includes a third P-type fet MP3 and a sixth P-type fet MP6, a second terminal of the sixth P-type fet MP6 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, a first terminal of the sixth P-type fet MP6 is connected to a second terminal of the third P-type fet MP3, and a first terminal of the third P-type fet MP3 is connected to a second terminal of the third N-type fet MN3 of the first current mirror module.

In the integrated reference-voltage source device 10 with base current compensation according to the above embodiment, the channel width-to-length ratios of the fourth P-type fet MP4, the fifth P-type fet MP5, and the sixth P-type fet MP6 are the same.

Preferably, the channel width-to-length ratios of the first P-type fet MP1, the second P-type fet MP2, and the third P-type fet MP3 are the same.

Preferably, the channel width-to-length ratio of the first N-type fet MN1 is the same as the channel width-to-length ratio of the second N-type fet MN 2.

Preferably, the emitter area ratio of the first transistor Q1 to the second transistor Q2 is N: 1 and N is a natural number.

Fig. 2 is a schematic circuit diagram of a reference voltage source integrated device 10 with base current compensation according to still another preferred embodiment of the present disclosure.

The following description focuses on differences between the circuit configuration of fig. 2 and the circuit configuration shown in fig. 1.

As shown in fig. 2, the first current mirror module of the integrated device 10 with base current compensation includes a third N-type fet MN3, a fourth N-type fet MN4, a fifth N-type fet MN5, a sixth N-type fet MN4, and a fifth resistor R5;

the first end of the third N-type field effect transistor MN3 is grounded, the first end of the fourth N-type field effect transistor MN4 is grounded, and the control end of the third N-type field effect transistor MN3 is connected with the control end of the fourth N-type field effect transistor MN 4;

a second end of the third N-type field effect transistor MN3 is connected with a first end of the fifth N-type field effect transistor MN5, and a second end of the fourth N-type field effect transistor MN4 is connected with a first end of the sixth N-type field effect transistor MN 6; the control end of the fifth N-type field effect transistor MN3 is connected with the control end of the sixth N-type field effect transistor MN 6;

the control end of the third N-type field effect transistor MN3 is connected with the second end of the fifth N-type field effect transistor MN 5;

a first end of the fifth resistor R5 is connected with a second end of the fifth N-type field effect transistor MN 5;

a second end of the fifth resistor R5 is connected with a control end of a fifth N-type field effect transistor MN 5;

a second end of the fifth resistor R5 is inputted with a bias current IPTAT, and a second end of the sixth N-type fet MN6 is connected to an emitter of the first compensation transistor Qcomp.

The first current mirror module in fig. 2 has a higher current replication accuracy with respect to the first current mirror module in fig. 1.

As shown in fig. 2, preferably, the second current mirror module of the reference voltage source integrated device 10 includes a seventh P-type fet MP7, an eighth P-type fet MP8, a ninth P-type fet MP9 and a tenth P-type fet MP 10;

the second current mirror module further comprises a third buffer MNbuf3 and an operational amplifier OP, wherein a second end of the third buffer MNbuf3 is connected with a first end of an eighth P-type field effect transistor MP8, a first end of the third buffer MNbuf3 is connected with a base of a first compensation triode Qcomp, an output end of the operational amplifier OP is connected with a control end of the third buffer MNbuf3, a non-inverting input end of the operational amplifier OP is connected with a first end of a seventh P-type field effect transistor MP7, and an inverting input end of the operational amplifier OP is connected with a first end of a third buffer MNbuf 3;

a first end of the eighth P-type fet MP8 is connected to the second end of the third buffer MNbuf3, a second end of the eighth P-type fet MP8 is connected to the first end of the tenth P-type fet MP10, a second end of the tenth P-type fet MP10 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, a second end of the ninth P-type fet MP9 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, a first end of the ninth P-type fet MP9 is connected to the second end of the seventh P-type fet MP7, and a first end of the seventh P-type fet MP7 is connected to the base B of the reference voltage generating module 100;

In the above embodiment, the ratio of the channel width-to-length ratio of the third N-type field effect transistor MN3 to the channel width-to-length ratio of the fourth N-type field effect transistor MN4 is preferably 1: 2.

In the above embodiment, it is preferable that the channel area width/length ratio of the seventh P-type fet MP7 is the same as the channel width/length ratio of the eighth P-type fet MP8, and the channel width/length ratio of the ninth P-type fet MP9 is the same as the channel width/length ratio of the tenth P-type fet MP 10.

In the above embodiment, preferably, the third current mirror module includes a third P-type fet MP3 and a sixth P-type fet MP6, a second terminal of the sixth P-type fet MP6 is connected to the device voltage terminal VDD of the reference voltage source integrated device 10, a first terminal of the sixth P-type fet MP6 is connected to a second terminal of the third P-type fet MP3, and a first terminal of the third P-type fet MP3 is connected to a second terminal of the fifth resistor R5 of the first current mirror module.

In the above embodiment, the channel width-to-length ratio of the second buffer MNbuf2 to the channel width-to-length ratio of the second N-type fet MN2 is preferably 2: 1.

In the above embodiment, it is preferable that the ratio of the fourth resistor R4 to the fifth resistor R5 is 2: 1.

In the commercial embodiment, the emitter area of the second transistor Q2 is the same as that of the first compensation transistor Qcomp.

The reference voltage source integrated device 10 of the present disclosure can realize arbitrary voltage output without an operational amplifier, has a low offset performance, has a low temperature coefficient (no additional temperature coefficient caused by offset voltage of an operational amplifier), can output high-precision voltage (error caused by base current is compensated), and does not need a high Beta process, and therefore, there is no additional high-order temperature coefficient introduced by high Beta.

In the description herein, reference to the description of the terms "one embodiment/mode," "some embodiments/modes," "example," "specific example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/mode or example is included in at least one embodiment/mode or example of the application. In this specification, the schematic representations of the terms used above are not necessarily intended to be the same embodiment/mode or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/aspects or examples and features of the various embodiments/aspects or examples described in this specification can be combined and combined by one skilled in the art without conflicting therewith.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. A reference voltage source integrated device with base current compensation, comprising:

a reference voltage generating module, a base of which is used for outputting a reference voltage;

a base current compensation module, configured to generate a base compensation current and output the base compensation current to the base of the reference voltage generation module to offset a base current of the base of the reference voltage generation module, so that the reference voltage generation module outputs a compensated reference voltage; and

a reference voltage output module including a voltage adjustment submodule capable of boosting the compensated reference voltage to a predetermined voltage.

2. The integrated device according to claim 1, wherein the reference voltage output module comprises a third resistor, a fourth resistor, and a first buffer, a first end of the third resistor is connected to ground, a second end of the third resistor is connected to a first end of the fourth resistor, a second end of the fourth resistor is connected to a first end of the first buffer, a second end of the first buffer is connected to a device voltage end of the integrated device, a second end of the third resistor is connected to the base of the reference voltage generation module, and a second end of the fourth resistor outputs the predetermined voltage.

3. The integrated device according to claim 2, wherein the predetermined voltage is adjustable by a ratio of the third resistor to the fourth resistor.

4. The integrated device of reference voltage source with base current compensation according to claim 1 or 2, characterized in that the base current compensation module comprises a first current mirror module, a second current mirror module and a first compensation triode, the first current mirror module mirrors a bias current of the reference voltage integrated device to M times, m is a natural number which is more than or equal to 1, so that the emitter current of the first compensation triode is M times of the bias current and the base current of the first compensation triode is M IPTAT/Beta, the Beta is a current amplification coefficient of the first compensation triode, the second current mirror module mirrors the base current of the first compensation triode, the mirror image is M IPTAT/Beta, and the base current is output to the base of the reference voltage generation module as the base compensation current.

5. The reference voltage source integrated device with base current compensation according to claim 2, wherein the base current compensation module comprises a first current mirror module, a second current mirror module and a first compensation triode, the first current mirror module mirrors a bias current IPTAT of the reference voltage integrated device to two times, i.e. 2 IPTAT, so that an emitter current of the first compensation triode is two times the bias current and a base current of the first compensation triode is 2 IPTAT/Beta, wherein Beta is a current amplification coefficient of the first compensation triode, and the second current mirror module mirrors a base current of the first compensation triode to be 2 IPTAT/Beta, and outputs the base compensation current to the base of the reference voltage generation module.

6. The reference voltage source integrated device with base current compensation according to claim 5, wherein the first current mirror module includes a third N-type field effect transistor and a fourth N-type field effect transistor, a first end of the third N-type field effect transistor is grounded, a first end of the fourth N-type field effect transistor is grounded, a control end of the third N-type field effect transistor is connected to a control end of the fourth N-type field effect transistor, a second end of the third N-type field effect transistor is connected to a control end of the third N-type field effect transistor, a second end of the third N-type field effect transistor inputs a bias current, and a second end of the fourth N-type field effect transistor is connected to an emitter of the first compensation triode.

7. Integrated reference-voltage source device with base-current compensation according to claim 5, the second current mirror module comprises a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor, the first end of the eighth P-type field effect transistor is connected with the base electrode of the first compensation triode, the second end of the eighth P-type field effect transistor is connected with the first end of the tenth P-type field effect transistor, the second end of the tenth P-type field effect transistor is connected with the device voltage end of the reference voltage source integrated device, the second end of the ninth P-type field effect transistor is connected with the device voltage end of the reference voltage source integrated device, a first end of the ninth P-type field effect transistor is connected with a second end of a seventh P-type field effect transistor, and a first end of the seventh P-type field effect transistor is connected with a base electrode of the reference voltage generation module;

8. The integrated device of reference voltage source with base current compensation according to claim 6, wherein the ratio of the channel width-to-length ratio of the third N-type field effect transistor to the channel width-to-length ratio of the fourth N-type field effect transistor is 1: 2.

9. The integrated device of reference voltage source with base current compensation according to claim 7, wherein the channel area length/width ratio of the seventh P-type fet is the same as the channel width/length ratio of the eighth P-type fet, and the channel width/length ratio of the ninth P-type fet is the same as the channel width/length ratio of the tenth P-type fet.

10. The integrated device of reference voltage source with base current compensation of claim 5, wherein the base current compensation module further comprises a second buffer, a first end of the second buffer is connected to the collector of the first compensation transistor, a second end of the second buffer is connected to the device voltage end of the integrated device of reference voltage source, and a control end of the second buffer is connected to the control end of the first buffer.

11. The integrated device of reference voltage source with base current compensation according to claim 5, wherein the base current compensation module further comprises a third current mirror module, which mirrors the bias current of the reference voltage generation module to input the bias current to the first current mirror module, so that the first current mirror module mirrors the bias current of the integrated device of reference voltage to twice.

12. The integrated device of reference voltage source with base current compensation according to claim 11, wherein the reference voltage generating module comprises a first P-type field effect transistor, a second P-type field effect transistor, a fourth P-type field effect transistor, a fifth P-type field effect transistor, a bias resistor, a first N-type field effect transistor, a second N-type field effect transistor, a first triode, a second triode, a first resistor and a second resistor;

13. The integrated device according to claim 12, wherein the third current mirror module comprises a third pfet and a sixth pfet, a second end of the sixth pfet is connected to the device voltage end of the integrated device, a first end of the sixth pfet is connected to a second end of the third pfet, and a first end of the third pfet is connected to a second end of the third nfet of the first current mirror module.

14. The integrated device according to claim 13, wherein the channel width-to-length ratios of the fourth P-type fet, the fifth P-type fet, and the sixth P-type fet are the same.

15. The integrated device according to claim 13, wherein the first P-type fet, the second P-type fet, and the third P-type fet have the same channel width-to-length ratio.

16. The integrated device according to claim 13, wherein the first N-type fet has the same channel width to length ratio as the second N-type fet.

17. The integrated device according to claim 13, wherein an emitter area ratio of the first transistor to the second transistor is N: 1 and N is a natural number.

18. The integrated device of reference voltage source with base current compensation according to claim 11, wherein the first current mirror module comprises a third N-type field effect transistor, a fourth N-type field effect transistor, a fifth N-type field effect transistor, a sixth N-type field effect transistor and a fifth resistor;

19. The integrated device of reference voltage source with base current compensation according to claim 5, wherein the second current mirror module comprises a seventh P-type field effect transistor, an eighth P-type field effect transistor, a ninth P-type field effect transistor and a tenth P-type field effect transistor;

the second current mirror module further comprises a third buffer and an operational amplifier, a second end of the third buffer is connected with a first end of the eighth P-type field effect transistor, a first end of the third buffer is connected with a base electrode of the first compensation triode, an output end of the operational amplifier is connected with a control end of the third buffer, a normal phase input end of the operational amplifier is connected with a first end of the seventh P-type field effect transistor, and a reverse phase input end of the operational amplifier is connected with a first end of the third buffer;

20. The integrated device of reference voltage source with base current compensation according to claim 18, wherein the ratio of the channel width-to-length ratio of the third N-type fet to the channel width-to-length ratio of the fourth N-type fet is 1: 2.

21. The integrated device of reference voltage source with base current compensation according to claim 19, wherein the channel area length/width ratio of the seventh P-type fet is the same as the channel width/length ratio of the eighth P-type fet, and the channel width/length ratio of the ninth P-type fet is the same as the channel width/length ratio of the tenth P-type fet.

22. The integrated device according to claim 18, wherein the third current mirror module comprises a third pfet and a sixth pfet, a second end of the sixth pfet is connected to the device voltage end of the integrated device, a first end of the sixth pfet is connected to a second end of the third pfet, and a first end of the third pfet is connected to a second end of the fifth resistor of the first current mirror module.