CN217606302U - Voltage bias circuit - Google Patents
Voltage bias circuit Download PDFInfo
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- CN217606302U CN217606302U CN202221779155.6U CN202221779155U CN217606302U CN 217606302 U CN217606302 U CN 217606302U CN 202221779155 U CN202221779155 U CN 202221779155U CN 217606302 U CN217606302 U CN 217606302U
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Abstract
The utility model relates to the technical field of radio frequency front end chips, and discloses a voltage bias circuit, which comprises a band gap reference circuit for providing reference voltage; the MOS tube P3 and the band-gap reference circuit form a current mirror circuit; the linear voltage stabilizing circuit comprises an operational amplifier OPA2, an MOS tube P4, a resistor R3, a resistor R4 and a resistor R5, wherein the output end of the operational amplifier OPA2 is electrically connected with the grid electrode of the MOS tube P4, the drain electrode of the MOS tube P4 is electrically connected with one end of the resistor R3, the other end of the resistor R3 is electrically connected with the second input end of the operational amplifier OPA2 and one end of the resistor R4 respectively, the other end of the resistor R4 is electrically connected with the drain electrode of the MOS tube P3 and one end of the resistor R5 respectively, and the other end of the resistor R5 is grounded; when in actual use, through using the utility model discloses, on the basis that the output voltage stepping value that realizes voltage bias circuit and stepping temperature coefficient adjusted, reduced voltage bias circuit's complexity and reduced the circuit area.
Description
Technical Field
The utility model relates to a radio frequency front end chip technical field, concretely relates to voltage bias circuit of positive and negative temperature coefficient and voltage gear independent regulation.
Background
In the design of an integrated circuit, a voltage bias circuit is needed by a plurality of circuits to provide a reference voltage, and the performance of the voltage bias circuit directly influences the performance of the integrated circuit. The conventional voltage bias circuit comprises a band gap reference circuit and a low dropout voltage regulator circuit, wherein the band gap reference circuit is used for providing reference voltage for determining a voltage temperature coefficient, and the low dropout voltage regulator circuit outputs stable output voltage based on the reference voltage. However, since the magnitude of the reference voltage provided by the bandgap reference circuit is related to the voltage temperature coefficient, that is, the reference voltage varies with the variation of the voltage temperature coefficient, the output voltage of the low dropout voltage regulator circuit varies with the variation of the voltage temperature coefficient, so that the voltage value and the voltage temperature coefficient of the voltage bias circuit cannot be adjusted independently.
In order to solve the defects of the existing voltage bias circuit, as shown in fig. 1, the existing voltage bias circuit comprises a band gap reference circuit, a reference current adjusting module 1 and a current converting module 2, wherein the reference current converting module converts a reference voltage with a voltage temperature coefficient of 0 output by the band gap reference circuit into a reference current, the current adjusting module outputs a current with a voltage temperature coefficient of 0 and/or adjustable direction based on the reference current, the non-inverting input end of a low-dropout voltage stabilizing circuit is connected with the output end of the current adjusting module to achieve the purpose of independently adjusting the voltage value, the inverting input end of the low-dropout voltage stabilizing circuit is connected with the voltage output end with the voltage temperature coefficient of the band gap reference circuit not being 0 to achieve the purpose of independently adjusting the voltage temperature coefficient, and finally the voltage bias circuit can independently adjust the voltage value and the voltage temperature coefficient.
However, the voltage bias circuit has the following disadvantages in practical use: due to the additional introduction of the current conversion circuit and the current regulation module, the complexity of the whole circuit is increased, the area of a chip is wasted, and the practical application of engineering is not facilitated; the newly added modules inevitably bring random errors introduced by each module, and influence the precision requirement of the final output voltage value; in addition, since the voltage bias circuit needs to output different step voltages, i.e., VREF1 and VREF2, it is necessary to consider the input common mode voltage level rejection ratio of the operational amplifier OPA1 and the operational amplifier OPA2, which has an influence on the accuracy requirement of the final output voltage value.
SUMMERY OF THE UTILITY MODEL
In view of the deficiencies of the background art, the present invention provides a voltage bias circuit to solve the deficiencies of the prior voltage bias circuit in the background art.
For solving the technical problem, the utility model provides a following technical scheme: a voltage bias circuit comprises
A bandgap reference circuit for providing a reference voltage;
the MOS tube P3 and the band gap reference circuit form a current mirror circuit, and the drain electrode of the MOS tube P3 outputs current I1;
the current mirror array comprises an input end and an output end, the input end is electrically connected with the drain electrode of the MOS transistor P3, and the current I1 is input into the current mirror array;
the linear voltage stabilizing circuit comprises an operational amplifier OPA2, an MOS tube P4, a resistor R3, a resistor R4 and a resistor R5, wherein reference voltage is input to a first input end of the operational amplifier OPA2, an output end of the operational amplifier OPA2 is electrically connected with a grid electrode of the MOS tube P4, a drain electrode of the MOS tube P4 is electrically connected with one end of the resistor R3, the other end of the resistor R3 is electrically connected with a second input end of the operational amplifier OPA2 and one end of the resistor R4 respectively, the other end of the resistor R4 is electrically connected with an output end of a current mirror array and one end of the resistor R5, and the other end of the resistor R5 is grounded.
In one embodiment, the MOS transistors P3 and P4 are both PMOS transistors.
In one embodiment, the first input terminal of the operational amplifier OPA2 is a negative input terminal of the operational amplifier OPA 2; the second input end of the operational amplifier OPA2 is the positive input end of the operational amplifier OPA 2.
In one embodiment, the bandgap reference circuit includes a MOS transistor P1, a diode D1, a MOS transistor P2, a resistor R1, a resistor R2, a diode D2, and an operational amplifier OPA1;
the source electrode of the MOS tube P1 is electrically connected with the source electrode of the MOS tube P2, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 respectively; the drain electrode of the MOS tube P1 is respectively and electrically connected with the anode of the diode D1 and the first input end of the operational amplifier OPA1; the cathode of the diode D1 is grounded;
the drain electrode of the MOS tube P2 is electrically connected with one end of the resistor R1 and the first input end of the operational amplifier OPA2 respectively; the other end of the resistor R1 is electrically connected with one end of the resistor R2 and a second input end of the operational amplifier OPA1 respectively; the other end of the resistor R2 is grounded through a diode D2;
the output end of the operational amplifier OPA1 is electrically connected to the gate of the MOS transistor P1, the gate of the MOS transistor P2, and the gate of the MOS transistor P3, respectively.
In one embodiment, the MOS transistors P1 and P2 are both PMOS transistors.
In one embodiment, the first input terminal of the operational amplifier OPA1 is a negative input terminal of the operational amplifier OPA1; the second input end of the operational amplifier OPA1 is a positive input end of the operational amplifier OPA 1.
The utility model discloses adjust the principle of final output voltage Vout as follows:
the end of the resistor R3 electrically connected with the resistor R4 is taken as a node X, the end of the resistor R4 electrically connected with the resistor R5 is taken as a node Y, the voltage input to the linear voltage stabilizing circuit by the bandgap reference circuit is VREF, the current input to the node Y by the current mirror array is Iptat, and the voltage of the node X is equal to VREF due to the voltage clamping action of the operational amplifier OPA2, wherein the voltage VY of the node Y is = (VX/R3 + Iptat) = Rc = (VREF/R3 + Iptat) = Rc, wherein Rc = R4// R5;
note that, the end of the resistor R3 electrically connected to the drain of the MOS transistor P4 outputs the voltage Vout, and Vout = VREF + (VX-VY) × (R3/R4). In combination with the formula of the voltage VY, vout = [1+ (1-Rc/R4) × (R3/R4) ] × VREF-Iptat × (Rc/R4), it can be stated that the current Iptat is directional, the sink current input is positive, the source current output is negative, the first term in the formula is the zero temperature coefficient voltage portion, and the second term is the voltage portion of the temperature coefficient information. The voltage with the expected positive and negative temperature coefficient grading can be obtained by adjusting the ratio of R4 to R5. Then, the resistor R1 is adjusted to obtain the voltage of the expected voltage step.
Compared with the prior art, the utility model beneficial effect who has is: through using the utility model discloses, on the basis that the output voltage stepping value that realizes voltage bias circuit and stepping temperature coefficient adjust, reduced voltage bias circuit's complexity and reduced the circuit area.
Drawings
FIG. 1 is a circuit diagram of a conventional voltage bias circuit;
fig. 2 is a circuit diagram of the present invention in an embodiment.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic drawings and illustrate the basic structure of the present invention only in a schematic manner, and thus show only the components related to the present invention.
As shown in FIG. 1, a voltage bias circuit comprises
A band gap reference circuit 1 for providing a reference voltage;
the MOS transistor P3 and the band-gap reference circuit 1 form a current mirror circuit, and the drain electrode of the MOS transistor P3 outputs current I1;
the current mirror array 3 comprises an input end and an output end, the input end is electrically connected with the drain electrode of the MOS transistor P3, and the current I1 is input into the current mirror array 3;
linear voltage stabilizing circuit 2, including operational amplifier OPA2, MOS pipe P4, resistance R3, resistance R4 and resistance R5, reference voltage inputs the first input of operational amplifier OPA2, operational amplifier OPA 2's output is connected with MOS pipe P4's grid electricity, MOS pipe P4's drain electrode is connected with resistance R3 one end electricity, the resistance R3 other end is connected with operational amplifier OPA 2's second input and resistance R4 one end electricity respectively, the resistance R4 other end is connected with current mirror array 3's output and resistance R5 one end electricity respectively, the resistance R5 other end ground connection.
In this embodiment, the MOS transistor P3 and the MOS transistor P4 are both PMOS transistors.
In this embodiment, the first input terminal of the operational amplifier OPA2 is the negative input terminal of the operational amplifier OPA 2; the second input terminal of the operational amplifier OPA2 is the positive input terminal of the operational amplifier OPA 2.
In this embodiment, the bandgap reference circuit 1 includes a MOS transistor P1, a diode D1, a MOS transistor P2, a resistor R1, a resistor R2, a diode D2, and an operational amplifier OPA1;
the source electrode of the MOS tube P1 is respectively and electrically connected with the source electrode of the MOS tube P2, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4; the drain electrode of the MOS tube P1 is respectively and electrically connected with the anode of the diode D1 and the first input end of the operational amplifier OPA1; the cathode of the diode D1 is grounded;
the drain electrode of the MOS tube P2 is respectively and electrically connected with one end of the resistor R1 and the first input end of the operational amplifier OPA 2; the other end of the resistor R1 is electrically connected with one end of the resistor R2 and a second input end of the operational amplifier OPA1 respectively; the other end of the resistor R2 is grounded through a diode D2;
the output end of the operational amplifier OPA1 is electrically connected with the gate of the MOS transistor P1, the gate of the MOS transistor P2, and the gate of the MOS transistor P3, respectively.
The reference voltage VREF = Vbe + (R1/R2) × VT × ln (n) output from the bandgap reference circuit 1 in fig. 1 is about 1.2V. Wherein Vbe is the conduction voltage drop of diode D2; n is the ratio of the number of diode sizes in the bandgap reference circuit 1, and assuming that the ratio of the length to the width of the diode D1 is a and the ratio of the length to the width of the diode D2 is b, n is b/a, preferably n has a value of 8; VT is the voltage equivalent of temperature, proportional to the thermodynamic temperature, expressed as VT = (K × T)/q, T is the thermodynamic temperature in K, q =1.602 × 10-19C is the electrical quantity of electrons, and K is the boltzmann constant.
In this embodiment, the MOS transistors P1 and P2 are both PMOS transistors.
In this embodiment, the first input terminal of the operational amplifier OPA1 is the negative input terminal of the operational amplifier OPA1; the second input terminal of the operational amplifier OPA1 is the positive input terminal of the operational amplifier OPA 1.
The utility model discloses adjust the principle of final output voltage Vout as follows:
the end of the resistor R3 electrically connected with the resistor R4 is taken as a node X, the end of the resistor R4 electrically connected with the resistor R5 is taken as a node Y, the voltage input to the linear voltage stabilizing circuit by the bandgap reference circuit is VREF, the voltage of the node X is equal to VREF due to the voltage clamping action of the operational amplifier OPA2, the current input to the node Y by the current mirror array is Iptat, and the voltage VY = (VX/R3 + Iptat) = (VREF/R3 + Iptat) = (Rc), and Rc = R4// R5 of the node Y; wherein the current mirror array 3 is disposed in the linear mirror image copy current I1, and outputs a current Iptat, the current Iptat is a positive temperature coefficient current, the current Iptat at the point of the node Y can be a sink current or a pull-down current, and the single current mirror array 3 is the prior art, the utility model discloses a change the current direction input to the electrical node Y through the current mirror array 3;
the end of the resistor R3 electrically connected to the drain of the MOS transistor P4 outputs the voltage Vout, and Vout = VREF + (VX-VY) (R3/R4). In combination with the formula of the voltage VY, vout = [1+ (1-Rc/R4) × (R3/R4) ] × VREF-Iptat × (Rc/R4), it should be noted that since the current Iptat is directional, the sink current input is positive and the source current output is negative, the first term in the formula is the zero temperature coefficient voltage portion and the second term is the voltage portion of the temperature coefficient information. The voltage with the expected positive and negative temperature coefficient grading can be obtained by adjusting the ratio of R4 to R5. Then, the resistor R1 is adjusted to obtain the voltage of the expected voltage step.
To sum up, through using the utility model discloses, on the basis that realizes voltage bias circuit's output voltage stepping value and stepping temperature coefficient and adjust, reduced voltage bias circuit's complexity and reduced the circuit area.
In light of the above, the present invention is not limited to the above embodiments, and various changes and modifications can be made by the worker without departing from the scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (6)
1. A voltage bias circuit, comprising
A bandgap reference circuit for providing a reference voltage;
the MOS tube P3 and the band gap reference circuit form a current mirror circuit, and the drain electrode of the MOS tube P3 outputs current I1;
the current mirror array comprises an input end and an output end, the input end is electrically connected with the drain electrode of the MOS transistor P3, and the current I1 is input into the current mirror array;
the linear voltage stabilizing circuit comprises an operational amplifier OPA2, an MOS tube P4, a resistor R3, a resistor R4 and a resistor R5, wherein reference voltage is input to a first input end of the operational amplifier OPA2, an output end of the operational amplifier OPA2 is electrically connected with a grid electrode of the MOS tube P4, a drain electrode of the MOS tube P4 is electrically connected with one end of the resistor R3, the other end of the resistor R3 is electrically connected with a second input end of the operational amplifier OPA2 and one end of the resistor R4 respectively, the other end of the resistor R4 is electrically connected with an output end of a current mirror array and one end of the resistor R5, and the other end of the resistor R5 is grounded.
2. The voltage bias circuit of claim 1, wherein the MOS transistors P3 and P4 are PMOS transistors.
3. A voltage bias circuit according to claim 1, wherein the first input terminal of the operational amplifier OPA2 is the negative input terminal of the operational amplifier OPA 2; the second input terminal of the operational amplifier OPA2 is the positive input terminal of the operational amplifier OPA 2.
4. The voltage bias circuit according to claim 1, wherein the bandgap reference circuit comprises a MOS transistor P1, a diode D1, a MOS transistor P2, a resistor R1, a resistor R2, a diode D2, and an operational amplifier OPA1;
the source electrode of the MOS tube P1 is electrically connected with the source electrode of the MOS tube P2, the source electrode of the MOS tube P3 and the source electrode of the MOS tube P4 respectively; the drain electrode of the MOS tube P1 is respectively and electrically connected with the anode of the diode D1 and the first input end of the operational amplifier OPA1; the cathode of the diode D1 is grounded;
the drain electrode of the MOS tube P2 is electrically connected with one end of the resistor R1 and the first input end of the operational amplifier OPA2 respectively; the other end of the resistor R1 is electrically connected with one end of the resistor R2 and a second input end of the operational amplifier OPA1 respectively; the other end of the resistor R2 is grounded through a diode D2;
the output end of the operational amplifier OPA1 is electrically connected to the gate of the MOS transistor P1, the gate of the MOS transistor P2, and the gate of the MOS transistor P3, respectively.
5. The voltage bias circuit according to claim 4, wherein the MOS transistor P1 and the MOS transistor P2 are both PMOS transistors.
6. The voltage bias circuit according to claim 4, wherein the first input terminal of the operational amplifier OPA1 is a negative input terminal of the operational amplifier OPA1; the second input end of the operational amplifier OPA1 is a positive input end of the operational amplifier OPA 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221779155.6U CN217606302U (en) | 2022-07-11 | 2022-07-11 | Voltage bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202221779155.6U CN217606302U (en) | 2022-07-11 | 2022-07-11 | Voltage bias circuit |
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| Publication Number | Publication Date |
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| CN217606302U true CN217606302U (en) | 2022-10-18 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202221779155.6U Active CN217606302U (en) | 2022-07-11 | 2022-07-11 | Voltage bias circuit |
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| CN (1) | CN217606302U (en) |
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- 2022-07-11 CN CN202221779155.6U patent/CN217606302U/en active Active
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