CN215641494U - High-voltage isolation sampling circuit - Google Patents
High-voltage isolation sampling circuit Download PDFInfo
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- CN215641494U CN215641494U CN202120888059.4U CN202120888059U CN215641494U CN 215641494 U CN215641494 U CN 215641494U CN 202120888059 U CN202120888059 U CN 202120888059U CN 215641494 U CN215641494 U CN 215641494U
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Abstract
The utility model provides a high-voltage isolation sampling circuit, which samples the voltage of a bus to be tested through a voltage division circuit, outputs a triangular wave signal through a triangular wave signal generating circuit, compares the sampling voltage respectively input by a non-inverting input end and an inverting input end with the triangular wave signal through a comparator, outputs a high level when the sampling voltage is higher than the triangular wave value, and outputs a low level when the sampling voltage is lower than the triangular wave value. Therefore, the PWM waveform with the duty ratio in direct proportion to the sampling voltage can be obtained, and the PWM waveform is sent to the MCU processor through the optical coupler, so that the circuit does not need to adopt a lattice force operational amplifier chip of a traditional sampling circuit.
Description
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to a high-voltage isolation sampling circuit.
Background
In the prior art, when sampling direct-current high voltages such as power battery bus voltage, the isolation operational amplifier chip is usually adopted to realize, however, the isolation operational amplifier chip is a vulnerable part which is easy to damage, and if the isolation operational amplifier chip is damaged, the direct-current high voltages such as power battery bus voltage cannot be sampled, so how to realize isolation sampling of the power battery bus voltage on the premise of not using the isolation operational amplifier chip becomes one of the technical problems to be solved urgently by technical personnel in the field.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the present invention provides a high voltage isolation sampling circuit to implement voltage sampling of a high voltage bus.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
a high voltage isolated sampling circuit comprising:
the first end of the voltage division circuit is connected with the tested bus, and the second end of the voltage division circuit is grounded;
a triangular wave generating circuit for generating and outputting a triangular wave signal;
the non-inverting input end of the comparator is connected with the voltage division signal output end of the voltage division circuit, and the inverting input end of the comparator is connected with the output end of the triangular wave generator;
the input end of the optical coupler is connected with the output end of the comparator;
and the input end of the MCU processor is connected with the output end of the optocoupler.
Optionally, in the high-voltage isolation sampling circuit, the method further includes:
the first operational amplifier is arranged between the comparator and the voltage division circuit, the input end of the first operational amplifier is connected with the voltage division signal output end of the voltage division circuit, and the output end of the first operational amplifier is connected with the non-inverting input end of the comparator.
Optionally, in the high-voltage isolation sampling circuit, the triangular wave generating circuit includes:
a second transporting and placing device and a third transporting and placing device,
the non-inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier and the output end of the third operational amplifier;
the inverting input end of the second operational amplifier is connected with the non-inverting input end of the third operational amplifier, and the inverting input end of the second operational amplifier is grounded through a grounding resistor;
the output end of the third operational amplifier is used as the output end of the triangular wave generating circuit;
the inverting input end of the third operational amplifier is connected with the output end of the second operational amplifier, and the inverting input end of the third operational amplifier is connected with the output end of the third operational amplifier through a first capacitor;
and the non-inverting input end of the third operational amplifier is used for acquiring a first voltage, and the first voltage is a working voltage of the first comparator.
Optionally, in the high-voltage isolation sampling circuit, the method further includes:
the first voltage drop resistor is arranged between the non-inverting input end of the second operational amplifier and the output end of the third operational amplifier;
the second voltage drop resistor is arranged between the non-inverting input end of the second operational amplifier and the output end of the second operational amplifier;
and the third voltage drop resistor is arranged between the output end of the second operational amplifier and the inverting input end of the third operational amplifier.
Optionally, in the high-voltage isolation sampling circuit, the voltage dividing circuit includes:
n divider resistors connected in series in sequence, wherein N is a positive integer not less than 2.
Optionally, in the high-voltage isolation sampling circuit, the method further includes:
the Schmitt trigger and the FPGA are arranged between the MCU processor and the optocoupler;
the input end of the Schmitt trigger is connected with the output end of the optical coupler;
the input end of the FPGA is connected with the output end of the Schmitt trigger, and the FPGA is used for filtering and calculating the voltage signal output by the Schmitt trigger and outputting a calculation result;
and the output end of the FPGA is connected with the input end of the MCU processor.
Optionally, in the high-voltage isolation sampling circuit, the method further includes:
an isolation transformer for providing a power VDD and a power VCC which are isolated from each other, wherein, the power VDD is the working voltage of the comparator, and the power VCC is the working voltage of the Schmitt trigger.
Based on the above technical solution, in the above technical solution provided in the embodiments of the present invention, the voltage of the bus to be tested is sampled by the voltage divider circuit, the triangular wave signal is output by the triangular wave signal generating circuit, the comparator compares the sampling voltage respectively input by the non-inverting input terminal and the inverting input terminal with the triangular wave signal, when the sampling voltage is higher than the triangular wave value, a high level is output, and when the sampling voltage is lower than the triangular wave value, a low level is output. Therefore, the PWM waveform with the duty ratio in direct proportion to the sampling voltage can be obtained, and the PWM waveform is sent to the MCU processor through the optical coupler, so that the circuit does not need to adopt a lattice force operational amplifier chip of a traditional sampling circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a high-voltage isolation sampling circuit provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a high-voltage isolation sampling circuit according to another embodiment of the present application;
fig. 3 is a schematic diagram of input and output signals of a comparator according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The application provides a high-voltage isolation sampling circuit without using an isolation operational amplifier chip, and referring to fig. 1, the circuit may include:
the circuit comprises a voltage division circuit 100, a triangular wave generation circuit 200, a comparator 300, an optical coupler 400 and an MCU processor;
a first end of the voltage dividing circuit 100 is connected with a tested bus, and a second end of the voltage dividing circuit is grounded; the structure of the voltage divider circuit can be set according to the user's requirements, for example, referring to fig. 2, in the technical solution disclosed in the embodiment of the present application, the voltage dividing circuit comprises N voltage dividing resistors which are sequentially connected in series, wherein N is a positive integer not less than 2, for example, in the scheme, the value of N is 5, namely, the voltage-dividing circuit is composed of a first voltage-dividing resistor R1, a second voltage-dividing resistor R2, a third voltage-dividing resistor R3, a fourth voltage-dividing resistor R4 and a fifth voltage-dividing resistor R5, the first voltage-dividing resistor R1, the second voltage-dividing resistor R2, the third voltage-dividing resistor R3, the fourth voltage-dividing resistor R4 and the fifth voltage-dividing resistor R5 are connected in series in turn, wherein, the end of the first divider resistor R1 not connected with the second divider resistor R2 is used as the input end of the divider circuit and is connected with the tested bus, the common terminal of the fourth voltage-dividing resistor R4 and the fifth voltage-dividing resistor R5 can be used as a voltage-dividing signal output terminal of the voltage-dividing circuit 100.
The apparatus includes a triangular wave generating circuit 200, configured to generate and output a triangular wave signal, and in this scheme, the triangular wave generating circuit is configured to output a periodic triangular wave, and in this scheme, the triangular wave generating circuit 200 is configured by two operational amplifiers and a peripheral circuit, the two operational amplifiers are respectively denoted as a second operational amplifier UIB and a third operational amplifier UIC, specifically, referring to fig. 2, a non-inverting input end of the second operational amplifier UIB is connected to an output end of the second operational amplifier UIB and an output end of the third operational amplifier UIC; a resistor R6 is arranged between the non-inverting input end of the second operational amplifier UIB and the output end of the second operational amplifier UIB, and a resistor R7 is arranged between the non-inverting input end of the second operational amplifier UIB and the output end of the third operational amplifier UIC;
the inverting input terminal of the second op amp UIB is connected to the non-inverting input terminal of the third op amp UIC, and the inverting input terminal of the second op amp UIB is grounded through a grounding resistor R, where the grounding of the inverting input terminal of the second op amp UIB is the same as the grounding of the second terminal of the voltage dividing circuit, and may be commonly connected to the ground line VBAT "of the tested bus;
the output end of the third operational amplifier UIC is used as the output end of the triangular wave generating circuit 200;
the inverting input terminal of the third opamp UIC is connected to the output terminal of the second opamp UIB, and the inverting input terminal of the third opamp UIC is connected to the output terminal of the third opamp UIC through a first capacitor C1;
the non-inverting input terminal of the third operational amplifier UIC is configured to obtain a first voltage VDD, where the first voltage VDD is a working voltage of the first comparator 300, and the non-inverting input terminal of the third operational amplifier UIC specifically obtains the first voltage VDD through the voltage drop resistor.
The non-inverting input end of the comparator 300 is connected to the voltage dividing signal output end of the voltage dividing circuit 100, the inverting input end of the comparator 300 is connected to the output end of the triangular wave generator 200, and the working voltage of the comparator 300 is the first voltage VDD;
in the present embodiment, an RC filter circuit and a first operational amplifier U1D may be further disposed between the comparison circuit 300 and the voltage division signal output terminal of the voltage division circuit 100, wherein the RC filter circuit includes a resistor R9 and a second capacitor C2, a first end of the resistor R9 is connected to a common terminal of the fourth voltage division resistor R4 and the fifth voltage division resistor R5, a second end of the resistor R9 is connected to a first end of the second capacitor C2, and a second end of the second capacitor C2 is grounded. The non-inverting input terminal of the first operational amplifier U1D is connected to the second terminal of the resistor R9, the output terminal of the first operational amplifier U1D is connected to the non-inverting output terminal of the comparator 300, and the inverting input terminal of the first operational amplifier U1D is connected to the output terminal of the first operational amplifier U1D;
in the present scheme, the input end of the optical coupler 400 is connected to the output end of the comparator 100, and in the present scheme, the input end of the optical coupler 400 may be connected to the output end of the comparator 300 through a resistor R10;
the input end of the MCU processor 500 is connected with the output end of the optocoupler;
in the technical solution disclosed in the embodiment of the present application, a schmitt trigger U3 and an FPGAU4 may be disposed between the MCU processor 500 and the output end of the optical coupler 400, and an input end of the schmitt trigger U3 is connected to the output end of the optical coupler 400; the input end of the FPGA U4 is connected with the output end of the Schmitt trigger U3, and the FPGA U4 is used for filtering and voltage calculating the voltage signal output by the Schmitt trigger U3 and outputting a calculation result; the output of the FPGAU4 is connected to the input of the MCU processor 500. In particular, the schmitt trigger U3 is used to implement a hysteresis comparison to prevent the level of the digital signal from slightly jittering to cause frequent unexpected changes in the result. The FPGA is configured to mainly perform digital filtering and voltage calculation during signal processing of the dc high voltage sampling, and transmit a processed result to the MCU processor 500. A filter circuit is further arranged between the input end of the Schmitt trigger U3 and the output end of the optical coupler 400, the filter circuit is composed of a resistor R11 and a third capacitor C3, the resistor R11 is connected with the third capacitor C3 in parallel, a first common end of a resistor R11 and a first common end of a third capacitor C3 are connected with the input end of the Schmitt trigger U3 and the output end of the optical coupler 400, and a second common end of the resistor R11 and a second common end of the third capacitor C3 are grounded.
In the technical solution disclosed in the above embodiment of the present application, the isolation device may further include an isolation transformer U5, the isolation transformer U5 is configured to provide a power supply VDD and a power supply VCC that are isolated from each other, where the power supply VDD is the operating voltage of the comparator, and the power supply VCC is the operating voltage of the schmitt trigger U3.
In summary, the comparator U1A compares the sampling voltage and the triangular wave signal respectively input to the non-inverting input terminal and the inverting input terminal, and outputs a high level when the sampling voltage is higher than the triangular wave value and outputs a low level when the sampling voltage is lower than the triangular wave value. Therefore, a PWM waveform with a duty ratio proportional to the magnitude of the sampling voltage can be obtained, and as shown in fig. 2, the generated PWM waveform coupler 400 is transmitted to the MCU processor 500.
Specifically, the PWM signal generated by the comparator 300 has a frequency equal to that of the triangular wave signal, and the period and the frequency are T ═ (4 × R7 × R8 × C1)/R6, and F ═ R6/(4 × R7 × R8 × C1), respectively.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the utility model. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A high voltage isolation sampling circuit, comprising:
the first end of the voltage division circuit is connected with the tested bus, and the second end of the voltage division circuit is grounded;
a triangular wave generating circuit for generating and outputting a triangular wave signal;
the non-inverting input end of the comparator is connected with the voltage division signal output end of the voltage division circuit, and the inverting input end of the comparator is connected with the output end of the triangular wave generator;
the input end of the optical coupler is connected with the output end of the comparator;
and the input end of the MCU processor is connected with the output end of the optocoupler.
2. The high voltage isolated sampling circuit of claim 1, further comprising:
the first operational amplifier is arranged between the comparator and the voltage division circuit, the input end of the first operational amplifier is connected with the voltage division signal output end of the voltage division circuit, and the output end of the first operational amplifier is connected with the non-inverting input end of the comparator.
3. The high voltage isolated sampling circuit of claim 2, wherein the triangular wave generating circuit comprises:
a second transporting and placing device and a third transporting and placing device,
the non-inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier and the output end of the third operational amplifier;
the inverting input end of the second operational amplifier is connected with the non-inverting input end of the third operational amplifier, and the inverting input end of the second operational amplifier is grounded through a grounding resistor;
the output end of the third operational amplifier is used as the output end of the triangular wave generating circuit;
the inverting input end of the third operational amplifier is connected with the output end of the second operational amplifier, and the inverting input end of the third operational amplifier is connected with the output end of the third operational amplifier through a first capacitor;
and the non-inverting input end of the third operational amplifier is used for acquiring a first voltage, and the first voltage is a working voltage of the first comparator.
4. The high voltage isolated sampling circuit of claim 3, further comprising:
the first voltage drop resistor is arranged between the non-inverting input end of the second operational amplifier and the output end of the third operational amplifier;
the second voltage drop resistor is arranged between the non-inverting input end of the second operational amplifier and the output end of the second operational amplifier;
and the third voltage drop resistor is arranged between the output end of the second operational amplifier and the inverting input end of the third operational amplifier.
5. The high voltage isolated sampling circuit of claim 1, wherein the voltage divider circuit comprises:
n divider resistors connected in series in sequence, wherein N is a positive integer not less than 2.
6. The high voltage isolated sampling circuit of claim 4, further comprising:
the Schmitt trigger and the FPGA are arranged between the MCU processor and the optocoupler;
the input end of the Schmitt trigger is connected with the output end of the optical coupler;
the input end of the FPGA is connected with the output end of the Schmitt trigger, and the FPGA is used for filtering and calculating the voltage signal output by the Schmitt trigger and outputting a calculation result;
and the output end of the FPGA is connected with the input end of the MCU processor.
7. The high voltage isolated sampling circuit of claim 6, further comprising:
an isolation transformer for providing a power VDD and a power VCC which are isolated from each other, wherein, the power VDD is the working voltage of the comparator, and the power VCC is the working voltage of the Schmitt trigger.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120888059.4U CN215641494U (en) | 2021-04-27 | 2021-04-27 | High-voltage isolation sampling circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202120888059.4U CN215641494U (en) | 2021-04-27 | 2021-04-27 | High-voltage isolation sampling circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115541972A (en) * | 2022-11-30 | 2022-12-30 | 深圳市捷益达电子有限公司 | Direct-current voltage isolation sampling method, device and circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115541972A (en) * | 2022-11-30 | 2022-12-30 | 深圳市捷益达电子有限公司 | Direct-current voltage isolation sampling method, device and circuit |
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