CN217332595U - Grid voltage sampling circuit - Google Patents
Grid voltage sampling circuit Download PDFInfo
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- CN217332595U CN217332595U CN202123408809.2U CN202123408809U CN217332595U CN 217332595 U CN217332595 U CN 217332595U CN 202123408809 U CN202123408809 U CN 202123408809U CN 217332595 U CN217332595 U CN 217332595U
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Abstract
The utility model provides a grid voltage sampling circuit, its circuit structure is simple, and the cost is lower. The three-phase power supply at the side of the frequency converter is input, then is respectively converted into a voltage signal after being subjected to resistance voltage division and attenuation, and then can be directly transmitted to a CPU (central processing unit) for A/D (analog/digital) conversion treatment after being subjected to strong and weak electric isolation by a photoelectric coupler, so that all parameters such as phase sequence, phase position, amplitude value and the like can be directly obtained.
Description
Technical Field
The utility model relates to a converter voltage sampling circuit technical field specifically is a grid voltage sampling circuit.
Background
When a four-quadrant frequency converter power grid side AFE (active front end rectifying circuit) works, power grid parameters need to be set: including phase sequence, phase, voltage amplitude, etc. The current commonly used sampling circuit is to perform resistance voltage division on an input side three-phase power supply, reduce a voltage value in proportion, rectify the voltage into direct current voltage and perform operational amplification to obtain a required voltage signal; after optical coupling and strong and weak electric isolation, CUP is input for A/D conversion to obtain the amplitude of the power grid voltage; and finally, acquiring a pulse signal of a voltage zero crossing point by the voltage comparator to judge the phase sequence and phase of the voltage. After the circuit is adopted, the phase sequence, the phase and the amplitude are required to be sampled by the sampling circuit respectively, and then the sampled signals are processed and sent to the CPU, so that the whole circuit structure is complex, the subsequent calculation is complex, and the cost is high.
SUMMERY OF THE UTILITY MODEL
Complicated to current converter sampling circuit structure, the higher problem of cost, the utility model provides a grid voltage sampling circuit, its circuit structure is simple, and the cost is lower.
The technical scheme is as follows: a grid voltage sampling circuit comprising a connector TM3, characterized by: a pin 1 of the connector TM3 is connected with an R-phase power supply of a frequency converter and is sequentially connected with one ends of resistors R1-R6, a lead between the resistor R5 and the resistor R6 is connected with a pin 2 of a photoelectric coupler U2 and one end of a capacitor C15, pins 3 and 4 of the photoelectric coupler U2 are connected with the other end of the capacitor C15 and are grounded, a pin 1 of the photoelectric coupler U2 is connected with a P5V voltage source, a pin 5 of the photoelectric coupler U2 is connected with one end of the capacitor C17 and is grounded, a pin 6 of the photoelectric coupler U2 is connected with the other end of the capacitor C17 and a voltage source Vref +5, a pin 8 of the photoelectric coupler U2 is connected with a voltage source V +5, and a pin 7 of the photoelectric coupler U2 outputs a VRU voltage signal to a CPU; a 2 pin of the connector TM3 is connected with an S-phase power supply of a frequency converter and is sequentially connected with one ends of resistors R7-R12, a lead between the resistor R11 and the resistor R12 is connected with a 2 pin of a photoelectric coupler U3 and one end of a capacitor C22, 3 pins and 4 pins of the photoelectric coupler U3 are connected with the other end of the capacitor C22 and are grounded, a 1 pin of the photoelectric coupler U3 is connected with a P5V voltage source, a 5 pin of the photoelectric coupler U3 is connected with one end of the capacitor C23 and is grounded, a 6 pin of the photoelectric coupler U3 is connected with the other end of the capacitor C23 and a +5 voltage source Vref, an 8 pin of the photoelectric coupler U3 is connected with a +5V voltage source, and a 7 pin of the photoelectric coupler U3 outputs a VSV voltage signal to a CPU; the 3 pins of the connector TM3 are connected with an S-phase power supply of a frequency converter and are sequentially connected with one ends of resistors R16-R21, a lead between the resistor R20 and the resistor R21 is connected with a 2 pin of a photoelectric coupler U4 and one end of a capacitor C27, 3 pins and 4 pins of the photoelectric coupler U4 are connected with the other end of the capacitor C27 and are grounded, a 1 pin of the photoelectric coupler U4 is connected with a P5V voltage source, a 5 pin of the photoelectric coupler U4 is connected with one end of the capacitor C29 and is grounded, a 6 pin of the photoelectric coupler U4 is connected with the other end of the capacitor C29 and a +5 voltage source Vref, an 8 pin of the photoelectric coupler U4 is connected with a +5V voltage source, and a 7 pin of the photoelectric coupler U4 outputs a VTW voltage signal to a CPU.
It is further characterized in that: the photocouplers U2 to U4 adopt QCPL-752H linear photocouplers.
After the structure is adopted, the three-phase power supply at the side of the frequency converter is input, is respectively converted into a voltage signal after being subjected to resistance voltage division and attenuation, and then can be directly transmitted to the CPU for A/D conversion processing after being subjected to strong and weak current isolation by the photoelectric coupler, so that all parameters such as phase sequence, phase, amplitude and the like can be directly obtained, and the circuit is simple in structure and low in cost.
Drawings
Fig. 1 is a circuit diagram of the whole structure of the present invention.
Detailed Description
As shown in fig. 1, a grid voltage sampling circuit includes a connector TM3, where a pin 1 of the connector TM3 is connected to an R-phase power supply of a frequency converter and is sequentially connected to one end of resistors R1 to R6, a lead between the resistor R5 and a resistor R6 is connected to a pin 2 of a photocoupler U2 and one end of a capacitor C15, pins 3 and 4 of the photocoupler U2 are connected to the other end of a capacitor C15 and are grounded, a pin 1 of the photocoupler U2 is connected to a voltage source P5V, a pin 5 of the photocoupler U2 is connected to one end of a capacitor C17 and is grounded, a pin 6 of the photocoupler U2 is connected to the other end of the capacitor C17 and a voltage source +5Vref, a pin 8 of the photocoupler U2 is connected to a voltage source +5V, and a pin 7 of the photocoupler U2 is connected to output a VRU voltage signal to a CPU; a 2 pin of a connector TM3 is connected with an S-phase power supply of the frequency converter and is sequentially connected with one ends of resistors R7-R12, a lead between the resistor R11 and the resistor R12 is connected with a 2 pin of a photoelectric coupler U3 and one end of a capacitor C22, 3 and 4 pins of the photoelectric coupler U3 are connected with the other end of the capacitor C22 and are grounded, a 1 pin of a photoelectric coupler U3 is connected with a P5V voltage source, a 5 pin of a photoelectric coupler U3 is connected with one end of the capacitor C23 and are grounded, a 6 pin of the photoelectric coupler U3 is connected with the other end of the capacitor C23 and a +5Vref voltage source, an 8 pin of the photoelectric coupler U3 is connected with a +5V voltage source, and a 7 pin of the photoelectric coupler U3 outputs VSV voltage signals to a CPU; the 3 pins of the connector TM3 are connected with an S-phase power supply of the frequency converter and are sequentially connected with one ends of resistors R16-R21, a lead between the resistor R20 and the resistor R21 is connected with the 2 pins of a photoelectric coupler U4 and one end of a capacitor C27, the 3 pins and the 4 pins of the photoelectric coupler U4 are connected with the other end of the capacitor C27 and are grounded, the 1 pin of the photoelectric coupler U4 is connected with a P5V voltage source, the 5 pin of the photoelectric coupler U4 is connected with one end of the capacitor C29 and is grounded, the 6 pin of the photoelectric coupler U4 is connected with the other end of the capacitor C29 and a +5Vref voltage source, the 8 pin of the photoelectric coupler U4 is connected with a +5V voltage source, and the 7 pin of the photoelectric coupler U4 outputs a VTW voltage signal to the CPU.
Furthermore, the QCPL-752H linear photocouplers are adopted as the photocouplers U2-U4, and the linear photocouplers are low in price and have the advantages of being high in bandwidth, high in voltage isolation, excellent in gain and good in linearity and the like.
The working principle of the utility model is as follows: r, S, T three-phase power supply output by the frequency converter is respectively connected to 3 pins of an interface TM3, and after resistance voltage division attenuation is carried out through serially connected resistors, voltage signals after voltage division respectively enter a photoelectric coupler U2 to be subjected to strong and weak current isolation and then three-phase voltage signals of VRU, VSV and VTW are output.
The above description is only for the preferred embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (2)
1. A grid voltage sampling circuit comprising a connector TM3, characterized by: a pin 1 of the connector TM3 is connected with an R-phase power supply of a frequency converter and is sequentially connected with one ends of resistors R1-R6, a lead between the resistor R5 and the resistor R6 is connected with a pin 2 of a photoelectric coupler U2 and one end of a capacitor C15, pins 3 and 4 of the photoelectric coupler U2 are connected with the other end of the capacitor C15 and are grounded, a pin 1 of the photoelectric coupler U2 is connected with a P5V voltage source, a pin 5 of the photoelectric coupler U2 is connected with one end of the capacitor C17 and is grounded, a pin 6 of the photoelectric coupler U2 is connected with the other end of the capacitor C17 and a voltage source Vref +5, a pin 8 of the photoelectric coupler U2 is connected with a voltage source V +5, and a pin 7 of the photoelectric coupler U2 outputs a VRU voltage signal to a CPU; a 2 pin of the connector TM3 is connected with an S-phase power supply of a frequency converter and is sequentially connected with one ends of resistors R7-R12, a lead between the resistor R11 and the resistor R12 is connected with a 2 pin of a photoelectric coupler U3 and one end of a capacitor C22, 3 pins and 4 pins of the photoelectric coupler U3 are connected with the other end of the capacitor C22 and are grounded, a 1 pin of the photoelectric coupler U3 is connected with a P5V voltage source, a 5 pin of the photoelectric coupler U3 is connected with one end of the capacitor C23 and is grounded, a 6 pin of the photoelectric coupler U3 is connected with the other end of the capacitor C23 and a +5 voltage source Vref, an 8 pin of the photoelectric coupler U3 is connected with a +5V voltage source, and a 7 pin of the photoelectric coupler U3 outputs a VSV voltage signal to a CPU; the 3 pins of the connector TM3 are connected with an S-phase power supply of a frequency converter and are sequentially connected with one ends of resistors R16-R21, a lead between the resistor R20 and the resistor R21 is connected with a 2 pin of a photoelectric coupler U4 and one end of a capacitor C27, 3 pins and 4 pins of the photoelectric coupler U4 are connected with the other end of the capacitor C27 and are grounded, a 1 pin of the photoelectric coupler U4 is connected with a P5V voltage source, a 5 pin of the photoelectric coupler U4 is connected with one end of the capacitor C29 and is grounded, a 6 pin of the photoelectric coupler U4 is connected with the other end of the capacitor C29 and a +5 voltage source Vref, an 8 pin of the photoelectric coupler U4 is connected with a +5V voltage source, and a 7 pin of the photoelectric coupler U4 outputs a VTW voltage signal to a CPU.
2. A grid voltage sampling circuit according to claim 1, wherein: the photocouplers U2 to U4 adopt QCPL-752H linear photocouplers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123408809.2U CN217332595U (en) | 2021-12-31 | 2021-12-31 | Grid voltage sampling circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123408809.2U CN217332595U (en) | 2021-12-31 | 2021-12-31 | Grid voltage sampling circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN217332595U true CN217332595U (en) | 2022-08-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123408809.2U Active CN217332595U (en) | 2021-12-31 | 2021-12-31 | Grid voltage sampling circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN217332595U (en) |
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2021
- 2021-12-31 CN CN202123408809.2U patent/CN217332595U/en active Active
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