CN215496706U

CN215496706U - Semiconductor packaging structure

Info

Publication number: CN215496706U
Application number: CN202120628154.0U
Authority: CN
Inventors: P·莫纳德盖米
Original assignee: Micron Technology Inc
Current assignee: Micron Technology Inc
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2022-01-11
Anticipated expiration: 2031-03-26

Abstract

The present application relates to semiconductor package structures. The semiconductor package structure according to the present application includes: a first substrate, a plurality of chips, an electronic component, a thermal conduction element, an encapsulation, and a thermal conduction layer. A plurality of chips stacked on a top surface of a first substrate; electronic components are disposed on top surfaces of the plurality of chips; the thermally conductive element is disposed adjacent to a top surface of the electronic component; an encapsulation member disposed on the top surface of the first substrate and encapsulating the plurality of chips, the electronic component and the heat conduction element; and a thermally conductive layer is disposed adjacent to the top surface of the encapsulant, wherein the thermally conductive layer is thermally connected with the electronic component through the thermally conductive element. The semiconductor packaging structure provided by the application can provide a heat conduction path for the electronic component in the semiconductor packaging structure through the arrangement of the heat conduction element so as to release heat concentration generated by operation of the electronic component with high energy consumption in the semiconductor packaging structure.

Description

Semiconductor packaging structure

Technical Field

The present application relates to the field of semiconductors, and more particularly, to a semiconductor package structure.

Background

Nowadays, semiconductor encapsulation is widely used in most electronic products, such as smart phones, mobile electronic devices or electric vehicles, and the safety performance thereof is strictly required. In the field of semiconductor packaging technology, with the improvement of semiconductor usage and performance, semiconductor devices are moving toward high power and high density. As semiconductor packages have become more and more demanding in terms of operation and power consumption, the heat generated by electronic components thereof has increased, especially for high power consumption electronic components (e.g., control chips, DRAMs, etc.). The effects of the heat distribution generated in the semiconductor package structure on the operation performance and safety performance of the structure need to be paid attention and studied.

In the conventional semiconductor package structure, in order to further increase the chip density per unit area in the package structure, a semiconductor package structure design in which an electronic component is combined with a plurality of chip stacking structures and the electronic component is disposed on the top or bottom of the plurality of chip stacking structures is one of the methods for optimizing the chip structure. However, for high energy consuming electronic components, the combination with multiple chip stacking structures can reduce their thermal conduction paths, which can result in heat concentration areas at the high energy consuming electronic components within the semiconductor package structure, which can, in severe cases, result in overheating of the package structure, damage to the electronic components, and even fire.

Therefore, there are many technical problems to be solved in the art regarding how to avoid the heat concentration phenomenon inside the semiconductor package structure and improve the heat spreading thereof.

SUMMERY OF THE UTILITY MODEL

An objective of the present invention is to provide a semiconductor package structure capable of providing a heat conduction path to reduce uneven heat distribution caused by high-power-consumption electronic components in the semiconductor package structure, thereby providing good package quality and improving safety performance.

According to some embodiments of a first aspect of the present application, there is provided a semiconductor package structure, comprising: a first substrate, a plurality of chips, an electronic component, a thermal conduction element, an encapsulation, and a thermal conduction layer. A plurality of chips stacked on a top surface of a first substrate; electronic components are disposed on top surfaces of the plurality of chips; the thermally conductive element is disposed adjacent to a top surface of the electronic component; an encapsulation member disposed on the top surface of the first substrate and encapsulating the plurality of chips, the electronic component and the heat conduction element; and a thermally conductive layer is disposed adjacent to the top surface of the encapsulant, wherein the thermally conductive layer is thermally connected with the electronic component through the thermally conductive element.

In some embodiments, a thermally conductive layer is disposed to surround a side surface of the encapsulation and a side surface of the first substrate.

In some embodiments, the thermally conductive layer is electrically coupled to a substrate ground of the first substrate, and the thermally conductive layer is configured as a radio frequency shield.

In some embodiments, the semiconductor package structure further includes an external connection electrically and thermally coupled to the substrate ground of the first substrate.

In some embodiments, the external connection is electrically connected to the second substrate.

In some embodiments, the thermally conductive element comprises a first conductive wire and/or a conductive post.

In some embodiments, the top surface of the electronic component is an active surface and the thermally conductive element is connected to a ground port on the active surface.

In some embodiments, the number of first conductive lines and/or conductive pillars is 10% to 50% of the total number of input/output ports on the active face.

In some embodiments, the electronic component is electrically connected to the first substrate by a second conductive line, wherein a maximum height of the second conductive line above the electronic component is less than a minimum distance between a top surface of the electronic component and the heat conductive layer.

According to some embodiments of the second aspect of the present application, there is provided a semiconductor package structure, comprising: a first substrate, an electronic component, a plurality of chips, a film, a heat conduction element, an encapsulation, and a heat conduction layer. An electronic component disposed on a top surface of the first substrate; the thermally conductive element is disposed adjacent to a top surface of the electronic component; a film disposed on a top surface of the electronic component and encapsulating at least a portion of the heat conducting element; a plurality of chips stacked on a top surface of the film; an encapsulation member disposed on the top surface of the first substrate and encapsulating the plurality of chips, the electronic component, the film, and the heat conduction element; and a heat conductive layer disposed to surround the top surface and the side surface of the encapsulation, wherein the heat conductive layer is thermally connected with the electronic component through a heat conductive element, wherein the heat conductive element includes a first conductive line.

In some embodiments, the first conductive line directly contacts the thermally conductive layer.

In some embodiments, the top surface of the electronic component is a passivation surface and the electronic component is flip-chip connected to the first substrate.

In some embodiments, the semiconductor package structure further comprises a spacer and a second conductive line. A spacer disposed between the top surface of the first substrate and the membrane; and the second conductive line is coupled to the spacer, wherein the spacer is thermally coupled to the first conductive line and the second conductive line is thermally coupled to the thermally conductive layer.

In some embodiments, the first conductive line is connected to the first substrate and to the spacer from the first substrate.

In some embodiments, the top surface of the electronic component is an active surface and the first wire is connected to a ground port on the active surface.

In some embodiments, the number of first conductors is 10% to 50% of the total number of input/output ports on the active surface.

In some embodiments, the film is disposed adjacent to a top surface of the first substrate and encapsulates the electronic component.

In some embodiments, a maximum height of the first conductive lines above the electronic component is less than a minimum distance between a top surface of the electronic component and the plurality of chips.

In some embodiments, a thermally conductive layer is disposed to surround a side surface of the first substrate, and the thermally conductive layer is electrically coupled to a substrate ground of the first substrate, wherein the thermally conductive layer is configured as a radio frequency shield.

In some embodiments, the semiconductor package structure provided by the present application can provide one or more thermal conduction paths for electronic components disposed on the top or bottom of the stacked plurality of chips inside the semiconductor package structure by disposing the thermal conduction element, so as to release heat concentration generated by operation of the electronic components with high energy consumption in the semiconductor package structure. Therefore, the semiconductor packaging structure has good product quality and high safety.

Additional aspects and advantages provided by the present application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of the present application.

Drawings

Drawings necessary for describing embodiments of the present application or the prior art will be briefly described below in order to describe the embodiments of the present application. It is to be understood that the drawings in the following description are only some of the embodiments of the present application. It will be apparent to those skilled in the art that other embodiments of the drawings can be obtained from the structures illustrated in these drawings without the need for inventive work.

Fig. 1 is a schematic longitudinal cross-sectional view of a semiconductor package structure 10 according to an embodiment of the present application.

Fig. 2 is a schematic longitudinal cross-sectional view of a semiconductor package structure 20 according to an embodiment of the present application.

Fig. 3 is a schematic longitudinal cross-sectional view of a semiconductor package structure 30 according to an embodiment of the present application.

Fig. 4 is a schematic top view of a semiconductor package structure according to an embodiment of the present application.

Fig. 5 is a schematic longitudinal cross-sectional view of a semiconductor package structure 40 according to an embodiment of the present application.

Fig. 6 is a schematic longitudinal cross-sectional view of a semiconductor package structure 50 according to an embodiment of the present application.

Fig. 7 is a schematic longitudinal cross-sectional view of a semiconductor package structure 60 according to an embodiment of the present application.

Fig. 8A-E are schematic flow diagrams of fabricating a semiconductor package structure with an electronic component disposed on top of a stacked plurality of chip structures, according to an embodiment of the present application.

Fig. 9A-F are schematic flow diagrams of fabricating a semiconductor package structure with electronic components disposed on a lower portion of a stacked multiple chip structure according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below. Throughout the specification, the same or similar components and components having the same or similar functions are denoted by like reference numerals. The embodiments described herein with respect to the figures are illustrative in nature, are diagrammatic in nature, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as limiting the present application.

As used herein, the terms "about", "substantially", "essentially" are used to describe and describe small variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs in close proximity. For example, when used in conjunction with numerical values, the term can refer to a range of variation that is less than or equal to ± 10% of the numerical value, such as less than or equal to ± 5%, less than or equal to ± 0.5%, or less than or equal to ± 0.05%. For example, two numerical values may be considered "substantially" the same if the difference between the two values is less than or equal to ± 10% of the mean of the values.

Moreover, for convenience in description, "first," "second," "third," etc. may be used herein to distinguish between different elements of a figure or series of figures. "first," "second," "third," etc. are not intended to describe corresponding components.

In this application, unless specified or limited otherwise, "disposed," "connected," "coupled," "secured," and words of similar import are used broadly and those skilled in the art will understand that the words used above apply to situations in which, for example, a fixed connection, a removable connection, or an integrated connection; it may also be a mechanical, thermal or electrical connection; they may also be directly connected or indirectly connected through intervening structures.

In the semiconductor field, as the power and density of electronic components in a semiconductor package structure are increasing, the electronic components with high energy consumption in the semiconductor package structure need a more efficient heat conduction manner during operation to remove a large amount of heat generated by the electronic components, especially for mobile electronic appliances without a heat dissipation device.

For example, a control chip in a NAND memory package is a high-power electronic component, which generates a large amount of heat energy during operation, and thus the temperature of the control chip region in the NAND memory package is higher than that of other regions, and the regions with too large temperature difference cause different thermal expansion ratios between different regions, which may cause the semiconductor package structure to bend or even deform in severe cases. Meanwhile, in the absence of a heat dissipation path, the heat concentration region may cause overheating of the electronic component, and in a serious case, may cause short circuit, damage, or even fire burning of the semiconductor package structure. In addition, the heat transmission path of the electronic component is influenced by the design of the package structure, and especially when the electronic component in the semiconductor package structure adopts a design arranged at the bottom or the top of a plurality of chip stacking structures, although the design can effectively improve the chip density in a unit area of the semiconductor package structure, the heat dissipation path of the electronic component in the chip stacking structure is reduced, and the structure cannot improve the heat dissipation performance of the electronic component by adding the existing heat sink.

In view of the above problems, the present application provides a heat distribution path inside the semiconductor package structure and an outward heat spreading path when various components in the semiconductor package structure generate heat during operation to form uneven heat distribution by providing a heat conduction element on the top surface of a high-energy-consumption electronic component, thereby reducing heat concentration and possible damage or deformation of the semiconductor package structure during operation, and effectively improving the operation life and safety of the semiconductor package structure.

According to some embodiments of the first aspect of the present application, when the electronic component is disposed on top of the stacked plurality of chip structures, the heat conduction element disposed on the top surface of the electronic component of the present application can directly contact the heat conduction layer in a vertical direction of the semiconductor package structure to provide a heat conduction path. The settings of the specific embodiment are explained as follows:

fig. 1-3 are respective longitudinal cross-sectional schematic views of semiconductor package structures according to some embodiments of the present application.

As shown in fig. 1, a semiconductor package structure 10 according to some embodiments of the present application can include: a first substrate 100, a plurality of chips 101, electronic components 102, heat conducting elements, an encapsulation 104 and a heat conducting layer 105.

The first substrate 100 has a top surface 100t and a bottom surface 100 b. The top surface 100t and the bottom surface 100b may be substantially flat surfaces. In some embodiments, the first substrate 100 may include one or more bond pads disposed on the top surface 100t for electrical connection with any other type of electronic component. In some embodiments, bottom surface 100b may include any manner of attachment structure provided as desired. In some embodiments, the first substrate 100 may include one or more bond pads disposed proximate the bottom surface 100b for electrical connection with other electronic components located outside the semiconductor package structure 10. In some embodiments, the first substrate 100 may include a plurality of layers, which may include dielectric layers, metal layers, and electrical connections (via) connecting the layers, as is common in the art. In some embodiments, the first substrate 100 includes a substrate ground 100a, and the substrate ground 100a may be disposed in the first substrate 100 for ground connection with any other type of electronic element. In some embodiments, the substrate ground 100a can be exposed on a portion of one or more of the top surface 100t, the bottom surface 100b, or the side surfaces of the first substrate 100 according to chip ground requirements in the package structure. In some embodiments, the substrate ground 100a may also serve as an interposer to couple electronic components in the semiconductor package to the external connection 106. In some embodiments, the first substrate 100 may be composed of any suitable type of substrate material.

A plurality of chips 101 are stacked on the top surface 100t of the first substrate 100. The plurality of chips 101 can include at least one chip or more. The chips of the plurality of chips may be any type of die or die, for example, but not limited to, the chips may be memories, etc. In some embodiments, the chip includes a NAND chip. In some embodiments, the stacked structure of the plurality of chips 101 includes a shingled stack and an inverted shingled stack. In some embodiments, the stacking structure of the plurality of chips 101 may be a single-chip stack or a multi-chip stack. It should be understood that the size and number of chips in the plurality of chips 101 can be adjusted according to the chip design, the package size, and the like, and is not limited thereto. In some embodiments, the chips of the plurality of chips 101 are bonded by a Die Attach Film (DAF). Bonding of the bottom surfaces of the plurality of chips 101 to the top surface 100t of the first substrate 100 may be a common arrangement in the art, such as, but not limited to, direct contact bonding, adhesive bonding.

The electronic components 102 are disposed on the top surfaces 101t of the plurality of chips 101. In some embodiments, the electronic component 102 is bonded to the top surfaces 101t of the plurality of chips 101 by a die attach film DAF. The electronic component 102 may be any type of die or chip, for example, but not limited to, the electronic component 102 may be a memory, a processor, or an interdigital transducer, and the like. The electronic component 102 may be a high-power electronic component or a low-power electronic component. In some embodiments, the electronic component 102 is a high energy consuming electronic component, such as, but not limited to: a control chip, a processor, or a DRAM.

The thermally conductive element is disposed adjacent to the top surface 102t of the electronic component 102. In some embodiments, the thermally conductive element includes a first conductive line 103a and/or a conductive post 103 b. Referring to fig. 1, the semiconductor package 10 employs the first conductive traces 103a as heat conduction elements. Referring to fig. 2, the heat conduction element of the semiconductor package structure 20 is a conductive pillar 103 b.

Compared with the conducting wire, the conducting rod has a thicker diameter, so that the heat conduction efficiency can be improved. However, the conductive wires are easier to arrange than the conductive posts, so that the manufacturing cost can be reduced. In some embodiments, the first conductive line 103a and/or the conductive post 103b may be conductive lines or posts as is common in the art. In some embodiments, the thermally conductive element comprises a material having a high coefficient of thermal conductivity, such as, but not limited to, gold, silver, copper, and the like. In some embodiments, the material of the thermally conductive element may be an electrically conductive material as is common in the art, including, but not limited to, gold, silver, copper, and the like.

The thermally conductive element is thermally coupled to the top surface 102t of the electronic component 102. It will be appreciated that the heat transfer elements of the present application may be adjusted in number, area of arrangement, and size according to the actual heat spreading design requirements. Since the heat conduction element of the present application employs the first conductive wire 103a and/or the conductive post 103b, it is not only low in cost but also can be flexibly disposed on the active surface or the passive surface of the electronic component according to the existing structure of the electronic component without being limited thereto. As shown in fig. 1 and 2, in some embodiments, the top surface 102t of the electronic component 102 is an active surface, and the thermally conductive element can be connected to a ground port on the active surface of the electronic component 102 and provide a thermal transport path for the electronic component 102. In some embodiments, the number of first conductive lines and/or conductive pillars is 10% to 50% of the total number of input/output ports on the active face.

The encapsulation 104 is disposed on the top surface 100t of the first substrate 100, and encapsulates the plurality of chips 101, the electronic components 102, and the heat conductive elements. The encapsulant 104 may be formed by an encapsulant as is common in the art.

A thermally conductive layer 105 is disposed adjacent to the top surface of the encapsulation 104. The thermal conductive layer 105 can be thermally connected to the electronic component 102 through the thermal conductive element, so as to further improve the efficiency of heat dissipation from the electronic component 102 to the outside inside of the semiconductor package structure 10. In some embodiments, a portion of the thermally conductive element is exposed from the top surface of the encapsulant 104 and is thermally connected with the thermally conductive layer 105. In some embodiments, the heat conductive layer 105 is in direct contact with the exposed portion of the heat conductive element. In some embodiments, a thermally conductive layer 105 can be disposed to surround the side surface of the encapsulation 104 and the side surface of the first substrate 100.

In some embodiments, the thermal conductive layer 105 comprises a material having a high coefficient of thermal conductivity, such as, but not limited to, copper, aluminum, stainless steel, and the like. The thermally conductive layer 105 may be a single layer or a multi-layer structure. In some embodiments, the heat conductive layer 105 is a single layer structure of stainless steel to provide some protection to the semiconductor package structure while providing a heat dissipation path. In some embodiments, the thickness of the thermally conductive layer 105 is 3 μm to 30 μm.

During operation, the semiconductor packages 10 and 20 are provided with the thermal conduction elements, so that the thermal energy generated by the electronic component 102 can be conducted and distributed through the thermal conduction elements 103a and/or 103 b. Since a portion of the thermal conduction element is exposed from the top surface of the encapsulant 104, the exposed portion of the thermal conduction element 103 can be thermally connected to the thermal conduction layer 105 and provide a thermal conduction path for the

semiconductor package structure

10, 20 to the outside to dissipate heat from the internal electronic components to the outside. Therefore, the semiconductor packaging structure has better heat distribution and better packaging quality and safety.

In some embodiments, the electronic component 102 is electrically connected to the first substrate 100 through the second conductive line 107, wherein a maximum height S1 of the second conductive line 107 above the electronic component is less than a minimum distance S2 between the top surface 102t of the electronic component 102 and the heat conductive layer 105 to maintain a stable electrical connection.

In some embodiments, the

semiconductor package structures

10 and 20 further include external connections 106, the external connections 106 being disposed on the bottom surface 100b of the first substrate 100. In some embodiments, the external connection 106 can be thermally coupled with the bottom surface 100b of the first substrate 100 to further provide a thermal conduction path.

The external connection 106 may or may not have an electrical connection function. In some embodiments, the external connection 106 may be used to externally electrically connect other electronic components. The external connection 106 may be, for example, but not limited to, a solder ball.

In some embodiments, the thermal conductive layer 105 can be further applied as a Radio Frequency (RF) shield in the semiconductor package structure, wherein the thermal conductive layer 105 is electrically coupled to the substrate ground 100a of the first substrate 100 to form a ground structure, so as to shield the semiconductor package structure from electromagnetic interference. In some embodiments, the external connection 106 is capable of being thermally and electrically coupled to the substrate ground 100a from the bottom surface 100b of the first substrate 100, via being thermally and electrically connected to the thermally conductive layer 105, to further provide a thermal conduction path.

Referring to fig. 3, fig. 3 is a schematic longitudinal cross-sectional view of a semiconductor package structure 30 according to an embodiment of the present application. The semiconductor package structure 30 differs from the semiconductor package structure 10 shown in fig. 1 in that the semiconductor package structure 30 further includes a second substrate 200.

As shown in fig. 3, the semiconductor package structure 30 can be electrically and/or thermally coupled to the second substrate 200 through the external connection 106. In some embodiments, the thermally conductive layer 105 is electrically connected to the external connection 106 through the substrate ground 100a of the first substrate 100, wherein the external connection 106 is electrically coupled to the second substrate 200 and grounded through the second substrate 200 to achieve the electromagnetic interference shielding effect. In addition, in some embodiments, the external connection member 106 may be thermally coupled to the second substrate 200, and heat may also be transferred to the second substrate 200 through the thermal conductive layer 105, the substrate ground 100a, and the external connection member 106, thereby dissipating heat through the second substrate 200.

Referring to fig. 4, fig. 4 is a schematic top view of a semiconductor package structure according to the embodiment illustrated in fig. 1 of the present application.

As shown in fig. 4, the electronic component 102 is electrically connected to one or more bond pads on the top surface of the first substrate 100 through second conductive lines 107. The plurality of chips 101 are electrically connected to one or more bonding pads on the top surface of the first substrate 100 through third wires. The first conductive lines 103 are disposed on a top surface of the electronic component 102 and form one or more first conductive line structures.

According to some embodiments of the second aspect of the present application, when the electronic component is disposed at the bottom of the stacked plurality of chip structures, the heat conduction element disposed on the top surface of the electronic component of the present application cannot directly contact the heat conduction layer in the vertical direction of the semiconductor package structure. Therefore, it is necessary to provide a plurality of heat conduction paths by adjusting the structural arrangement of the heat conduction element in the horizontal direction. The settings of the specific embodiment are explained as follows:

fig. 5-7 are respective longitudinal cross-sectional schematic views of semiconductor package structures according to some embodiments of the present application.

As shown in fig. 5-7, a

semiconductor package structure

40, 50, 60 according to some embodiments of the present application includes at least: a first substrate 100, electronic components 102, a plurality of chips 101, a film 201, a heat conducting element, an encapsulation 104, and a heat conducting layer 105.

The electronic components 102 are disposed on the top surface 100t of the first substrate 100. Referring to fig. 5 and 6, in some embodiments, the electronic component 102 can employ a flipped mounted (flipped mounted) to the top surface 100t of the first substrate 100, wherein the bottom surface of the electronic component 102 is an active surface, the top surface 102t of the electronic component 102 is a passive surface, and the active surface of the electronic component 102 is in direct electrical connection with the first substrate 100. Referring to fig. 7, in some embodiments, the electronic component 102 can be disposed directly to the top surface 100t of the first substrate 100, wherein the bottom surface of the electronic component 102 is a passivated surface, the top surface 102t of the electronic component 102 is an active surface, and the active surface of the electronic component 102 is electrically connected to the first substrate 100 by a third wire.

The thermally conductive element is disposed adjacent to the top surface 102t of the electronic component 102. In some embodiments, the thermally conductive element comprises a first conductive line 103 a. The first conductive line 103a is thermally coupled to the top surface 102t of the electronic component 102. In some embodiments, the top surface 102t of the electronic component 102 is a passivated surface, and the first conductive line 103a can be disposed on the passivated surface of the electronic component 102 and provide a thermal transport path for the electronic component 102.

In some embodiments, the top surface 102t of the electronic component 102 is an active surface, and the first wire 103a can be connected to a ground port on the active surface of the electronic component 102 and provide a heat transfer path for the electronic component 102. In some embodiments, the number of first conductive lines 103a is 10% to 50% of the total number of input/output ports on the active surface.

The film 201 is disposed on the top surface 102t of the electronic component 102 and encapsulates at least a portion of the first wires 103a located above the top surface of the electronic component, the film 201 providing the top surface as a stacking surface of the stacked plurality of chips 101. The top and bottom surfaces of the film 201 may be substantially planar surfaces. In some embodiments, the maximum height S3 of the first conductive lines 103a above the electronic component is less than the minimum distance S4 between the top surface 102t of the electronic component 102 and the film 201 to avoid direct contact of the first conductive lines 103a with the stacked plurality of chips 101. In some embodiments, the film 201 may comprise one of a film-over-wire (FOW) or a chip-over-die (FOD). Referring to fig. 5 and 6, in some embodiments, the film 201 is a wire-coated film, which can provide better thermal conductivity. Referring to fig. 7, in some embodiments, the film 201 is a flip-chip film, and the use of the flip-chip film can provide a more stable semiconductor package structure. It should be understood that those skilled in the art can select the desired wire-covering film or chip-covering film according to the actual semiconductor package structure design without limitation. In some embodiments, the thickness of the film 201 is greater than 50 μm.

A plurality of chips 101 are stacked on the top surface of the film 201. The plurality of chips 101 can include at least one chip or more. The chips of the plurality of chips may be any type of die or die, for example, but not limited to, the chips may be memories, etc. In some embodiments, the chip includes a NAND chip. In some embodiments, the stacked structure of the plurality of chips 101 includes a shingled stack and an inverted shingled stack. In some embodiments, the stacking structure of the plurality of chips 101 may be a single-chip stack or a multi-chip stack. It should be understood that the size and number of chips in the plurality of chips 101 can be adjusted according to the chip design, the package size, and the like, and is not limited thereto.

The encapsulation 104 is disposed on the top surface 100t of the first substrate 100, and encapsulates the plurality of chips 101, the electronic components 102, the film 201, and the heat conductive elements. The encapsulant 104 may be formed by an encapsulant as is common in the art.

The heat conductive layer 105 is disposed adjacent to the top surface of the encapsulation 104 and around the side surface of the encapsulation 104. In some embodiments, the thermal conductive layer 105 can be thermally connected to the electronic component 102 through the first conductive line 103a, and further improve the efficiency of heat dissipation from the electronic component 102 to the outside inside of the semiconductor package structure.

Referring to fig. 5 and 6, in some embodiments, the semiconductor package structure further includes a spacer 202, the spacer 202 being disposed between the top surface 100t of the first substrate 100 and the film 201 for supporting the plurality of chips 101 stacked on the top surface of the film 201. The spacer 202 may be any material common in the art, such as, but not limited to, silicon, copper, stainless steel.

In some embodiments, the spacer 202 can be thermally connected with the electronic component 102 through the first wire 103a, and the spacer 202 can act as a heat sink (heat sink) and further reduce the heat concentration of the electronic component 102 inside the semiconductor package structure 40. Referring to fig. 5, in some embodiments, the first conductive line 103a is first connected to the substrate ground of the first substrate 100 and is connected to the spacer 202 from the first substrate 100. Referring to fig. 6, in some embodiments, the first conductive line 103a is directly connected to the spacer 202. It should be understood that, based on the teachings of the embodiments of the present application, the arrangement of the first conductive lines 103a and the spacers 202 may be adjusted by those skilled in the art according to the design of the actual semiconductor package structure, and is not limited thereto. In some embodiments, the spacers 202 comprise a material having a high coefficient of thermal conductivity, such as, but not limited to, copper, aluminum, stainless steel, and the like. In some embodiments, the spacers 202 are silicon with a copper layer plated on the surface.

In some embodiments, the semiconductor package structure further includes a fourth conductive line 203, the fourth conductive line 203 is configured to be thermally coupled to the spacer 202, and a portion of the fourth conductive line 203 is exposed from a side surface of the encapsulation 104 and directly contacts the thermal conductive layer 105 to form a thermal connection with the thermal conductive layer 105, such that the spacer 202 can be thermally connected with the thermal conductive layer 105 through the fourth conductive line 203, thereby forming a thermal conduction path from the electronic component 102 to the thermal conductive layer 105 through the first conductive line 103a, the spacer 202 and the fourth conductive line 203.

Referring to fig. 7, in some embodiments, the electronic component 102 in the semiconductor package structure can be disposed near a side of the semiconductor package structure, and a portion of the first conductive trace 103a thereof can be exposed from a side surface of the encapsulation 104 and directly contact the thermal conductive layer 105 to form a thermal connection with the thermal conductive layer 105. In some embodiments, the heat conductive layer 105 is in direct contact with and forms a thermal connection with the exposed portion of the first conductive line 103 a.

In some embodiments, the heat conductive layer 105 can be further applied as a Radio Frequency (RF) shield in the semiconductor package structure, and the specific structure thereof is already described in the previous section and is not described herein again. Referring to fig. 6, the semiconductor package structure 60 can further include an external connection component 106, and the specific structure thereof is described in the previous section and is not described herein again.

Fig. 8A, 8B, 8C, 8D, and 8E are flow diagrams of manufacturing a semiconductor package structure with electronic components disposed on top of stacked multiple chip structures according to embodiments of the present application, which may manufacture the semiconductor package structure 10 shown in fig. 1, for example.

As shown in fig. 8A, a first substrate 100 is provided, which may include a plurality of layers, including dielectric layers, metal layers, and electrical connections (via) connecting the layers, as is common in the art. The substrate may be comprised of any suitable type of substrate material. A plurality of chips 101 are stacked on a first substrate 10, and electronic components 102 are disposed on top surfaces of the plurality of chips 101, and the arrangement of the plurality of chips 101 and the electronic components 102 may be provided by any suitable bonding method in the art, for example, die attach film DAF bonding. Subsequently, the first conductive line 103a, the second conductive line 107 and the third conductive line are respectively disposed, wherein the height of the first conductive line 103a above the top surface of the electronic component 102 must be higher than the height of the second conductive line 107. The arrangement order of the first conductive line 103a, the second conductive line 107 and the third conductive line can be adjusted by those skilled in the art according to the preparation requirement. In addition, those skilled in the art may employ conductive pillars instead of the first conductive lines.

Next, as shown in fig. 8B, the plurality of chips 101, the electronic component 102, the first wires 103a, and the second wires 107 are encapsulated with an encapsulant on the first surface 100A of the first substrate 100 to form an encapsulation 104.

As shown in fig. 8C, next, an individual semiconductor package structure may be further formed through a cutting, dividing, polishing process, and the top surface 104t of the encapsulation 104 is ground until the first wires 103a are exposed while avoiding the second wires 107 from being exposed. In some embodiments, the substrate ground 100a in the first substrate 100 can be exposed on the side surface of the first substrate 100 during the cutting, dividing and polishing processes.

As shown in fig. 8D, the external connection members 106 are provided, and a person skilled in the art can adjust the arrangement order of the external connection members 106 according to the preparation requirement.

Next, as shown in fig. 8E, a heat conductive layer 105 is provided on the top and side surfaces of the encapsulation 104 and the side surface of the first substrate 100 by a sputtering process. The heat conductive layer 105 is in contact with a portion of the first conductive line 103a exposed from the top surface 104t of the encapsulation 104. It is understood that the heat conductive layer 105 may be provided using any suitable process known in the art without departing from the spirit of the present application, such as, but not limited to, a sputtering process, a physical vapor deposition process, and the like. In some embodiments, the substrate ground 100a exposed on the side surface of the first substrate 100 can be electrically and thermally coupled with the thermal conductive layer 105 to obtain the semiconductor package structure 10 as shown in fig. 1.

Fig. 9A, 9B, 9C, 9D, 9E, and 9F are flow diagrams of manufacturing a semiconductor package structure in which an electronic component is disposed at the bottom of a stacked plurality of chip structures according to an embodiment of the present application, which can manufacture the semiconductor package structure 40 shown in fig. 5, for example.

As shown in fig. 9A, a first substrate 100 is provided, which may include a plurality of layers, including dielectric layers, metal layers, and electrical connections (via) connecting the layers, as is common in the art. The substrate may be comprised of any suitable type of substrate material. Electronic components 102 are provided on the first substrate 10, and the arrangement of the electronic components 102 may be provided by any suitable bonding method in the art, for example, die attach film DAF bonding. The arrangement of the electronic components 102 may be a direct arrangement or a flipped arrangement, depending on design choice. In some embodiments, the preparing step further comprises disposing spacers 202 on the first substrate 10.

Next, as shown in fig. 9B, the first wire 103a and/or the second wire 203 are provided to form a thermal connection structure. The arrangement position and the connection structure of the first wire 103a and/or the second wire 203 can be adjusted by those skilled in the art according to the design. In some embodiments, the ends of the first conductive line 103a and/or the second conductive line 203 may be disposed on the top surface 100t of the substrate 100.

As shown in fig. 9C, next, a film 201 is provided to cover the first wire 103a and/or the second wire 203 on the top surface of the electronic component 102. In some embodiments, the film 201 can be further disposed on the top surface 100t of the first substrate 100 and encases the electronic components 102. Subsequently, a plurality of chips 101 are stacked on the top surface of the film 201.

As shown in fig. 9D, the plurality of chips 101, the electronic components 102, the film 201, and the first wires 103a are encapsulated with an encapsulant on the first surface 100A of the first substrate 100 to form an encapsulant 104.

As shown in fig. 9E, an individual semiconductor package structure may be further formed through a cutting, dividing, and polishing process by which the ends of the first wires 103a and/or the second wires 203 disposed on the top surface 100t of the first substrate 100 can be exposed on the side surface of the encapsulation 104. Subsequently, the external connection members 106 are provided, and those skilled in the art can adjust the order of the external connection members 106 according to the preparation requirements.

Finally, as shown in fig. 9F, a heat conductive layer 105 is provided on the top and side surfaces of the encapsulation 104 and the side surfaces of the first substrate 100 by a sputtering process. The heat conductive layer 105 is in contact with portions of the first conductive lines 103a and/or the second conductive lines 203 exposed from the side surface 104t of the encapsulation 104. It is understood that the heat conductive layer 105 may be provided using any suitable process known in the art without departing from the spirit of the present application, such as, but not limited to, a sputtering process, a physical vapor deposition process, and the like.

The technical content and technical features of the present application have been disclosed as above, however, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present application without departing from the spirit of the present application. Therefore, the protection scope of the present application should not be limited to the disclosure of the embodiments, but should include various alternatives and modifications without departing from the scope of the present application, which is encompassed by the claims of the present application.

Claims

1. A semiconductor package structure, comprising:

a first substrate; and

a plurality of chips stacked on a top surface of the first substrate,

wherein the semiconductor package structure further comprises:

an electronic component disposed on top surfaces of the plurality of chips;

a thermally conductive element disposed adjacent to a top surface of the electronic component;

an encapsulant disposed on the top surface of the first substrate and encapsulating the plurality of chips, the electronic components, and the heat conduction elements; and

a thermally conductive layer disposed adjacent to a top surface of the encapsulation, wherein the thermally conductive layer is thermally connected with the electronic component through the thermally conductive element.

2. The semiconductor package structure of claim 1, wherein the thermally conductive layer is disposed to surround a side surface of the encapsulant and a side surface of the first substrate.

3. The semiconductor package structure of claim 2, wherein the thermally conductive layer is electrically coupled to a substrate ground of the first substrate, and the thermally conductive layer is configured as a radio frequency shield.

4. The semiconductor package structure of claim 3, further comprising an external connection electrically and thermally coupled to ground of the substrate of the first substrate.

5. The semiconductor package structure of claim 4, wherein the external connection is electrically connected to the second substrate.

6. The semiconductor package structure of claim 1, wherein the thermal conduction element comprises a first conductive wire and/or a conductive post.

7. The semiconductor package structure of claim 6, wherein the top surface of the electronic component is an active face and the thermally conductive element is connected to a ground port on the active face.

8. The semiconductor package structure of claim 7, wherein the number of the first conductive lines and/or the conductive pillars is 10% to 50% of the total number of input/output ports on the active surface.

9. The semiconductor package structure of claim 1, wherein the electronic component is electrically connected to the first substrate by a second conductive line, wherein a maximum height of the second conductive line above the electronic component is less than a minimum distance between the top surface of the electronic component and the thermal conductive layer.

10. A semiconductor package structure, comprising:

a first substrate; and

an electronic component disposed on a top surface of the first substrate,

wherein the semiconductor package structure further comprises:

a film disposed on the top surface of the electronic component and encapsulating at least a portion of the heat conducting element;

a plurality of chips stacked on a top surface of the film;

an encapsulant disposed on the top surface of the first substrate and encapsulating the plurality of chips, the electronic components, the film, and the heat conductive elements; and

a heat conductive layer disposed to surround a top surface and a side surface of the encapsulation,

wherein the thermally conductive layer is thermally connected to the electronic component through the thermally conductive element, wherein the thermally conductive element comprises a first conductive line.

11. The semiconductor package structure of claim 10, wherein the first conductive line directly contacts the thermal conductive layer.

12. The semiconductor package structure of claim 10, wherein the top surface of the electronic component is a passivation surface and the electronic component is flip-chip connected to the first substrate.

13. The semiconductor package structure of claim 12, further comprising

A spacer disposed between the top surface of the first substrate and the membrane; and

a second conductive line coupled to the spacer,

wherein the spacer is thermally coupled to the first conductive line and the second conductive line is thermally coupled to the thermal conductive layer.

14. The semiconductor package structure of claim 13, wherein the first wire is connected to the first substrate and from the first substrate to the spacer.

15. The semiconductor package structure of claim 10, wherein the top surface of the electronic component is an active surface and the first wire is connected to a ground port on the active surface.

16. The semiconductor package structure of claim 15, wherein the number of the first conductive lines is 10% to 50% of the total number of input/output ports on the active surface.

17. The semiconductor package structure of claim 15, wherein the film is disposed adjacent to the top surface of the first substrate and encapsulates the electronic component.

18. The semiconductor package structure of claim 10, wherein a maximum height of the first conductive line above the electronic component is less than a minimum distance between the top surface of the electronic component and the plurality of chips.

19. The semiconductor package structure of claim 10, wherein the thermal conductive layer is disposed to surround a side surface of the first substrate and is electrically coupled to a substrate ground of the first substrate, wherein the thermal conductive layer is configured as a radio frequency shield.

20. The semiconductor package structure of claim 19, further comprising an external connection electrically and thermally coupled to ground of the substrate of the first substrate.

21. The semiconductor package structure of claim 20, wherein the external connection is electrically connected to the second substrate.