CN101887885B - Stacking structure of semiconductor packages - Google Patents
Stacking structure of semiconductor packages Download PDFInfo
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- CN101887885B CN101887885B CN 200910051149 CN200910051149A CN101887885B CN 101887885 B CN101887885 B CN 101887885B CN 200910051149 CN200910051149 CN 200910051149 CN 200910051149 A CN200910051149 A CN 200910051149A CN 101887885 B CN101887885 B CN 101887885B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
The invention discloses a stacking structure of semiconductor packages, which comprises a first package, a second package and a plurality of switching elements. The first package is provided with a first circuit board, at least one first chip and at least one first package colloid. The first circuit board is provided at least one depression and a plurality of switching solder pads, the depression accommodates the first chip, and the first package colloid fills the depression and covers the first chip. The switching solder pads are formed on the upper surface of the first circuit board where no depression is arranged. The lower surface of the second package is electrically connected with the switching solder pad of the first circuit board of the first package through the switching element. Because the depression accommodates the chip, the protrusion height caused by the chip and the package colloid can be reduced, and the overall stacking height during stacking assembly can be further reduced.
Description
[technical field]
The invention relates to a kind of stacking construction of semiconductor package body, particularly relevant for a kind of stacking construction that can effectively reduce the semiconductor package body of integral stacked height.
[background technology]
Now; The semiconductor packages industry is in order to satisfy the demand of various high-density packages; Develop the packaging structure that various different types gradually, (system in package, SIP) design concept is usually used in framework high-density packages structure to wherein various system in package.Generally speaking, system in package can be divided into multi-chip module (multi chip module, MCM), stacked package body on the packaging body (package on package, stacked package body POP) and in the packaging body (package in package, PIP) etc.Said multi-chip module (MCM) is meant lays several chips on same substrate; After chip is set; Utilize same all chips of packing colloid embedding again, and can it be subdivided into stacked chips (stacked die) encapsulation or chip (side-by-side) encapsulation side by side again according to the arrangements of chips mode.Moreover; The structure of stacked package body (POP) is meant that completion one earlier has first packaging body of substrate on the said packaging body; Then pile up another second complete packaging body in the packing colloid upper surface of first packaging body again; Second packaging body can see through suitable switching element and be electrically connected on the substrate of first packaging body, thereby becomes a compound packaging structure.In comparison; The structure of stacked package body (PIP) then is further to utilize another packing colloid that embedding such as the former encapsulation colloid of second packaging body, switching element and first packaging body etc. together is fixed on the substrate of first packaging body in the said packaging body, thereby becomes a compound packaging structure.
For instance; Please with reference to shown in Figure 1; It discloses the composite construction of stacked package body (POP) on a kind of existing packaging body; It comprises one first packaging body 11, one second packaging body 12 and a switching circuit board 13, wherein said first packaging body 11 and second packaging body 12 all belong to ball grid array packaging structure (ball gridarray, BGA).The upper surface of said first packaging body 11 carries one first chip 111, and has said first chip 111 of one first packing colloid, 112 coatings, and the lower surface of said first packaging body 11 then combines several tin balls 113.The upper surface of said second packaging body 12 carries one or more second chips 121, and has said second chip 121 of one second packing colloid, 122 coatings.Said switching circuit board 13 is ring circuit plates, and its lower surface and upper surface combine several first switching metal ball 131 and several second switching metal ball 132 respectively.When piling up, utilize first and second switching metal ball 131,132 of said switching circuit board 13 can electrically connect said first and second packaging body 11,12 indirectly, so can constitute the composite construction of stacked package body (POP) on the packaging body.
As shown in Figure 1; Because said first packing colloid 112 has quite height; And said first and second switching metal ball 131,132 can't manufacture the size of the enough height of tool, therefore must utilize said switching circuit board 13 to transfer and combine said first and second packaging body 11,12.Though the composite construction of stacked package body can reach the effect of high-density packages on the existing packaging body; But but be unfavorable for reducing the integral stacked height that piles up after the assembling; The advantage of volume miniaturization just can't be provided, be unfavorable for being applied to the field of miniaturization electronics products such as mobile phone.Moreover, use said switching circuit board 13 also can increase the assembled material cost when piling up relatively.In addition; When assembling; Said first and second switching metal ball 131,132 must be carried out 2 contrapositions assembling with said first and second packaging body 11,12 respectively; Relative also the raising assembled required time and complexity, and can increase the risk of yields (yield) decline that causes because of assembling contraposition failure.
Die, be necessary to provide a kind of stacking construction of semiconductor package body, to solve the existing in prior technology problem.
[summary of the invention]
Main purpose of the present invention is to provide a kind of stacking construction of semiconductor package body; Wherein provide depression to hold chip by substrate; To reduce the rising height that chip and packing colloid cause; And then make packaging body and another packaging body when piling up assembling, and can directly utilize small size switching metal ball to reach the switching purpose, therefore help reducing the integral stacked height, reduce and pile up assembly cost, simplify and pile up the yields that assembling is piled up in assembling flow path and raising.
Secondary objective of the present invention is to provide a kind of stacking construction of semiconductor package body; Wherein provide depression to hold chip by substrate; And the internal face of depression can be provided with heat radiation coating, therefore helps improving the radiating efficiency and ELECTROMAGNETIC OBSCURANT (EMI shielding) efficient of stacking construction.
Another object of the present invention is to provide a kind of stacking construction of semiconductor package body; Wherein provide depression to hold chip by substrate; To reduce the height that chip and packing colloid cause; And the height space of saving is used to be provided with fin or heat radiation plated film, therefore help improving the radiating efficiency and ELECTROMAGNETIC OBSCURANT (EMI shielding) efficient of stacking construction.
For reaching aforementioned purpose of the present invention, the present invention provides a kind of stacking construction of semiconductor package body, it is characterized in that: said stacking construction comprises: one first packaging body, one second packaging body and several switching elements.Said first packaging body has a first circuit board, at least one first chip and at least one first packing colloid.Said first circuit board is provided with at least one depression, several switch-over soldering pads and several outputs; Ccontaining said first chip of said depression, said first packing colloid fills up said depression and coats said first chip; The upper surface that said switch-over soldering pad is formed at said first circuit board is not provided with the position of depression; And said output is located at the lower surface of said first circuit board.The lower surface of said second packaging body is electrically connected to the switch-over soldering pad of the first circuit board of said first packaging body through said switching element.
In one embodiment of this invention, the upper surface of said first circuit board is provided with several routing weld pads around said depression, and said first chip electrically connects said routing weld pad through several wires.
In one embodiment of this invention, the height of the upper surface of said first chip is equal to or less than the height of the upper surface of said first circuit board.
In one embodiment of this invention, the internal face of the depression of said first circuit board is provided with a heat radiation coating.
In one embodiment of this invention, the inner bottom surface of the depression of said first circuit board is provided with several flip-chip weld pads, and said first chip electrically connects said flip-chip weld pad through several projections.
In one embodiment of this invention, the internal face of the depression of said first circuit board forms a scalariform portion, and said scalariform portion is provided with several routing weld pads, and said first chip electrically connects the routing weld pad in the said scalariform portion through several wires.
In one embodiment of this invention, said switching element is the switching metal ball.
In one embodiment of this invention; Said first packaging body comprises a fin in addition; Said fin is embedded in said first packing colloid, said first chip of an end in contact of said fin, and the other end of said fin exposes outside said first packing colloid.
In one embodiment of this invention, said first packaging body comprises a heat radiation plated film in addition, and said heat radiation plated film is coated the surface of said first packing colloid.
In one embodiment of this invention, said second packaging body has a second circuit board, at least one second chip and at least one second packing colloid.
In one embodiment of this invention, said second circuit board has at least one depression, with ccontaining said second chip.
[description of drawings]
Fig. 1 is the sketch map of the composite construction of stacked package body (POP) on the existing packaging body.
Fig. 2 A, 2B, 2C, 2D, 2E and 2F are the manufacturing process sketch mapes of the stacking construction of first embodiment of the invention semiconductor package body.
Fig. 3 A and 3B be the second embodiment of the invention semiconductor package body stacking construction pile up schematic flow sheet.
Fig. 4 is the sketch map of the stacking construction of third embodiment of the invention semiconductor package body.
Fig. 5 is the sketch map of the stacking construction of fourth embodiment of the invention semiconductor package body.
[embodiment]
For making above-mentioned purpose of the present invention, characteristic and advantage more obviously understandable, hereinafter is special lifts preferred embodiment of the present invention, and conjunction with figs., elaborates as follows:
Please with reference to shown in Fig. 2 A, 2B, 2C, 2D, 2E and the 2F; The manufacturing approach flow process of the stacking construction of the semiconductor package body of its announcement first embodiment of the invention; Wherein shown in Fig. 2 A, 2B and 2C; The first step of said manufacturing approach is: a first circuit board 21 is provided, and it is provided with at least one depression 210, several switch-over soldering pads 218.In this step; Shown in Fig. 2 A; At first make up several base board units through process for pressing (laminationprocess); For example make up one first base board unit 211, one second base board unit 212 and one the 3rd base board unit 213, wherein said first base board unit 211 is on the upper and lower surface of an insulating barrier (indicating) patterned circuit layer (indicating) to be set respectively, and said first base board unit 211 offers at least one through hole 214; Said second base board unit 212 is uncured preimpregnation material films, and said the 3rd base board unit 213 is on the upper and lower surface of an insulating barrier (indicating) patterned circuit layer (indicating) to be set respectively.The quantity of aforesaid substrate unit is to adjust according to the circuit layout demand of actual product.Then, shown in Fig. 2 B, after accomplishing pressing, further said second base board unit, 212 parts exposed in the said through hole 214 are removed in cutting, thereby become at least one depression 210, the patterned circuit layer of said depression 210 exposed said the 3rd base board units 213.In the present invention, preferred further utilize plating mode to form a heat radiation coating 215 at all internal faces (comprising inner bottom surface) of the depression 210 of said first circuit board 21, its material is preferably copper, silver, gold, nickel, palladium or its composition.Then, shown in Fig. 2 C, after forming said depression 210 and heat radiation coating 215, run through said first circuit board 21, to form several plated-through-holes (plating through hole) 216; And form a solder mask (soldermask) 217 respectively, and the said solder mask 216 of patterning at the upper surface of said first base board unit 211 and the lower surface of said the 3rd base board unit 213.At this moment; The locational solder mask 217 that the upper surface of said first base board unit 211 is not provided with depression 210 exposes several switch-over soldering pads 218 and several routing weld pads 218 ', and wherein said routing weld pad 218 ' is formed on around the depression 210 of upper surface of said first circuit board 21.Moreover 217 of the solder masks of the lower surface of said the 3rd base board unit 213 expose several weld pads (not indicating).
Please with reference to shown in Fig. 2 D; Second step of the manufacturing approach of the stacking construction of the semiconductor package body of its announcement first embodiment of the invention is: at least one first chip 22 is arranged at least one depression 210 of said first circuit board 21; And utilize at least one first packing colloid 23 to fill up said depression 210 and coat said first chip 22, to be assembled into one first packaging body 200.In this step, the quantity of said first chip 22 is corresponding to said depression 210, and each said depression 210 can select to hold single, two or more first chip 22.In the present embodiment, the lower surface of said first chip 22 utilizes an adhesion layer 24 to cohere on the heat radiation coating 215 of the inner bottom surface that is fixed in said depression 210 usually.Said first chip 22 is to be selected from routing (wire bonding) cake core; The upper surface of said first chip 22 is active surface; Said upper surface has the routing weld pad 218 ' that several weld pads (not indicating) can be electrically connected to the upper surface of said first circuit board 21 through several wires 221; The height of the upper surface of wherein said first chip 22 is preferably the height of the upper surface that is equal to or less than said first circuit board 21; So that reduce the length and the routing bending angle thereof of said lead 221; In addition, the height of the upper surface of said first chip 22 also can be slightly larger than the height of the upper surface of said first circuit board 21, to adapt to the bigger chip of thickness or conveniently to carry out routing technology.After accomplishing routing, utilize at least one first packing colloid 23 to fill up said depression 210 and coat said first chip 22, so promptly can be assembled into one first packaging body 200.After accomplishing said procedure, several weld pads that said the 3rd base board unit 213 lower surfaces are exposed (not indicating) then combine several outputs 219.In the present embodiment; Said output 219 is selected from tin ball (solder ball), with the framework of formation plastic ball grid array packaging structure (PBGA), yet in other embodiments; Said output 219 also possibly be selected from contact (land) or stitch (pin); With constitute the land grid array package structure (land grid array, LGA) or stitch grid array encapsulation structure (pin grid array, framework PGA).
Please with reference to shown in Fig. 2 E; The third step of the manufacturing approach of the stacking construction of the semiconductor package body of its announcement first embodiment of the invention is: one second packaging body 300 is provided, and its lower surface is electrically connected to the switch-over soldering pad 218 of the first circuit board 21 of said first packaging body 200 through several switching elements 400.In this step; The switch-over soldering pad 218 of the first circuit board 21 of said first packaging body 200 can be in order to electrically connect the packaging body of arbitrary pattern; For example in the present embodiment; Said second packaging body 300 has a second circuit board 31, at least one second chip 32 and at least one second packing colloid 33; Said second chip 32 utilizes lead (not indicating) to be electrically connected to the upper surface of said second circuit board 31; The lower surface of the second circuit board 31 of said second packaging body 300 then is electrically connected to the switch-over soldering pad 218 of the first circuit board 21 of said first packaging body 200 through said switching element 400, said switching element 400 is preferably the switching metal ball, for example tin ball (solder ball), tin projection (solder bump) or golden projection (goldbump) etc.Because first chip 22 of said first packaging body 200 is embedded in the depression 210 of said first circuit board 21; Therefore can reduce the projecting height that said first chip 22 and first packing colloid 23 cause; And then make said first packaging body 200 and second packaging body 300 when piling up assembling; Can directly utilize undersized switching element 400 (like the switching metal ball) to reach the switching purpose, therefore help reducing the integral stacked height, reduce and pile up assembly cost, simplify and pile up the yields that assembling is piled up in assembling flow path and raising.Moreover the internal face of said depression 210 is provided with radiating efficiency and ELECTROMAGNETIC OBSCURANT (EMI shielding) efficient that 215 of said heat radiation coating help improving stacking construction.
Please with reference to shown in Fig. 2 F, the 4th step of the manufacturing approach of the stacking construction of the semiconductor package body of its announcement first embodiment of the invention is: the stacking construction that cuts said first and second packaging body 200,300.In the present invention; Each said first substrate, 21 actual several said first packaging body 200 that comprise; Each said second substrate, 31 actual several said second packaging body 300 that comprise of while; Therefore after assembling was piled up in completion, the stacking construction of said first and second packaging body 200,300 of essential further cutting was to separate into separately the independently stacking construction of semiconductor package body.Said method helps batch stacking construction of volume production semiconductor package body.In other embodiments, the present invention also possibly cut said first substrate 21 and second substrate 31 earlier, then just piles up said first and second packaging body 200,300 of assembling.
Please with reference to shown in Fig. 3 A and the 3B; The stacking construction of the semiconductor package body of second embodiment of the invention and manufacturing approach thereof are similar in appearance to first embodiment of the invention; But the difference characteristic of second embodiment is: said second embodiment be with two or more than the first roughly the same packaging body 200 pile up each other; For example 4 first packaging bodies 200 are piled up each other; And after assembling is piled up in completion, further carry out cutting action, to separate into separately the independently stacking construction of semiconductor package body.Each said first packaging body 200 can select to comprise the first identical or different chip 22.Because first chip 22 of said first packaging body 200 is embedded in the depression 210 of said first circuit board 21; Therefore can reduce the projecting height that said first chip 22 and first packing colloid 23 cause; And then make when piling up two or above said first packaging body 200; Can directly utilize undersized switching element (like the output 219 of said first substrate 22 itself) to reach the switching purpose, therefore help reducing the integral stacked height, reduce and pile up assembly cost, simplify and pile up the yields that assembling is piled up in assembling flow path and raising.
Please with reference to shown in Figure 4; The stacking construction of the semiconductor package body of third embodiment of the invention and manufacturing approach thereof are similar in appearance to first and second embodiment of the present invention; But the difference characteristic of the 3rd embodiment is: when said the 3rd embodiment piles up several packaging bodies (for example 2 first packaging bodies 200 and 1 second packaging body 300) at the framework that utilizes said first packaging body 200; The inner bottom surface of the depression 210 of said first circuit board 21 can select to be provided with several flip-chip weld pads 218 "; said first chip 22 is selected from flip-chip (flip chip) simultaneously; wherein said first chip 22 electrically connects said flip-chip weld pad 218 through several projections 222 ", said projection 22 can be tin projection or golden projection.Perhaps; The internal face of the depression 210 of said first circuit board 21 can be processed to form a 210a of scalariform portion in advance; And said routing weld pad 218 ' is arranged on the said scalariform 210a of portion, make said first chip 22 be electrically connected to the routing weld pad 218 ' on the said scalariform 210a of portion through said lead 221.The design of above-mentioned two kinds of depressions 210 all can further reduce the projecting height that said first chip 22 and first packing colloid 23 cause, and then helps reducing the integral stacked height.
Please with reference to shown in Figure 5; The stacking construction of the semiconductor package body of fourth embodiment of the invention and manufacturing approach thereof are similar in appearance to the present invention first, second and third embodiment; But the difference characteristic of the 4th embodiment is: when said the 4th embodiment piled up several packaging bodies (for example 2 first packaging bodies 200 and 1 second packaging body 300) at the framework that utilizes said first packaging body 200, said first packaging body 200 can select to comprise a fin 25 in addition.The material of said fin 25 is selected from copper, silver, gold, nickel or other equivalent high-termal conductivity materials; Said fin 25 is embedded in said first packing colloid 23; Said first chip 22 of one end in contact of said fin 25, and the other end of said fin 25 exposes outside said first packing colloid 23.Perhaps; Said first packaging body 200 can select to comprise a heat radiation plated film 26 in addition; Said heat radiation plated film 26 is to utilize modes such as plating or vapor deposition to coat the surface of said first packing colloid 23, and the material of said heat radiation plated film 26 also is selected from copper, silver, gold, nickel or other equivalent high-termal conductivity materials.The design of above-mentioned fin 25 or heat radiation plated film 26 all can further reduce the projecting height that said first chip 22 and first packing colloid 23 cause; And then help improving the radiating efficiency and ELECTROMAGNETIC OBSCURANT (EMI shielding) efficient of stacking construction; The chip that can keep each packaging body operates under normal temperature, and can avoid between the chip of each packaging body because of generating electromagnetic waves to the problem of external radiation phase mutual interference.
As stated; Must utilize said switching circuit board 13 to transfer compared to the composite construction that has stacked package body (POP) on the packaging body now and combine said first and second packaging body 11,12; And cause to reduce the shortcomings such as integral stacked height of piling up after the assembling; The present invention of Fig. 2 A to 5 is embedded in the depression 210 of said first circuit board 21 first chip 22 of said first packaging body 200; Therefore can reduce the projecting height that said first chip 22 and first packing colloid 23 cause; And then make said first packaging body 200 and second packaging body 300 when piling up assembling, and can directly utilize undersized switching element 400 (like the switching metal ball) to reach the switching purpose, therefore help reducing the integral stacked height, reduce and pile up assembly cost, simplify and pile up the yields that assembling is piled up in assembling flow path and raising.Moreover the internal face of said depression 210 is provided with radiating efficiency and ELECTROMAGNETIC OBSCURANT (EMI shielding) efficient that 215 of said heat radiation coating help improving stacking construction.In addition, also can the height space of saving be used to be provided with said fin 25 or heat radiation plated film 26, it also helps improving the radiating efficiency and ELECTROMAGNETIC OBSCURANT (EMIshielding) efficient of stacking construction.
The present invention is described by above-mentioned related embodiment, yet the foregoing description is merely the example of embodiment of the present invention.Must be pointed out that disclosed embodiment does not limit scope of the present invention.On the contrary, being contained in the spirit of claims and the modification and impartial setting of scope includes in scope of the present invention.
Claims (7)
1. the stacking construction of a semiconductor package body, it is characterized in that: said stacking construction comprises:
One first packaging body has a first circuit board, at least one first chip and at least one first packing colloid; Said first circuit board is provided with at least one depression, several switch-over soldering pads and several outputs; Ccontaining said first chip of said depression, said first packing colloid fills up said depression and coats said first chip; The upper surface that said switch-over soldering pad is formed at said first circuit board is not provided with the position of depression; And said output is located at the lower surface of said first circuit board;
Several switching elements; And
One second packaging body, the lower surface of said second packaging body are electrically connected to the switch-over soldering pad of the first circuit board of said first packaging body through said switching element;
The inner bottom surface of the depression of wherein said first circuit board is provided with several flip-chip weld pads, and said first chip electrically connects said flip-chip weld pad through several projections; Or the internal face of the depression of said first circuit board forms a scalariform portion, and said scalariform portion is provided with several routing weld pads, and said first chip electrically connects the routing weld pad in the said scalariform portion through several wires.
2. the stacking construction of semiconductor package body as claimed in claim 1, it is characterized in that: the height of the upper surface of said first chip is equal to or less than the height of the upper surface of said first circuit board.
3. the stacking construction of semiconductor package body as claimed in claim 1 is characterized in that: the internal face of the depression of said first circuit board is provided with a heat radiation coating.
4. the stacking construction of semiconductor package body as claimed in claim 1 is characterized in that: said switching element is the switching metal ball.
5. the stacking construction of semiconductor package body as claimed in claim 1; It is characterized in that: said first packaging body comprises a fin in addition; Said fin is embedded in said first packing colloid; Said first chip of one end in contact of said fin, and the other end of said fin exposes outside said first packing colloid.
6. the stacking construction of semiconductor package body as claimed in claim 1 is characterized in that: said first packaging body comprises a heat radiation plated film in addition, and said heat radiation plated film is coated the surface of said first packing colloid.
7. the stacking construction of semiconductor package body as claimed in claim 1; It is characterized in that: said second packaging body has a second circuit board, at least one second chip and at least one second packing colloid; Said second circuit board has at least one depression, with ccontaining said second chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910051149 CN101887885B (en) | 2009-05-12 | 2009-05-12 | Stacking structure of semiconductor packages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910051149 CN101887885B (en) | 2009-05-12 | 2009-05-12 | Stacking structure of semiconductor packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101887885A CN101887885A (en) | 2010-11-17 |
| CN101887885B true CN101887885B (en) | 2012-05-09 |
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| CN102280440A (en) * | 2011-08-24 | 2011-12-14 | 北京大学 | Laminated packaging structure and manufacturing method thereof |
| CN102881667A (en) * | 2012-10-08 | 2013-01-16 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure |
| US9365536B2 (en) | 2012-11-22 | 2016-06-14 | Kureha Corporation | Method for producing glycolide, which is provided with rectification step by means of gas-liquid countercurrent contact, and method for purifying crude glycolide |
| TWI555167B (en) * | 2014-01-29 | 2016-10-21 | 矽品精密工業股份有限公司 | Semiconductor package and manufacturing method thereof |
| CN104952857B (en) * | 2015-06-30 | 2017-12-26 | 通富微电子股份有限公司 | A kind of DNAcarrier free semiconductor laminated encapsulating structure |
| CN107742625B (en) * | 2017-09-22 | 2020-03-20 | 江苏长电科技股份有限公司 | Component vertical mounting packaging structure and process method thereof |
| CN110767614A (en) * | 2019-10-10 | 2020-02-07 | 华为技术有限公司 | Packaging structure and electronic device |
| WO2021097725A1 (en) * | 2019-11-20 | 2021-05-27 | 深圳市大疆创新科技有限公司 | Encapsulation structure, encapsulation assembly and electronic product |
| CN112201647A (en) * | 2020-09-09 | 2021-01-08 | 苏州通富超威半导体有限公司 | High-density interconnection chip structure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1391273A (en) * | 2001-06-13 | 2003-01-15 | 矽品精密工业股份有限公司 | Semiconductor package with heat radiator |
| CN101118890A (en) * | 2006-08-03 | 2008-02-06 | 国际商业机器公司 | Si-based packaging with integrated passive components |
| CN101236958A (en) * | 2008-03-05 | 2008-08-06 | 日月光半导体制造股份有限公司 | Semiconductor package |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1391273A (en) * | 2001-06-13 | 2003-01-15 | 矽品精密工业股份有限公司 | Semiconductor package with heat radiator |
| CN101118890A (en) * | 2006-08-03 | 2008-02-06 | 国际商业机器公司 | Si-based packaging with integrated passive components |
| CN101236958A (en) * | 2008-03-05 | 2008-08-06 | 日月光半导体制造股份有限公司 | Semiconductor package |
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