CN215298201U

CN215298201U - Multi-path high-speed signal synchronous acquisition system

Info

Publication number: CN215298201U
Application number: CN202121290017.7U
Authority: CN
Inventors: 张成飞
Original assignee: Beijing Runke General Technology Co Ltd
Current assignee: Beijing Runke General Technology Co Ltd
Priority date: 2021-06-09
Filing date: 2021-06-09
Publication date: 2021-12-24
Anticipated expiration: 2031-06-09

Abstract

The utility model discloses a multichannel high speed signal synchronous acquisition system, including clock synchronization module and at least one data acquisition module, the clock synchronization module include first FPGA, first clock management chip, first ADC chip and with the second clock management chip of quantity such as data acquisition module, the data acquisition module includes second FPGA and at least one second ADC chip, the utility model discloses well second FPGA all is connected through high-speed serial interface with first FPGA and every ADC chip, and high-speed serial interface transmission sampling data can improve the sampling data volume of transmission at every turn, promotes sampling data transmission rate, reduces data interface quantity, reduces the PCB wiring degree of difficulty. The first clock management chip sends the ADC device clock and the ADC device reference clock to the second clock management chips, so that each second FPGA can synchronously receive high-speed signals collected by the second ADC chips connected with each other.

Description

Multi-path high-speed signal synchronous acquisition system

Technical Field

The utility model relates to a signal acquisition technical field, more specifically the theory relates to a multichannel high-speed signal synchronous acquisition system.

Background

At present, with the development and application of FPGA (Field Programmable gate array) and DSP (Digital Signal processing) technologies, Signal data acquisition and processing technologies are rapidly developed. When multiple high-speed signals (e.g., multiple radar signals) are collected, synchronous collection of the multiple high-speed signals is generally required to ensure that phases of the multiple high-speed signals are consistent.

In the prior art, when multi-path high-speed signals are synchronously acquired, the multi-path high-speed signals are generally realized in a Low-Voltage Differential Signaling (LVDS) form. However, the conventional LVDS has a slow data transmission rate, and when a high acquisition speed is applied to data generated by an Analog-to-digital converter (ADC), the data amount generated by the ADC is large, so that a large number of LVDS data interfaces are required to meet the requirement for transmitting data by using the conventional LVDS. More LVDS data interfaces cause difficult wiring of a Printed Circuit Board (PCB), which makes synchronization of multiple high-speed signals more difficult to control.

Therefore, how to provide a multi-path high-speed signal synchronous acquisition system becomes a technical problem which needs to be solved urgently by those skilled in the art.

SUMMERY OF THE UTILITY MODEL

In view of this, the utility model discloses a multichannel high speed signal synchronous acquisition system to realize improving the sampling data volume of transmission at every turn, promote sampling data transmission rate, reduce data interface quantity, reduced the PCB wiring degree of difficulty, and can realize multichannel high speed signal's synchronous acquisition.

A multi-path high-speed signal synchronous acquisition system comprises: the system comprises a clock synchronization module and at least one data acquisition module;

the clock synchronization module includes: the first FPGA is respectively connected with the first clock management chip and the second clock management chip, the first clock management chip is connected with the second clock management chip, the first clock management chip can simultaneously send an ADC (analog to digital converter) equipment clock and an ADC equipment reference clock to each second clock management chip, and the first FPGA is connected with the first ADC chip through a high-speed serial interface and can receive high-speed serial data sent by the first ADC chip;

the data acquisition module comprises: the second FPGA is respectively connected with the first FPGA and each second ADC chip through a high-speed serial interface, the second clock management chip is respectively connected with the second FPGA and each second ADC chip, and the first clock management chip is respectively connected with each second FPGA in the data acquisition module.

Optionally, the first FPGA and the second FPGA both have externally-extended high-speed serial data transmission interfaces.

Optionally, each second ADC chip has a high-speed serial data transmitting interface, the second FPGA has a high-speed serial data receiving interface, and the high-speed serial data transmitted by the second ADC chip is sequentially transmitted to the second FPGA through the high-speed serial data transmitting interface and the high-speed serial data receiving interface.

Optionally, the second FPGA performs configuration initialization on each of the second ADC chips connected to the second FPGA through a serial peripheral interface.

Optionally, the method further includes: a BUFFER;

the BUFFER is respectively connected with the first clock management chip, the first FPGA and each second FPGA, and is used for distributing the serial transceiver reference clock generated by the first clock management chip to the first FPGA and each second FPGA.

Optionally, a preset number of low-voltage differential signal interfaces are reserved between any two FPGAs in the first FPGA and each second FPGA, so that the first FPGA can perform logic monitoring and state monitoring on each second FPGA and can be used as a backup for each second FPGA.

According to the above technical scheme, the utility model discloses a multichannel high speed signal synchronous acquisition system, including clock synchronization module and at least one data acquisition module, clock synchronization module includes first FPGA, first clock management chip, first ADC chip and with the second clock management chip of data acquisition module etc. quantity, data acquisition module includes second FPGA and at least one second ADC chip, the utility model discloses well second FPGA all is connected through high-speed serial interface with first FPGA and every ADC chip, and through high-speed serial interface transmission sampling data for adopting LVDS in the traditional scheme, can improve the sampling data volume of transmission at every turn greatly to can promote sampling data transmission rate, thereby reduce data interface quantity, reduce the PCB wiring degree of difficulty. And moreover, the first clock management chip sends the ADC device clock and the ADC device reference clock to each second clock management chip, so that each second FPGA can synchronously receive the high-speed signals acquired by each second ADC chip connected with the second FPGA, and multi-path high-speed signal synchronous acquisition is realized.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the disclosed drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a multi-path high-speed signal synchronous acquisition system disclosed in an embodiment of the present invention;

fig. 2 is a schematic structural diagram of another multi-path high-speed signal synchronous acquisition system disclosed in the embodiment of the present invention;

fig. 3 is a clock topology diagram of a multi-path high-speed signal synchronous acquisition system disclosed in the embodiment of the present invention;

fig. 4 is a clock topology diagram of another multi-path high-speed signal synchronous acquisition system disclosed in the embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

The embodiment of the utility model discloses multichannel high speed signal synchronous acquisition system, including clock synchronization module and at least one data acquisition module, clock synchronization module includes first FPGA, first clock management chip, first ADC chip and with the second clock management chip of quantity such as data acquisition module, data acquisition module includes second FPGA and at least one second ADC chip, the utility model discloses well second FPGA all is through high-speed serial interface connection with first FPGA and every ADC chip, and through high-speed serial interface transmission sampling data adopt LVDS in for traditional scheme, can improve the sampling data volume of transmission at every turn greatly to can promote sampling data transmission rate, thereby reduce data interface quantity, reduce the PCB wiring degree of difficulty. And moreover, the first clock management chip sends the ADC device clock and the ADC device reference clock to each second clock management chip, so that each second FPGA can synchronously receive the high-speed signals acquired by each second ADC chip connected with the second FPGA, and multi-path high-speed signal synchronous acquisition is realized.

Referring to fig. 1, the embodiment of the present invention discloses a structural schematic diagram of a multi-path high-speed signal synchronous acquisition system, the system includes: a clock synchronization module 11 and at least one data acquisition module 12.

Wherein:

the clock synchronization module 11 includes: the device comprises a first FPGA (namely, the FPGA1 in fig. 1), a first clock management chip (namely, the CLK1 in fig. 1), a first ADC chip (namely, the ADC11 in fig. 1) and a second clock management chip (namely, the CLK2 in fig. 1) which is equal in number to the data acquisition module 12, wherein the FPGA1 is respectively connected with the CLK1 and the CLK2, the CLK1 is connected with the CLK2, the CLK1 can send an ADC device clock and an ADC device reference clock to the CLK2, and the FPGA1 is connected with the ADC11 through a high-speed serial interface and can receive high-speed serial data sent by the ADC 11.

In this embodiment, CLK1 may send a clock signal CLK to CLK 2.

It should be noted that, only one data acquisition module 12 and one second clock management chip (i.e. CLK2 in fig. 1) are shown in fig. 1, in practical applications, the number of the data acquisition modules 12 may be multiple, and correspondingly, the number of the second clock management chips may also be multiple, and equal to the number of the data acquisition modules 12, at this time, the first clock management chip can simultaneously send the ADC device clock and the ADC device reference clock to each of the second clock management chips.

Specifically, referring to fig. 2, the embodiment of the present invention discloses another structure diagram of a multi-path high-speed signal synchronous acquisition system, which includes: the system comprises a clock synchronization module 11, a data acquisition module 12 and a data acquisition module 13;

the clock synchronization module 11 includes: the FPGA1, the CLK1, the CLK2, the CLK3 and the ADC11, the FPGA1 is respectively connected with the CLK1, the CLK2 and the CLK3, the CLK1 is respectively connected with the CLK2 and the CLK3, the CLK1 can simultaneously send an ADC device clock and an ADC device reference clock to the CLK2 and the CLK3, and the FPGA1 and the ADC11 are connected through a high-speed serial interface and can receive high-speed serial data sent by the ADC 11.

It should be noted that the first FPGA is connected to each second clock management chip, and each second clock management chip is connected to the first clock management chip. The second clock management chip in the embodiment shown in fig. 2 includes: CLK2 and CLK3, CLK1 may send clock signals CLK to CLK2 and CLK3 simultaneously.

It should be noted that the english words corresponding to the ADC are all called: analog-to-digitalcoverter, chinese interpretation: an analog-to-digital converter, ADC, generally refers to an electronic component that converts an analog signal into a digital signal. In this embodiment, the ADC11 has a high-speed serial data transmission interface, the FPGA1 has a high-speed serial data reception interface, and the high-speed serial data transmitted by the ADC11 is sequentially transmitted to the FPGA1 through the high-speed serial data transmission interface and the high-speed serial data reception interface.

The data acquisition module 12 includes: a second FPGA (i.e., FPGA2 in fig. 1) and at least one second ADC chip, the FPGA2 being connected to the FPGA1 and each second ADC chip, respectively, by a high-speed serial interface, and the CLK2 being connected to the second FPGA and each second ADC chip, respectively (not shown in fig. 1).

The CLK1 is connected with the second FPGA in each data acquisition module respectively.

In this embodiment, each of the second ADC chips (see ADC1, ADC2, ADC3, ADC4, and ADC5 in fig. 1) has a high-speed serial data transmitting interface, the second FPGA has a high-speed serial data receiving interface, and the high-speed serial data transmitted by the second ADC chip is sequentially transmitted to the second FPGA through the high-speed serial data transmitting interface and the high-speed serial data receiving interface.

The FPGA1 is configured to configure the CLK1 after the system is powered on, enable the CLK1 to lock the input clock signal source, configure each second clock management chip after detecting the lock signal of the CLK1, enable each second clock management chip to generate the clock signal required by the corresponding data acquisition module, send a configuration completion signal to the second FPGA in each data acquisition module after configuration is completed, send the ADC device clock and the ADC device reference clock to each second clock management chip through the CLK1, enable each second FPGA to perform configuration initialization on each second ADC chip connected to the second FPGA, and enable each second FPGA to synchronously receive the high-speed signal acquired by each second ADC chip connected to the second FPGA through the high-speed serial interface after initialization is completed.

In practical applications, in order to ensure the synchronization of signal acquisition, it is necessary to ensure the correctness of configuration parameters and the locking of CLK 1.

When each second FPGA configures and initializes each second ADC chip connected thereto, the second FPGA may configure and initialize each corresponding second ADC chip through a Serial Peripheral Interface (SPI). In practical application, the SPI interface may be a three-wire system SPI interface.

As shown in fig. 1, when the number of the data acquisition modules and the number of the second clock management chips are both one, in combination with the clock topology of the multi-path high-speed signal synchronous acquisition system shown in fig. 3, after the CLK1 is locked, the FPGA1 configures the CLK2, so that the CLK2 can generate the clock signals required by the data acquisition module 12, that is, the CLK2 can generate the clock signals required by the FPGA2, the ADC1, the ADC2, the ADC3, the ADC4, and the ADC5, and after the configuration is completed, a configuration completion instruction is sent to the FPGA2, and at the same time, the ADC device clock and the ADC device reference clock are sent to the CLK2 through the CLK1, so that the FPGA2 initializes the configuration of the ADC1, the ADC2, the ADC3, the ADC4, and the ADC5, so that the FPGA2 synchronously receives the high-speed signals acquired by the ADC1, the ADC2, the ADC3, the ADC4, and the ADC 5.

Where clk & sysref in fig. 3 denotes an ADC device clock and an ADC device reference clock.

The multi-path high-speed signal synchronous acquisition system can further comprise: the BUFFER is a chip for generating a plurality of clock signals from one clock signal, in this embodiment, the BUFFER is respectively connected to the CLK1, the first FPGA, and each second FPGA, and the BUFFER is configured to distribute a serial transceiver reference clock generated by the CLK1 to the first FPGA and each second FPGA.

For example, in fig. 3, CLK1 is connected to FPGA1 and FPGA2 via BUFFERs (BUFFERs) for distributing serial transceiver reference clocks GT _ refclk generated by CLK1 to FPGA1 and FPGA2, respectively.

As shown in fig. 2, when the number of the data acquisition modules and the number of the second clock management chips are both multiple, such as two shown in fig. 2, in combination with the clock topology of another multi-channel high-speed signal synchronous acquisition system shown in fig. 4, after CLK1 is locked, FPGA1 configures CLK1 and CLK1 at the same time, so that CLK1 can generate the clock signals required by data acquisition module 12, that is, CLK1 can generate the clock signals required by FPGA1 and ADC1, ADC1 and ADC1, and CLK1 can generate the clock signals required by data acquisition module 13, that is, CLK1 can generate the clock signals required by FPGA1 and ADC1, ADC1 and ADC1, and after configuration is completed, configuration completion instructions are sent to FPGA1 and FPGA1, and the clock and reference clock of the FPGA1 and ADC1 are sent to the FPGA1, the ADC1 and the ADC1, the ADC1 and the ADC1, the reference clock 1, the FPGA1, the ADC1 and the ADC1, the reference clock are configured synchronously The high-speed signals collected by the ADC2, the ADC3, the ADC4 and the ADC5, and the configuration initialization of the ADC6, the ADC7, the ADC8, the ADC9 and the ADC10 by the FPGA3, so that the FPGA3 can synchronously receive the high-speed signals collected by the ADC6, the ADC7, the ADC8, the ADC9 and the ADC 10.

Referring to fig. 4, the multi-path high-speed signal synchronous acquisition system may be further divided into a clock generation module and a clock receiving module, wherein the clock generation module includes: clock signal source, CLK1, CLK2, CLK3 and BUFFER, the clock receiving module mainly includes: ADC 1-ADC 11 and FPGA 1-FPGA 3, in practical application, the clock generation module generates each clock to realize normal work of the whole multi-path high-speed signal synchronous acquisition system.

It should be noted that the second clock management chip is enabled to generate the clock signal required by the corresponding data acquisition module 12, that is, the second clock management chip is enabled to generate the clock signal required by the second FPGA and all the second ADC chips in the corresponding data acquisition module 12.

In conclusion, the utility model discloses a multichannel high speed signal synchronous acquisition system, including clock synchronization module 11 and at least one data acquisition module 12, clock synchronization module 11 includes first FPGA, first clock management chip, first ADC chip and with the second clock management chip of data acquisition module 12 etc. quantity, data acquisition module 12 includes second FPGA and at least one second ADC chip, the utility model discloses well second FPGA all is through high-speed serial interface connection with first FPGA and every ADC chip, through high-speed serial interface transmission sampling data for adopting LVDS in the traditional scheme, can improve the sampling data volume of transmission at every turn greatly to can promote sampling data transmission rate, thereby reduce data interface quantity, reduce the PCB wiring degree of difficulty. And the first clock management chip sends an ADC device clock and an ADC device reference clock to each second clock management chip, so that each second FPGA carries out configuration initialization on each second ADC chip connected with the second FPGA, each second FPGA can synchronously receive high-speed signals collected by each second ADC chip connected with the second FPGA, and multi-path high-speed signal synchronous collection is realized.

Preferably, in the above embodiment, the first FPGA (e.g., FPGA1 in fig. 1 and 2) and the second FPGA (e.g., FPGA2 and FPGA3 in fig. 2) may adopt a large-scale FPGA device of Xilinx corporation, which determines that RAM (random access Memory), multiplier, logic, and Ser-Des resources need to be scaled according to system technical indexes. The multiplier resource is mainly used for signal processing algorithms of radio frequency storage, such as digital down-conversion, convolution and the like, the RAM is used for buffering and logic clock domain conversion of signal processing, and the Ser-Des is used for high-speed serial data transmission.

Wherein, Ser-Des is a combination of SERializer and DESerializer, and is also called as a serial transceiver.

In the embodiment shown in fig. 2, the FPGA1, the FPGA2, and the FPGA3 are connected by a high-speed serial interface, so as to implement data transmission with a large bandwidth and data interaction therebetween.

In order to further optimize the above embodiment, the first FPGA has an externally extended high-speed serial data transmission interface, and the first FPGA performs high-speed signal transmission between the externally extended high-speed serial data transmission interface and an external device of the multi-channel high-speed signal synchronous acquisition system.

Similarly, each second FPGA also has an externally-expanded high-speed serial data transmitting interface, and the second FPGA transmits high-speed signals to external equipment of the multi-channel high-speed signal synchronous acquisition system through the externally-expanded high-speed serial data transmitting interface.

The first FPGA and the second FPGA realize large broadband data interaction between the boards through the high-speed serial data transmitting interface which is externally expanded.

In this embodiment, the sampling rate and the data bit width of each second ADC chip in each data acquisition module 12 are determined by the technical index of the multi-path high-speed signal synchronous acquisition system.

In fig. 1, both the first clock management chip CLK1 and the second clock management chip CLK2 may provide a clock reference for the multi-chip ADC unit. CLK1 is used to provide a clock reference for FPGA1, the clock signal source being provided by an external clock signal source or an onboard clock; CLK2 is used to provide a clock reference for FPGA2, which is provided by an external clock signal source or an onboard clock. In fig. 2, CLK3 is used to provide a clock reference for FPGA3, the clock signal source being provided by an external clock signal source or an on-board clock.

In practical application, according to the requirement of the multi-path high-speed signal synchronous acquisition system, a preset number (for example, ten pairs) of Low-Voltage Differential Signaling (LVDS) interfaces are reserved between any two FPGAs in the first FPGA and each second FPGA, so that the first FPGA can perform logic control and state monitoring on each second FPGA and can be used as a backup for each second FPGA.

It is found through tests that in the multi-channel high-speed signal synchronous acquisition system to be protected, the high-speed signals acquired by all ADC chips (including the first ADC chip and the second ADC chip) are delayed and fixed, the synchronism is good, the delay error can be controlled within 20ps, and the 14-bit sampling data of 21 channels of 2.56G can be transmitted simultaneously. Therefore, compared with the conventional scheme, the data transmission speed is increased, the number of data interfaces is reduced, and the wiring complexity of a Printed Circuit Board (PCB) is reduced.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multi-channel high-speed signal synchronous acquisition system is characterized by comprising: the system comprises a clock synchronization module and at least one data acquisition module;

2. The multi-channel high-speed signal synchronous acquisition system according to claim 1, wherein the first FPGA and the second FPGA are both provided with high-speed serial data transmission interfaces extending outwards.

3. The multi-channel high-speed signal synchronous acquisition system according to claim 1, wherein each second ADC chip has a high-speed serial data transmission interface, the second FPGA has a high-speed serial data reception interface, and the high-speed serial data transmitted by the second ADC chip is transmitted to the second FPGA sequentially through the high-speed serial data transmission interface and the high-speed serial data reception interface.

4. The multi-channel high-speed signal synchronous acquisition system according to claim 1, wherein the second FPGA performs configuration initialization on each of the connected second ADC chips through a serial peripheral interface.

5. The multi-channel high-speed signal synchronous acquisition system according to claim 1, further comprising: a BUFFER;

6. The system according to claim 1, wherein a preset number of low voltage differential signal interfaces are reserved between any two of the first FPGA and each of the second FPGAs, so that the first FPGA can perform logic monitoring and status monitoring on each of the second FPGAs and can be used as a backup for each of the second FPGAs.