CN210225390U

CN210225390U - Self-adaptive multi-board-card high-speed DAC (digital-to-analog converter) synchronization system

Info

Publication number: CN210225390U
Application number: CN201921212227.7U
Authority: CN
Inventors: Zhihui Li; 李智慧
Original assignee: Chengdu Mingda Electronic Ltd By Share Ltd
Current assignee: Chengdu Mingda Electronic Ltd By Share Ltd
Priority date: 2019-07-30
Filing date: 2019-07-30
Publication date: 2020-03-31
Anticipated expiration: 2029-07-30

Abstract

The utility model discloses a high-speed DAC synchronous system of many integrated circuit boards of self-adaptation, it includes a plurality of integrated circuit boards that have DAC and system module, still integrated in the integrated circuit board has cophase trigger circuit, and cophase trigger circuit is used for receiving external input's reference clock signal and synchronous trigger signal to export and DAC with the sampling clock of reference clock cophase, synchronous pulse signal and the working clock of homology and export again to system module after converting for DAC. According to the self-adaptive multi-board high-speed DAC synchronous system, the transmission of high-speed analog clock signals among the multiple boards is abandoned through the effective design of the structural arrangement of the system, only a low-speed reference clock and a synchronous trigger signal need to be provided outside the system, and the sampling clock and the synchronous pulse signals which are in phase with the input reference clock are output through the in-phase trigger circuit inside the boards, so that the output synchronization of the analog signals can be ensured, the difficulty of hardware design is greatly simplified, and the synchronous performance of the multi-board DAC in the system is improved.

Description

Self-adaptive multi-board-card high-speed DAC (digital-to-analog converter) synchronization system

Technical Field

The utility model relates to an electron field, concretely relates to high-speed DAC synchronizing system of many integrated circuit boards of self-adaptation.

Background

A DAC is a Digital-to-analog converter (DAC) that is a device that converts a Digital signal into an analog signal (in the form of current, voltage, or charge). In many digital systems (e.g., computers), signals are stored and transmitted digitally, and digital-to-analog converters can convert such signals to analog signals so that they can be recognized by the outside world (human or other non-digital system).

At present, in the DAC synchronization system in the prior art, the implementation manner of synchronization is mainly a scheme for designing multi-board synchronization based on master-slave clock distribution and synchronization pulses, and the design in the prior art is a great challenge for implementing equal-length design and wiring of input high-speed clocks of boards and among multiple boards, so that a multi-board DAC synchronization system with higher performance needs to be designed.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing a high-speed DAC synchronizing system of many integrated circuit boards of self-adaptation to solve the problem mentioned in the above-mentioned background art.

For solving the technical problem, the utility model provides a high-speed DAC synchronous system of many integrated circuit boards of self-adaptation, it includes a plurality of integrated circuit boards that have DAC and system module, still integrated in the integrated circuit board has cophase trigger circuit, and cophase trigger circuit is used for receiving external input's reference clock signal and synchronous trigger signal to export and the sampling clock of reference clock cophase, synchronous pulse signal and the homologous work clock and export again to system module after for DAC converts.

Further, the synchronization trigger signal is a synchronization pulse trigger signal.

Further, the reference clock signal is a low-speed reference clock signal.

Furthermore, the in-phase trigger circuit comprises a phase-locked loop frequency multiplier for receiving a reference clock signal, and the output end of the phase-locked loop frequency multiplier is connected with the input end of the clock distributor; the clock distributor is also used for receiving the synchronous trigger signal, and the clock distributor distributes the received information to the DAC and/or the FPGA.

Furthermore, a delay timer is connected between the clock distributor and the DAC and/or the FPGA.

The utility model has the advantages that: according to the self-adaptive multi-board high-speed DAC synchronous system, the transmission of high-speed analog clock signals among the multiple boards is abandoned through the effective design of the structural arrangement of the system, only a low-speed reference clock and a synchronous trigger signal need to be provided outside the system, and the sampling clock and the synchronous pulse signals which are in phase with the input reference clock are output through the in-phase trigger circuit inside the boards, so that the output synchronization of the analog signals can be ensured, the difficulty of hardware design is greatly simplified, and the synchronous performance of the multi-board DAC in the system is improved.

Drawings

Fig. 1 schematically shows a block diagram of a multi-board DAC synchronization system in the prior art.

Fig. 2 schematically shows a structural block diagram of the adaptive multi-board high-speed DAC synchronization system.

Fig. 3 schematically shows a structural block diagram of the in-phase trigger circuit of the adaptive multi-board high-speed DAC synchronization system.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiment is only one embodiment of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings and specific embodiments.

Here, it should be noted that: for the sake of simplicity, the following omits technical common knowledge known to those skilled in the art.

At present, in a traditional DAC synchronization system, a synchronization implementation manner is mainly a scheme for performing multi-board synchronization based on master-slave clock distribution and synchronization pulses. Referring to fig. 1, fig. 1 schematically shows a DAC synchronization system of a multi-board card in the prior art; as shown in fig. 1, in the system, an external module provides a sampling clock and a synchronization trigger signal, the sampling clock is distributed to the sampling clocks of the DACs for system operation through a clock distribution circuit in each single board, a synchronization clock is generated inside a main DAC, the sampling clocks are distributed to the acquisition modules through the clock distribution circuit to ensure that all the DACs are locked and consistent in phase to ensure synchronization of sampling moments, and the system module sends synchronization data by receiving the synchronization trigger signal to ensure synchronization of analog output.

However, the system design in the prior art has high requirements on device, hardware wiring and system wiring, a high-frequency sampling clock is required for the sampling clock, meanwhile, compensation cannot be performed in later design, the quality and phase relation of the clock are difficult to guarantee, and the more boards to be designed, the worse synchronization performance is.

In order to improve the performance of multi-board DAC synchronization in the system, the design improves and designs the external clock to provide relatively low frequency. The design provides a self-adaptive multi-board high-speed DAC synchronous system; as shown in fig. 2, the self-adaptive multi-board high-speed DAC synchronization system includes a plurality of boards integrated with DACs and system modules, and an in-phase trigger circuit integrated in the boards, the in-phase trigger circuit being configured to receive an externally input reference clock signal and a synchronization trigger signal, and output a sampling clock, a synchronization pulse signal and a homologous working clock that are in phase with the reference clock to the DACs for conversion and then output to the system modules; the synchronous trigger signal is a synchronous pulse trigger signal, and the reference clock signal may be a low-speed reference clock signal.

In the specific implementation, in the design, a low-speed reference clock and a synchronous pulse trigger signal are provided outside a system, the externally introduced low-speed reference clock outputs a sampling clock, a synchronous pulse signal and a homologous working clock which are in the same phase with an input reference clock through an in-phase trigger circuit in a board, and the externally introduced synchronous trigger signal ensures that each board card simultaneously transmits data; the synchronization of the system is ensured because all signals are in phase with the input reference clock.

Compared with the design in the prior art, the design of the method has higher synchronization precision and sampling performance, does not need to be corrected by an algorithm in the later period, and has strong self-adaptability.

For a high-frequency acquisition system, the design difficulty of transmission of a high-speed analog clock signal between board cards needs to be considered, and the quality and phase relation of the high-speed analog clock signal can be changed due to the difference of the design of the board cards, the performance of devices, the length performance of a radio frequency cable and the like, so that the system is fatal to a multi-board card synchronization system, and the development difficulty is extremely high.

The effective design of this application has abandoned the transmission of high-speed analog clock signal between many integrated circuit boards, only need the system outside provide low-speed reference clock and synchronous trigger signal can, the integrated circuit board is inside to be exported through cophase trigger circuit and to be guaranteed with the sampling clock and the synchronous pulse signal of input reference clock cophase and export the synchronization of analog signal, has simplified hardware design's the degree of difficulty greatly.

In a specific implementation, as shown in fig. 3, the in-phase trigger circuit may include a phase-locked loop frequency multiplier for receiving the reference clock signal, an output terminal of the phase-locked loop frequency multiplier being connected to an input terminal of the clock distributor; the clock distributor is also used for receiving the synchronous trigger signal, and the clock distributor distributes the received information to the DAC and/or the FPGA. And in order to further improve the synchronism of the system, a time delay unit is connected between the clock distributor and the DAC and/or the FPGA.

In the following description, references to "one embodiment," "an embodiment," "one example," "an example," etc., indicate that the embodiment or example so described may include a particular feature, structure, characteristic, property, element, or limitation, but every embodiment or example does not necessarily include the particular feature, structure, characteristic, property, element, or limitation. Moreover, repeated use of the phrase "in accordance with an embodiment of the present application" although it may possibly refer to the same embodiment, does not necessarily refer to the same embodiment.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. The utility model provides a high-speed DAC synchronous system of many integrated circuit boards of self-adaptation, includes a plurality of integrated circuit boards that have DAC and system module, its characterized in that: the integrated circuit board is characterized in that an in-phase trigger circuit is integrated in the integrated circuit board and used for receiving an externally input reference clock signal and a synchronous trigger signal, outputting a sampling clock, a synchronous pulse signal and a homologous working clock which are in phase with the reference clock to the DAC, and outputting the converted signals to a system module.

2. The adaptive multi-board high-speed DAC synchronization system of claim 1, wherein: the synchronous trigger signal is a synchronous pulse trigger signal.

3. The adaptive multi-board high-speed DAC synchronization system of claim 1, wherein: the reference clock signal is a low speed reference clock signal.

4. The adaptive multi-board high-speed DAC synchronization system according to any one of claims 1-3, wherein: the in-phase trigger circuit comprises a phase-locked loop frequency multiplier used for receiving the reference clock signal, and the output end of the phase-locked loop frequency multiplier is connected with the input end of the clock distributor; the clock distributor is also used for receiving the synchronous trigger signal, and the clock distributor distributes the received information to the DAC and/or the FPGA.

5. The adaptive multi-board high-speed DAC synchronization system of claim 4, wherein: and a delay timer is connected between the clock distributor and the DAC and/or the FPGA.