CN114815965B - Clock signal generating and synchronizing method and device - Google Patents
Clock signal generating and synchronizing method and device Download PDFInfo
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- CN114815965B CN114815965B CN202210745709.9A CN202210745709A CN114815965B CN 114815965 B CN114815965 B CN 114815965B CN 202210745709 A CN202210745709 A CN 202210745709A CN 114815965 B CN114815965 B CN 114815965B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Abstract
The invention relates to the technical field of signal processing, and provides a method and a device for generating and synchronizing clock signals, wherein the method comprises the following steps: receiving an external clock signal, and performing two-stage distribution on the external clock signal; when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface; performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module; and performing secondary frequency division on the clock signal subjected to the primary frequency division according to a second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division. The clock signals are subjected to multi-stage frequency division processing based on the synchronous trigger signals, so that the generated clock signals have synchronism and adjustable clock frequency, the synchronism of the clock signals is ensured, and the generation efficiency of the clock signals is improved.
Description
Technical Field
The present invention relates to the field of signal processing technologies, and in particular, to a method and an apparatus for generating and synchronizing a clock signal.
Background
With the rapid development of modern technology, system bandwidth and resolution have met with significant challenges, which have prompted the need to connect multiple data converters in an array. In practical applications, the large number of clocks required by the data converter array exceeds the limit provided by a single clock ic (integrated circuit) device, and the clock used by the large number of data converters also puts higher requirements, namely, the requirement of maintaining synchronism is required.
Because the output clock frequency of the clock module has the limitation of the maximum output value, and the working frequency of the Converter ADC (Analog to Digital Converter)/DAC (Digital to Analog Converter) is higher than the maximum output frequency of the clock module, and the clock frequency is not synchronous, the problem of clock signal generation and synchronization needs to be solved at present.
Disclosure of Invention
The invention provides a method and a device for generating and synchronizing clock signals, which are used for solving the problems of generating and synchronizing the clock signals, generating the clock signals by adopting a clock tree architecture and ensuring the synchronism of the clock signals.
The invention provides a method for generating and synchronizing clock signals, which comprises the following steps:
receiving an external clock signal, and performing two-stage distribution on the external clock signal;
when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface;
performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division.
In one embodiment, the distributing the external clock signal in two stages includes:
performing first-level distribution on the external clock signals according to the first clock cache to obtain a first path of external clock signals and a second path of external clock signals;
and carrying out second-level distribution on the first path of external clock signals according to a second clock cache, and sending the second path of external clock signals to next cascade equipment.
In one embodiment, before the generating at least two second synchronous trigger signals according to the first clock module and the preset output mode of the interface, the method includes:
triggering and distributing the first synchronous trigger signal according to the trigger cache to obtain a first path of synchronous trigger signal and a second path of synchronous trigger signal;
and sending the second path of synchronous trigger signal to the next cascade equipment.
In one embodiment, the dividing the two-stage distributed external clock signal for the first time according to the first synchronization trigger signal and the first clock module includes:
and carrying out first frequency division on the external clock signal after the second-stage distribution according to the first path of synchronous trigger signal and the first clock module.
In one embodiment, the frequency dividing the clock signal after the first frequency division according to the second synchronous trigger signal, the second clock module, and the preset clock requirement includes:
determining interface clock requirements, wherein the preset clock requirements comprise the interface clock requirements;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, the second clock module and the interface clock requirement.
In one embodiment, the frequency dividing the clock signal after the first frequency division according to the second synchronous trigger signal, the second clock module, and the preset clock requirement includes:
determining synchronous clock requirements of a data converter, wherein the preset clock requirements comprise the synchronous clock requirements;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, the second clock module and the synchronous clock requirement.
In one embodiment, before the generating at least two second synchronous trigger signals according to the first clock module and the preset output mode of the interface, the method includes:
and configuring a preset output mode of the interface in the first clock module.
The present invention also provides a clock signal generating and synchronizing apparatus, comprising:
the receiving module is used for receiving an external clock signal and performing two-stage distribution on the external clock signal;
the generating module is used for generating at least two second synchronous trigger signals according to the first clock module and a preset output mode of the interface when receiving the first synchronous trigger signal;
the first frequency division module is used for carrying out first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module;
and the second frequency division module is used for carrying out second frequency division on the clock signal subjected to the first frequency division according to the second synchronous trigger signal, the second clock module and the preset clock requirement and outputting the clock signal subjected to the second frequency division.
The present invention also provides an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the clock signal generation and synchronization method as described in any of the above when executing the program.
The invention also provides a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method of clock signal generation and synchronization as described in any of the above.
According to the method and the device for generating and synchronizing the clock signals, the external clock signals are received, and two-stage distribution is carried out on the external clock signals; when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface; performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module; and performing secondary frequency division on the clock signal subjected to the primary frequency division according to a second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division. The clock signals are subjected to multi-stage frequency division processing based on the synchronous trigger signals, so that the generated clock signals have synchronism and adjustable clock frequency, the synchronism of the clock signals is ensured, and the generation efficiency of the clock signals is improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method for generating and synchronizing clock signals according to the present invention;
FIG. 2 is a second schematic flow chart of a clock signal generation and synchronization method provided by the present invention;
FIG. 3 is a third schematic flow chart of a clock signal generation and synchronization method provided by the present invention;
FIG. 4 is a schematic diagram of a clock signal generation and synchronization method provided by the present invention;
FIG. 5 is a schematic diagram of a clock signal generating and synchronizing apparatus provided by the present invention;
fig. 6 is a schematic structural diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The clock signal generation and synchronization method and apparatus of the present invention are described below in conjunction with fig. 1-6.
Specifically, the present invention provides a method for generating and synchronizing a clock signal, and referring to fig. 1, fig. 1 is one of the flow diagrams of the method for generating and synchronizing a clock signal provided by the present invention.
While a logical order is shown in the flow chart, in some cases, the steps shown or described may be performed in a different order than presented herein.
The method for generating and synchronizing the clock signals provided by the embodiment of the invention comprises the following steps:
step S10, receiving an external clock signal, and performing two-stage distribution on the external clock signal;
it should be noted that, because there is a limitation that the output clock frequency of the clock module has a maximum output value, and the operating frequency of the high-speed converter AD/DA (i.e. ADC/DAC) is higher than the maximum output frequency of the clock module, in order to meet the requirement that the high-speed converter AD/DA operates at the maximum operating clock, the embodiment of the present invention uses a clock tree architecture to generate the clock signal and ensure the synchronization of the clock signal, for example, referring to fig. 4, fig. 4 shows a two-stage clock tree with synchronization, where modules may be cascaded, each module may provide a corresponding clock for 7 high-speed converters AD/DA, and meanwhile, to meet the requirement of the high-speed converter, the input clock of each module is at most 8 GHz.
For example, referring to fig. 4, the external clock signal EXT _ CLK _ IN is connected to a clock input terminal of the module 1, the module 1 receives the external clock signal through the clock input terminal, and then the external clock signal is distributed IN two stages through a clock buffer IN the module 1.
Specifically, the two-stage distribution of the external clock signal includes:
step S11, performing first-level distribution on the external clock signal according to the first clock buffer to obtain a first path of external clock signal and a second path of external clock signal;
and step S12, performing second-level distribution on the first path of external clock signal according to a second clock cache, and sending the second path of external clock signal to a next cascade device.
After receiving the external clock signal, the module 1 controls the first clock cache to perform first-level distribution on the external clock signal to obtain a first path of external clock signal and a second path of external clock signal, then sends the first path of external clock signal to the second clock cache, sends the second path of external clock signal to the next cascade equipment, and simultaneously controls the second clock cache to perform second-level distribution on the first path of external clock signal. For example, referring to fig. 4, after receiving an external clock signal EXT _ CLK _ IN, a clock input terminal of the module 1 distributes the first level of the external clock signal through a clock BUFFER1 (i.e., a first clock BUFFER) to obtain two external clock signals, where the first external clock signal is received through a clock BUFFER2 (i.e., a second clock BUFFER) to the clock input terminal CLK _ IN of the first clock module (i.e., CLK _ a), and the second external clock signal is received through a clock input terminal CLK _ IN of the module 2 (i.e., a next cascade device). After receiving the first external clock signal sent by the clock BUFFER1, the clock BUFFER2 distributes the first external clock signal in the second stage to obtain 8 external clock signals, such as ADDA1_ CLK, ADDA2_ CLK, and ADDA3_ CLK, where 7 external clock signals are distributed to the next stage to be used as the operating clock of the AD/DA chip, and the other external clock signal is provided to the CLK _ a module.
It should be noted that, IN order to implement cascade connection between devices, first-stage distribution needs to be performed on an external clock signal, and one of the paths of clock signals obtained after the first-stage distribution is sent to the module 2, so that cascade connection between the module 1 and the module 2 is implemented, meanwhile, IN order to provide a clock signal for the module (such as the module 1), second-stage distribution needs to be performed on the clock signal, and one of the paths of clock signals obtained after the second-stage distribution is sent to the clock input terminal CLK _ IN of the CLK _ a, so that the clock signal is provided for the module.
Two paths of signals are obtained by performing first-stage distribution on an external clock signal by adopting a first clock cache, and one path of signal is sent to the next cascade equipment, so that cascade connection between the equipment is realized, and the generation efficiency of the clock signal is improved; and further, a second clock cache is adopted to carry out second-level distribution on the external clock signals after the first-level distribution, so that clock signals are provided for the module, and the generation efficiency of the clock signals is improved.
Step S20, when receiving the first synchronous trigger signal, generating at least two second synchronous trigger signals according to the first clock module and the preset output mode of the interface;
when receiving the first synchronous trigger signal, the first synchronous trigger signal also needs to be distributed, specifically, the first synchronous trigger signal is triggered and distributed through the trigger cache to obtain a first path of synchronous trigger signal and a second path of synchronous trigger signal, then the first path of synchronous trigger signal is connected to the input end of the module 1, and the second path of synchronous trigger signal is sent to the next cascade equipment. For example, referring to fig. 4, an external synchronization trigger signal EXT _ SYNC _ IN (i.e., a first synchronization trigger signal) is connected to a trigger input end of the module 1, and when the external synchronization trigger signal is received through the trigger input end, the module 1 controls a trigger BUFFER (i.e., a trigger BUFFER) to trigger and distribute the external synchronization trigger signal, so as to obtain two paths of synchronization trigger signals, where the first path of synchronization trigger signal is connected to the SYNC _ IN of the module 1, and the second path of synchronization trigger signal is connected to the SYNC _ IN of the module 2.
It should be noted that, to implement the cascade connection between the devices, the first synchronous trigger signal needs to be triggered and distributed, and one of the synchronous trigger signals obtained after the trigger distribution is sent to the module 2, so as to implement the cascade connection between the modules 1 and 2, and make the clock signals between the modules 1 and 2 have synchronicity; the other path of synchronous trigger signal obtained after trigger distribution is sent to the input end SYNCIN of the CLK _ A, so that the synchronous trigger signal is provided for the module (such as the module 1), and the synchronism of each frequency division signal is realized based on the synchronous trigger signal.
Before dividing the frequency of the external clock signal, a preset output mode of the interface in the first clock module needs to be configured in advance, for example, referring to fig. 4, the interface of output 1 and output 11 in CLK _ a (i.e., the first clock module) is configured in advance to be a single-pulse mode, and frequency division processing of the clock signal can be realized based on the single-pulse mode of the interface, so that generation efficiency of the clock signal is improved.
After configuring the preset output mode of the interface, at least two second synchronous trigger signals are generated according to the first clock module and the preset output mode of the interface, for example, referring to fig. 4, when a synchronous trigger signal is detected at the input terminal SYNCIN of the first clock module CLK _ a, that is, when a first synchronous trigger signal sent by the clock BUFFER2 to the input terminal SYNCIN is detected, the first clock module CLK _ a is controlled to simultaneously generate two phase-synchronized synchronous trigger signals, namely, a _ SCLKOUT1 and a _ SCLKOUT11, at two output terminals (for example, output 1 and output 11) based on the preconfigured single pulse mode, and then the synchronous trigger signal a _ SCLKOUT1 is sent to the second clock module CLK _ B, and the synchronous trigger signal a _ SCLKOUT11 is sent to the second clock module CLK _ C. It is understood that the synchronization trigger signal includes various synchronization types, such as frequency synchronization, phase synchronization, time synchronization, and frame synchronization, wherein the phase synchronization is also called time synchronization (time delay synchronization), which refers to synchronization of active edges (rising edges or falling edges) of the clock signal.
Step S30, according to the first synchronous trigger signal and the first clock module, the first frequency division is carried out on the external clock signal after two-stage distribution;
when detecting a first synchronous trigger signal at the input SYNCIN of the first clock module CLK _ a, controlling the first clock module to divide the external clock signal after two-stage distribution for the first time according to the first synchronous trigger signal, specifically, controlling the first clock module to divide the external clock signal after second-stage distribution for the first time according to the first synchronous trigger signal, for example, referring to fig. 4, when detecting a first synchronous trigger signal sent by the clock BUFFER2 at the input SYNCIN of the first clock module CLK _ a, controlling the first clock module CLK _ a to divide the external clock signal sent by the clock BUFFER2 according to the first synchronous trigger signal, for example, dividing the external clock signal input by the clock BUFFER2 at the interface output 0 and output 10 to obtain clock signals a _ CLKOUT0 and a _ CLKOUT10, and then sending the clock signal a _ CLKOUT0 to the second clock module CLK _ B, the clock signal a _ CLKOUT10 is sent to the second clock module CLK _ C. The frequency division processing is carried out through the clock signal, and the generation efficiency of the clock signal is improved.
And step S40, performing second frequency division on the clock signal subjected to the first frequency division according to the second synchronous trigger signal, the second clock module and the preset clock requirement, and outputting the clock signal subjected to the second frequency division.
For example, referring to fig. 4, the second clock module includes CLK _ B and CLK _ C, each second clock module has a corresponding preset clock requirement, and when the second clock module receives the second synchronous trigger signal sent by the first clock module, the module 1 controls the second clock module to perform the second frequency division on the clock signal after the first frequency division according to the second synchronous trigger signal and the preset clock requirement, and simultaneously outputs the clock signal after the frequency division.
It should be noted that all the clock signals generated by the second stage CLK _ B and CLK _ C have strict synchronism due to the phase synchronism of the 4 signals generated by CLK _ a, a _ CLKOUT0, a _ SCLKOUT1, a _ CLKOUT10 and a _ SCLKOUT 11. Meanwhile, the circuit can program CLK _ A, CLK _ B, CLK _ C through the FPGA, so that the output clock frequency can be changed at will, and the circuit has good flexibility.
According to the method for generating and synchronizing the clock signals, the external clock signals are received, and two-stage distribution is carried out on the external clock signals; when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface; performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module; and performing secondary frequency division on the clock signal subjected to the primary frequency division according to a second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division. The clock signals are subjected to multi-stage frequency division processing based on the synchronous trigger signals, so that the generated clock signals have synchronism and adjustable clock frequency, the synchronism of the clock signals is ensured, and the generation efficiency of the clock signals is improved.
Further, referring to fig. 2, fig. 2 is a second schematic flow chart of the clock signal generation and synchronization method provided by the present invention, where the second frequency division is performed on the clock signal after the first frequency division according to the second synchronization trigger signal, the second clock module, and the preset clock requirement, and the method includes:
step S41, determining interface clock requirements, wherein the preset clock requirements comprise the interface clock requirements;
and step S42, performing a second frequency division on the clock signal after the first frequency division according to the second synchronous trigger signal, the second clock module, and the interface clock requirement.
Specifically, interface clock requirements are determined, and then the second clock module is controlled to perform second frequency division on the clock signal subjected to the first frequency division according to a second synchronous trigger signal and the interface clock requirements, wherein the preset clock requirements include the interface clock requirements. For example, referring to fig. 4, for CLK _ B, when a synchronization trigger signal (e.g., synchronization trigger signal a _ SCLKOUT 1) is detected at the input terminal SYNCIN, the input signal (e.g., clock signal a _ CLKOUT 0) is divided to generate two clocks, GTX _ REFx and FPGA _ SYSREFx, respectively, required by the FPGA high-speed interface, based on which 7 sets of signals (each set has 2-way, i.e., 14-way signals) can be generated, and these 7 sets of signals are strictly synchronized under the SYNCIN trigger of CLK _ B.
According to the embodiment of the invention, the first clock module is controlled to carry out the second frequency division on the clock signal subjected to the first frequency division according to the second synchronous trigger signal and the interface clock requirement, so that the generation efficiency of the clock signal is improved, and the synchronism of the clock signal is ensured.
Further, referring to fig. 3, fig. 3 is a third schematic flow chart of a clock signal generating and synchronizing method provided by the present invention, where the second frequency dividing of the clock signal after the first frequency dividing according to the second synchronization trigger signal, the second clock module and the preset clock requirement includes:
step S43, determining synchronous clock requirements of the data converter, wherein the preset clock requirements comprise the synchronous clock requirements;
step S44, frequency-dividing the clock signal after the first frequency-dividing according to the second synchronous trigger signal, the second clock module, and the synchronous clock requirement.
Specifically, the synchronous clock requirement of the data converter is determined, and then the second clock module is controlled to perform second frequency division on the clock signal subjected to the first frequency division according to a second synchronous trigger signal and the synchronous clock requirement, wherein the preset clock requirement comprises the synchronous clock requirement. For example, referring to fig. 4, for CLK _ C, when a synchronization trigger signal (e.g., synchronization trigger signal a _ SCLKOUT 11) is detected at the input terminal SYNCIN, the input signal (e.g., clock signal a _ CLKOUT 10) is divided to generate the synchronization clock ADDA _ SYSREFx required by the high-speed converter AD/DA, and at the same time, 7 sets (2 for each set, i.e., 14 for each set) of user-defined clocks are generated for the FPGA processing signals, which 7 sets are strictly synchronized under the SYNCIN trigger of CLK _ C.
According to the embodiment of the invention, the second clock module is controlled to carry out the second frequency division on the clock signal subjected to the first frequency division according to the second synchronous trigger signal and the synchronous clock requirement, so that the generation efficiency of the clock signal is improved, and the synchronism of the clock signal is ensured.
The clock signal generating and synchronizing apparatus provided by the embodiments of the present invention is described below, and the clock signal generating and synchronizing apparatus described below and the clock signal generating and synchronizing method described above may be referred to in correspondence with each other.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a clock signal generating and synchronizing apparatus according to an embodiment of the present invention, in the embodiment of the present invention, the clock signal generating and synchronizing apparatus includes a receiving module 501, a generating module 502, a first frequency dividing module 503, and a second frequency dividing module 504;
the receiving module 501 is configured to receive an external clock signal and perform two-stage distribution on the external clock signal;
the generating module 502 is configured to generate at least two second synchronous trigger signals according to the first clock module and a preset output mode of the interface when receiving the first synchronous trigger signal;
the first frequency dividing module 503 is configured to perform a first frequency division on the external clock signal after the two-stage distribution according to the first synchronization trigger signal and the first clock module;
the second frequency dividing module 504 is configured to perform second frequency division on the clock signal subjected to the first frequency division according to the second synchronous trigger signal, the second clock module, and a preset clock requirement, and output the clock signal subjected to the second frequency division.
The clock signal generation and synchronization device provided by the embodiment of the invention receives the external clock signal and performs two-stage distribution on the external clock signal; when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface; performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module; and performing secondary frequency division on the clock signal subjected to the primary frequency division according to a second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division. The clock signals are subjected to multi-stage frequency division processing based on the synchronous trigger signals, so that the generated clock signals have synchronism and adjustable clock frequency, the synchronism of the clock signals is ensured, and the generation efficiency of the clock signals is improved.
In one embodiment, the receiving module 501 is specifically configured to:
performing first-level distribution on the external clock signals according to the first clock cache to obtain a first path of external clock signals and a second path of external clock signals;
and carrying out second-level distribution on the first path of external clock signals according to a second clock cache, and sending the second path of external clock signals to next cascade equipment.
In an embodiment, the generating module 502 is specifically configured to:
triggering and distributing the first synchronous trigger signal according to the trigger cache to obtain a first path of synchronous trigger signal and a second path of synchronous trigger signal;
and sending the second path of synchronous trigger signal to the next cascade equipment.
In one embodiment, the first frequency dividing module 503 is specifically configured to:
and carrying out first frequency division on the external clock signal after the second-stage distribution according to the first path of synchronous trigger signal and the first clock module.
In an embodiment, the second frequency dividing module 504 is specifically configured to:
determining interface clock requirements, wherein the preset clock requirements comprise the interface clock requirements;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, the second clock module and the interface clock requirement.
In an embodiment, the second frequency dividing module 504 is specifically configured to:
determining synchronous clock requirements of a data converter, wherein the preset clock requirements comprise the synchronous clock requirements;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, the second clock module and the synchronous clock requirement.
In an embodiment, the generating module 502 is specifically configured to:
and configuring a preset output mode of the interface in the first clock module.
Fig. 6 illustrates a physical structure diagram of an electronic device, which may include, as shown in fig. 6: a processor (processor)610, a communication Interface (Communications Interface)620, a memory (memory)630 and a communication bus 640, wherein the processor 610, the communication Interface 620 and the memory 630 communicate with each other via the communication bus 640. The processor 610 may invoke logic instructions in the memory 630 to perform a method of clock signal generation and synchronization, the method comprising:
receiving an external clock signal, and performing two-stage distribution on the external clock signal;
when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface;
performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division.
In addition, the logic instructions in the memory 630 may be implemented in software functional units and stored in a computer readable storage medium when the logic instructions are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk, and various media capable of storing program codes.
In another aspect, the present invention also provides a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method for generating and synchronizing clock signals provided by the above methods, the method comprising:
receiving an external clock signal, and performing two-stage distribution on the external clock signal;
when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface;
performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of clock signal generation and synchronization, comprising:
receiving an external clock signal, and performing two-stage distribution on the external clock signal;
when receiving a first synchronous trigger signal, generating at least two second synchronous trigger signals according to a first clock module and a preset output mode of an interface;
performing first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, a second clock module and a preset clock requirement, and outputting the clock signal subjected to the secondary frequency division.
2. The method of generating and synchronizing clock signals according to claim 1, wherein said two-stage distributing of said external clock signal comprises:
performing first-level distribution on the external clock signals according to the first clock cache to obtain a first path of external clock signals and a second path of external clock signals;
and carrying out second-level distribution on the first path of external clock signals according to a second clock cache, and sending the second path of external clock signals to next cascade equipment.
3. The method for generating and synchronizing clock signals according to claim 2, wherein the generating at least two second synchronization trigger signals according to the first clock module and the preset output mode of the interface comprises:
triggering and distributing the first synchronous trigger signal according to the trigger cache to obtain a first path of synchronous trigger signal and a second path of synchronous trigger signal;
and sending the second path of synchronous trigger signal to the next cascade equipment.
4. The method for generating and synchronizing clock signals according to claim 3, wherein the first frequency dividing the two-stage distributed external clock signal according to the first synchronization trigger signal and the first clock module comprises:
and carrying out first frequency division on the external clock signal after the second-stage distribution according to the first path of synchronous trigger signal and the first clock module.
5. The method for generating and synchronizing clock signals according to claim 1, wherein the dividing the first divided clock signal according to the second synchronization trigger signal, a second clock module and a preset clock requirement comprises:
determining interface clock requirements, wherein the preset clock requirements comprise the interface clock requirements;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, the second clock module and the interface clock requirement.
6. The method for generating and synchronizing clock signals according to claim 1, wherein the dividing the first divided clock signal according to the second synchronization trigger signal, a second clock module and a preset clock requirement comprises:
determining synchronous clock requirements of a data converter, wherein the preset clock requirements comprise the synchronous clock requirements;
and carrying out secondary frequency division on the clock signal subjected to the primary frequency division according to the second synchronous trigger signal, the second clock module and the synchronous clock requirement.
7. The method for generating and synchronizing clock signals according to claim 1, wherein the generating at least two second synchronization trigger signals according to the first clock module and the preset output mode of the interface comprises:
and configuring a preset output mode of the interface in the first clock module.
8. An apparatus for generating and synchronizing a clock signal, comprising:
the receiving module is used for receiving an external clock signal and performing two-stage distribution on the external clock signal;
the generating module is used for generating at least two second synchronous trigger signals according to the first clock module and a preset output mode of the interface when receiving the first synchronous trigger signal;
the first frequency division module is used for carrying out first frequency division on the external clock signals distributed by the two stages according to the first synchronous trigger signal and the first clock module;
and the second frequency division module is used for carrying out second frequency division on the clock signal subjected to the first frequency division according to the second synchronous trigger signal, the second clock module and the preset clock requirement and outputting the clock signal subjected to the second frequency division.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of generating and synchronizing a clock signal according to any one of claims 1 to 7 when executing the program.
10. A non-transitory computer-readable storage medium having stored thereon a computer program, which when executed by a processor implements the method of generating and synchronizing a clock signal according to any one of claims 1 to 7.
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