CN108988858A - Clock distribution system and method - Google Patents
Clock distribution system and method Download PDFInfo
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- CN108988858A CN108988858A CN201810965288.4A CN201810965288A CN108988858A CN 108988858 A CN108988858 A CN 108988858A CN 201810965288 A CN201810965288 A CN 201810965288A CN 108988858 A CN108988858 A CN 108988858A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/26—Automatic control of frequency or phase; Synchronisation using energy levels of molecules, atoms, or subatomic particles as a frequency reference
Abstract
The present invention provides a kind of clock distribution system and methods, wherein, which includes: that at least one first clock buffer chip clock signal for providing clock source is fanned out to multiple mutually independent first synchronization output signals and is input to second clock buffer chip through time delay unit；First synchronization output signal is fanned out to multiple mutually independent second synchronization output signals by least two second clock buffer chips；The clock phase for the second synchronization output signal that excursion measurement unit obtains and more each second clock buffer chip is exported；Delay controller determines retardation corresponding with each clock phase according to the comparison result of excursion measurement unit；At least one time delay unit is adjusted according to clock phase of the retardation to the first synchronization output signal that each second clock buffer chip is inputted.Technical solution provided in an embodiment of the present invention, the skewed clock that can be generated between effectively different clock buffer, reduces the output error of interconnection system.
Description
Technical field
The present embodiments relate to medical diagnostic equipment technical field more particularly to a kind of clock distribution system and methods.
Background technique
Positron emission tomography (Positron Emission Tomography, PET) is buried in oblivion by detection
The opposite gamma photon of the energy equal direction that positron-electron is discharged to come realize to radioactive isotope distribution imaging.
The photon for burying in oblivion generation is detected by detector module different on detector ring respectively, and PET device judges that a pair of of photon comes from
The same annihilation event is sufficiently closed to according to the time for being two photons arrival detectors, such as 10ns, 4ns etc..
The higher TOF-PET of signal-to-noise ratio is that an annihilation event hair is judged by calculating the reaching time-difference of two photons
Raw location probability.If there are error, the distributions of the position of estimated annihilation event for the detection of photon arrival time
Center will deviate, this location information for being equivalent to provide mistake to image reconstruction will cause letter for image reconstruction
It makes an uproar than decline, or even the situation of image mistake occurs.
The clock distribution system of PET system is distributed using the clock of open loop at present, using the clock of lower skew
Buffer carries out clock distribution, but caused by the clock chip parameter discrete type as caused by semiconductor technology between piece and piece
Delay variance be inevitable, after having replaced clock distribution system, existing way must use system compensation
Method is calculated and is corrected to the time delay of the entire link of system；Whole process is very complicated and time-consuming, and needs to have
There is the participation of the radioactive source of specific shape, for the more demanding of technical staff, entire implementation process higher cost.
Skewed clock is often generated between different clocks buffer, is often stated with part to part skew.It is different
Clock buffer chip it is different to the delay of clock signal, several hundred picoseconds are generally reached, close to nanosecond rank, in order to realize
Component can be replaced directly, and the output bias of interconnection system is reduced, and a most important step is exactly to eliminate part to part
The influence of skew.
Summary of the invention
The embodiment of the invention provides a kind of clock distribution system and method, to solve by being generated in clock distribution procedure
The technical problem that data inaccuracy is acquired caused by clock skew, realizes the technology for reducing the output bias of interconnection system
Effect.
In a first aspect, the system includes: clock source, at least one the embodiment of the invention provides a kind of clock distribution system
A first clock buffer chip, at least one time delay unit, at least two second clock buffer chips, excursion measurement unit
And delay controller；Wherein,
Clock source, for providing clock signal；
First clock buffer chip, connect with clock source, same for clock signal to be fanned out to multiple mutually independent first
Step output signal is input to second clock buffer chip through time delay unit；
Second clock buffer chip, for the first synchronization output signal to be fanned out to multiple mutually independent second synchronism outputs
Signal；
Excursion measurement unit is connect at least one output channel in each second clock buffer chip, for obtaining simultaneously
Compare the clock phase for the second synchronization output signal that each second clock buffer chip is exported；
Delay controller is connect with excursion measurement unit, for being determined according to the comparison result of the excursion measurement unit
Retardation corresponding with each clock phase；
Time delay unit buffers core with the delay controller, the first clock buffer chip and second clock respectively
Piece connection, for being carried out according to clock phase of the retardation to the first synchronization output signal for inputting each second clock buffer chip
It adjusts.
Further, the sequencing for each clock phase that excursion measurement unit is also used to determine to get；
Delay controller is connect with excursion measurement unit, for according to the sequencing of each clock phase and preset
The error range of each clock phase determines the retardation of each time delay unit.
Further, time delay unit is also used to according to retardation, is buffered with preset step-length to each second clock is inputted
The clock phase of chip is adjusted.
Further, the difference value for each clock phase that excursion measurement unit is also used to determine to get；
Delay controller is connect with excursion measurement unit, for determining that each time prolongs according to the difference value of each clock phase
The retardation of slow unit.
Further, second clock buffer chip is also connect with detector module, for fanning the first synchronization output signal
Multiple mutually independent second synchronization output signals are input to different detector modules as reference clock out.
Further, the wiring in each second clock buffer chip between at least one output channel and excursion measurement unit
Parameter is identical, wherein wiring parameter includes at least one of length of arrangement wire, cabling type, stack type and carrier medium.
Second aspect, the embodiment of the invention also provides a kind of time clock distribution methods, this method comprises:
It is same that multiple mutually independent first are fanned out to by the clock signal that the first clock buffer chip is exported clock source
Step output signal is input to second clock buffer chip；
The first synchronization output signal is fanned out to multiple mutually independent second synchronism outputs by second clock buffer chip
Signal；
It is obtained by excursion measurement unit and at least one output channel institute is defeated in more each second clock buffer chip
The clock phase of the second synchronization output signal out；
Prolong corresponding with each clock phase is determined according to the comparison result of the excursion measurement unit by delay controller
Chi Liang；
By time delay unit according to retardation to the first synchronization output signal for inputting each second clock buffer chip
Clock phase be adjusted.
Further, described to pass through at least one in excursion measurement unit acquisition and more each second clock buffer chip
The clock phase for the second synchronization output signal that output channel is exported, comprising:
Pass through the sequencing for each clock phase that excursion measurement unit is determined to get；
By delay controller according to the sequencing of each clock phase and the error range of preset each clock phase
Determine the retardation of each time delay unit.
Further, described to be determined and each clock by delay controller according to the comparison result of the excursion measurement unit
The corresponding retardation of phase further include:
By time delay unit according to retardation with preset step-length to the clock phase for inputting each second clock buffer chip
Position is adjusted.
Further, described to be determined and each clock by delay controller according to the comparison result of the excursion measurement unit
The corresponding retardation of phase, further includes:
Pass through the difference value for each clock phase that excursion measurement unit is determined to get；
Correspondingly, by delay controller according to the determination of the comparison result of the excursion measurement unit and each clock phase pair
The retardation answered, including
The retardation of each time delay unit is determined according to the difference value of each clock phase by delay controller.
The technical solution of the embodiment of the present invention, by the first clock buffer chip and second clock buffer chip by clock source
Clock signal be fanned out to as multiple mutually independent second synchronization output signals, that is, realize when will be homologous by two-stage distribution
Clock signal is converted into multiple clock signals and is distributed, and is then relatively got by excursion measurement unit synchronous with each second
The clock phase of output signal, and then determined and each clock phase by delay controller according to the comparison result of excursion measurement unit
Corresponding retardation is most synchronized to input each second clock buffer chip first through time delay unit according to retardation defeated afterwards
The clock phase of signal is adjusted out, generates clock skew and needs manual synchronizing etc. repeatedly to solve clock distribution system
Technical problem realizes the output bias for reducing interconnection system, eliminates the clock skew between piece and piece to acquisition data
It is influenced caused by accuracy, optimizes the technical effect of existing clock distribution system.
Detailed description of the invention
In order to more clearly illustrate the technical scheme of the exemplary embodiment of the present invention, below to required in description embodiment
The attached drawing to be used does a simple introduction.Obviously, the attached drawing introduced is present invention a part of the embodiment to be described
Attached drawing, rather than whole attached drawings without creative efforts, may be used also for those of ordinary skill in the art
To obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of structural schematic diagram of clock distribution system provided by the embodiment of the present invention one；
Fig. 2 is a kind of flow diagram of clock distribution system provided by the embodiment of the present invention two.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Embodiment one
Fig. 1 is a kind of flow chart of the structural schematic diagram of clock distribution system provided by the embodiment of the present invention one.Such as Fig. 1
It is shown, the clock distribution system in the present embodiment include: clock source 10, at least one first clock buffer chip, at least one
Time delay unit 60, at least two second clock buffer chips 30, excursion measurement unit 40 and delay controller 50；Its
In, clock source 10, for providing clock signal；First clock buffer chip, connect with clock source 10, for fanning clock signal
Multiple mutually independent first synchronization output signals are input to second clock buffer chip 30 through time delay unit 60 out；Second
Clock buffer chip 30, for the first synchronization output signal to be fanned out to multiple mutually independent second synchronization output signals；Offset
Measuring unit 40 is connect at least one output channel in each second clock buffer chip 30, for obtaining and more each the
The clock phase for the second synchronization output signal that two clock buffer chips 30 are exported；Delay controller 50, with offset measurement list
Member 40 connects, for determining retardation corresponding with each clock phase according to the comparison result of the excursion measurement unit 40；When
Between delay cell 60, respectively with the first delay controller 50, the first clock buffer chip and second clock buffer chip 30 connect
It connects, for being adjusted according to clock phase of the retardation to the first synchronization output signal for inputting each second clock buffer chip 30
Section.
Wherein, clock source 10 preferably uses the high-precision clock source 10 of low jitter.Buffer chip the first clock buffer core
Piece 20 and buffer chip second clock buffer chip 30 are preferably the clock buffer chip using the low additional dither of low offset
Buffer has lower offset skew level in chip between each output channel.When time delay unit 60 can be programmable
Between delay cell 60, preferably with higher time adjustment precision programmable time delay unit 60.For example, can reach 10ps
And the programmable time delay unit 60 of the delay precision within 10ps.
Clock distribution system in the embodiment of the present invention may include that two and more than two buffer chip second clocks are slow
Rush chip 30.Further, each buffer chip second clock buffer chip 30 is fanned out to channel, such as each buffering with multiple
Chip second clock buffer chip 30 may include eight output channels of an input channel.Preferably, each buffer chip
Two clock buffer chips 30 all have lesser interior output offset.It can be more than 30 by buffer chip second clock buffer chip
Any one output channel in output channel is connected to the input port of excursion measurement unit 40 as feedback branch.Each
Buffer chip second clock buffer chip 30 all respectively has an output channel as feedback branch and is connected to excursion measurement unit 40.
It should be noted that the first clock buffer chip can be identical as second clock buffer chip 30, can also be different.
For example, the first clock buffer of buffer chip chip 20 may include four output channels of an input channel.
In order to which the otherness for reducing due to feedback branch impacts clock skew, the clock of preferably each feedback branch
The retardation of phase is equal.It specifically can be, the wiring parameter of each feedback branch is consistent.In i.e. each second clock buffer chip 30
Output channel and excursion measurement unit 40 between wiring parameter it is identical.Wherein wiring parameter includes length of arrangement wire, cabling class
At least one of type, stack type and carrier medium.For implementing on printing board PCB, the cloth that needs to control
Line parameter includes: PCB trace length, stack type and PCB material type etc., to guarantee the clock delay amount of each feedback branch
It is equal.
Optionally, the sequencing for each clock phase that excursion measurement unit 40 can be used for determining getting；Delay control
Device 50 processed, connect with excursion measurement unit 40, for the sequencing and preset each clock phase according to each clock phase
Error range determine the retardation of each time delay unit 60.
Alternatively, excursion measurement unit 40 can also be used in the difference value for each clock phase for determining to get；Delay control
Device 50 is connect with excursion measurement unit 40, for determining prolonging for each time delay unit 60 according to the difference value of each clock phase
Chi Liang.
Illustratively, excursion measurement unit 40 can by time-to-digit converter (Time Digital Converter,
TDC it) realizes.Optionally, TDC unit can pass through field programmable gate array (Field-Programmable Gate
Array, FPGA) carry chain realize.At this point, optional calibrated to TDC, further signal input port can also be carried out
Routing constraints, the advantages of this arrangement are as follows cabling inside FPGA can effectively be avoided to bring the extra delay offset measurement of signal
Unit 40.
Delay controller 50 can adjust each buffer chip second clock buffering according to the measurement result of excursion measurement unit 40
The retardation of the time delay unit 60 of 30 front of chip, to compensate the delay inequality of buffer chip second clock buffer chip 30
It is different, achieve the purpose that reduce output offset between different chips.
On this basis, time delay unit 60 is also used to slow to each second clock is inputted with preset step-length according to retardation
The clock phase for rushing chip 30 is adjusted.For example, the clock phase that can be exported with a second clock buffer chip 30 is made
For reference, the clock phase that remaining each second clock buffer chip 30 exports is adjusted.Fixed adjustment 10ps every time, until
The clock skew that each second clock buffer chip 30 exports is within the scope of preset, wherein adjustment includes in advance or prolonging
Afterwards.
On the basis of above-mentioned each technical solution, second clock buffer chip 30 can also be connect with detector module, be used for
First synchronization output signal is fanned out to multiple mutually independent second synchronization output signals and is input to different detector module works
For reference clock.
By the adjusting of retardation feedback control in above-mentioned clock distribution system, what each second clock buffer chip 30 exported
Clock phase difference can be controlled in the level of one single chip internal blas, can be less than 45 picoseconds, or even can reach
15 picoseconds of level, and hundreds of picoseconds of delay difference between chip will be eliminated.
The technical solution of the embodiment of the present invention, by the first clock buffer chip and second clock buffer chip by clock source
Clock signal be fanned out to as multiple mutually independent second synchronization output signals, that is, realize when will be homologous by two-stage distribution
Clock signal is converted into multiple clock signals and is distributed, and is then relatively got by excursion measurement unit synchronous with each second
The clock phase of output signal, and then determined and each clock phase by delay controller according to the comparison result of excursion measurement unit
Corresponding retardation, most afterwards through time delay unit according to retardation to input the clock phase of each second clock buffer chip into
Row is adjusted, and is generated clock skew and the needs technical problems such as manual synchronizing repeatedly to solve clock distribution system, is realized and reduce
The output bias of interconnection system eliminates shadow caused by accuracy of the clock skew to acquisition data between piece and piece
It rings, optimizes the technical effect of existing clock distribution system.
It certainly, can also include being buffered with second clock to realize the demand of multichannel in this clock distribution system
Chip third clock buffer chip, further, third clock buffer chip can also be connect with detector module, be used for second
Synchronization output signal is fanned out to multiple mutually independent third synchronization output signals and is input to different detector modules as reference
Clock.Further, second clock buffer chip and third clock buffer chip can also be provided with time delay unit, institute
It states time delay unit to connect with excursion measurement unit, the time clock distribution method mentioned in technical solution as above comes to input the
The clock signal of three clock buffer chips is adjusted.It is such, all excursion measurement units using the embodiment of the present invention
The scheme being adjusted with clock delay unit to clock signal is within the scope of the present invention.
It should be noted that detector module can be the detector cells for sharing the same reference clock.With PET system
For, in PET system, there are several detector modules to constitute a pet detector ring, each pet detector module tool
There is a reference clock.Therefore each detector module can be connected from different second clock buffer chips respectively.
It is understood that " the first clock buffer chip ", " second clock buffer chip " in the embodiment of the present invention and
" first ", " second " and " third " in " third clock buffer chip " is only used for distinguishing the clock buffer core of different levels
Piece, and it is non-limiting.
Embodiment two
Fig. 2 is a kind of flow diagram of time clock distribution method provided by the embodiment of the present invention two.This method is especially suitable
For needing the case where being adjusted to the clock skew generated in clock distribution procedure, can be provided by the embodiment of the present invention
Clock distribution system execute, which can be realized by way of software and/or hardware.
As shown in Fig. 2, the method for the present embodiment specifically includes:
S210, multiple mutually independent are fanned out to by the clock signal that the first clock buffer chip is exported clock source
One synchronization output signal is input to second clock buffer chip.
As previously mentioned, clock source preferably uses the high-precision clock source of low jitter.First clock buffer chip and second
Clock buffer chip is preferably the clock buffer chip using the low additional dither of low offset, has between each output channel in chip
Lower offset level.
S220, the first synchronization output signal is fanned out to by multiple mutually independent second synchronizations by second clock buffer chip
Output signal.
S230, pass through at least one output channel in excursion measurement unit acquisition and more each second clock buffer chip
The clock phase of the second synchronization output signal exported.
Optionally, the second synchronism output that at least one output channel is exported in more each second clock buffer chip
The clock phase of signal can be the sequencing that each clock phase got is determined by excursion measurement unit.Specifically
Ground, excursion measurement unit can be used for the clock phase exported between the different second clock buffer chip of comparison, that is, to piece
A kind of measurement of offset part to part skew between piece.The excursion measurement unit can need not provide accurate delay
Variance data, but be required to the precedence relationship of the more two or more clock phases of degree of precision.For example, it is assumed that when
Clock CH1 is advanced by 20ps than clock CH2, which need not provide the measurement result of 20ps, judges " clock CH1
Shift to an earlier date than clock CH2 " this result.
Alternatively, it is also possible to being the difference value for determining each clock phase got by excursion measurement unit.It is optional to be,
Using the clock phase of any one second clock buffer chip in each second clock buffer chip as reference clock phase, calculate
The difference value of the clock phase of remaining each second clock buffer chip and the reference clock phase.
S240, by delay controller according to the comparison result of the excursion measurement unit determination it is corresponding with each clock phase
Retardation.
It illustratively, can be by delay controller according to the sequencing and preset each clock phase of each clock phase
Error range determine the retardation of each time delay unit.It specifically, can will be any one in each second clock buffer chip
The clock phase of a second clock buffer chip is as target clock phase, according to remaining each second clock buffer chip wait adjust
Whole clock phase and the sequencing of the target clock phase determine the clock phase to be adjusted and the target clock
The retardation of each time delay unit of determination when the difference of phase is in error range.
Each time delay unit is determined according to the difference value of each clock phase by delay controller alternatively, can also be
Retardation.It specifically can be, the clock phase of any one second clock buffer chip in each second clock buffer chip made
For target clock phase, the clock phase of remaining each second clock buffer chip and the difference of the target clock phase are calculated,
Using and the corresponding difference of second clock buffer chip as each time delay unit corresponding with each second clock buffer chip
Retardation.
S250, by time delay unit according to retardation to the first synchronism output for inputting each second clock buffer chip
The clock phase of signal is adjusted.
It illustratively, can be by the clock phase of second clock buffer chip one of in each second clock buffer chip
As target clock phase, the corresponding clock phase of remaining each second clock buffer chip is adjusted to target phase always
Position.
It specifically can be, core buffered to each second clock is inputted with preset step-length according to retardation by time delay unit
The clock phase of piece is adjusted.Wherein, the specific value of preset step-length can be configured according to the actual situation, not done herein
It limits.Such as preset step-length can be 10 picoseconds, 5 picoseconds or 2 picoseconds etc..It is of course also possible to directly by each clock phase
Retardation of the difference value as time delay unit.
Time clock distribution method provided by executable any one embodiment of the invention of above-mentioned clock distribution system, has and holds
The corresponding functional module of the above-mentioned time clock distribution method of row and beneficial effect.The not technical detail of detailed description in the present embodiment,
It can be found in time clock distribution method provided by any one embodiment of the invention.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments here, be able to carry out for a person skilled in the art it is various it is apparent variation, again
Adjustment and substitution are without departing from protection scope of the present invention.Therefore, although by above embodiments to the present invention carried out compared with
For detailed description, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, can be with
Including more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of clock distribution system characterized by comprising clock source, at least one first clock buffer chip, at least one
A time delay unit, at least two second clock buffer chips, excursion measurement unit and delay controller；Wherein,
Clock source, for providing clock signal；
First clock buffer chip, connect with clock source, for by clock signal be fanned out to multiple mutually independent first synchronize it is defeated
Signal is input to second clock buffer chip through time delay unit out；
Second clock buffer chip is believed for the first synchronization output signal to be fanned out to multiple mutually independent second synchronism outputs
Number；
Excursion measurement unit is connect, for obtaining and comparing at least one output channel in each second clock buffer chip
The clock phase for the second synchronization output signal that each second clock buffer chip is exported；
Delay controller is connect with excursion measurement unit, for determining and each according to the comparison result of the excursion measurement unit
The corresponding retardation of clock phase；
Time delay unit connects with the delay controller, the first clock buffer chip and second clock buffer chip respectively
It connects, for being adjusted according to clock phase of the retardation to the first synchronization output signal for inputting each second clock buffer chip
Section.
2. system according to claim 1, it is characterised in that:
The sequencing for each clock phase that excursion measurement unit is also used to determine to get；
Delay controller is connect with excursion measurement unit, for according to the sequencing of each clock phase and it is preset each when
The error range of clock phase determines the retardation of each time delay unit.
3. system according to claim 2, it is characterised in that:
Time delay unit is also used to according to retardation, with preset step-length to the clock phase for inputting each second clock buffer chip
It is adjusted.
4. system according to claim 1, it is characterised in that:
The difference value for each clock phase that excursion measurement unit is also used to determine to get；
Delay controller is connect with excursion measurement unit, for determining each time delay list according to the difference value of each clock phase
The retardation of member.
5. system according to claim 1, which is characterized in that second clock buffer chip is also connect with detector module,
Different detector moulds is input to for the first synchronization output signal to be fanned out to multiple mutually independent second synchronization output signals
Block is as reference clock.
6. system according to claim 1, it is characterised in that: at least one output channel in each second clock buffer chip
Wiring parameter between excursion measurement unit is identical, wherein wiring parameter include length of arrangement wire, cabling type, stack type with
And at least one of carrier medium.
7. a kind of time clock distribution method characterized by comprising
By the clock signal that the first clock buffer chip is exported clock source be fanned out to multiple mutually independent first synchronize it is defeated
Signal is input to second clock buffer chip out；
The first synchronization output signal is fanned out to multiple mutually independent second synchronization output signals by second clock buffer chip；
It is exported by least one output channel in excursion measurement unit acquisition and more each second clock buffer chip
The clock phase of second synchronization output signal；
Retardation corresponding with each clock phase is determined according to the comparison result of the excursion measurement unit by delay controller；
By time delay unit according to retardation to the first synchronization output signal for inputting each second clock buffer chip when
Clock phase is adjusted.
8. being obtained by excursion measurement unit and more each the method according to the description of claim 7 is characterized in that described
The clock phase for the second synchronization output signal that at least one output channel is exported in two clock buffer chips includes:
Pass through the sequencing for each clock phase that excursion measurement unit is determined to get；
It is determined by delay controller according to the sequencing of each clock phase and the error range of preset each clock phase
The retardation of each time delay unit.
9. according to the method described in claim 8, it is characterized in that, it is described by delay controller according to the offset measurement list
The comparison result of member determines that retardation corresponding with each clock phase includes:
By time delay unit according to retardation with preset step-length to input the clock phase of each second clock buffer chip into
Row is adjusted.
10. the method according to the description of claim 7 is characterized in that it is described by delay controller according to the offset measurement
The comparison result of unit determines retardation corresponding with each clock phase further include:
Pass through the difference value for each clock phase that excursion measurement unit is determined to get；
Correspondingly, corresponding with each clock phase according to the determination of the comparison result of the excursion measurement unit by delay controller
Retardation, comprising:
The retardation of each time delay unit is determined according to the difference value of each clock phase by delay controller.
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| CN111466936A (en) * | 2020-03-31 | 2020-07-31 | 上海联影医疗科技有限公司 | Clock synchronization method and device and computer equipment |
| CN112257379A (en) * | 2020-10-30 | 2021-01-22 | 上海兆芯集成电路有限公司 | Method for correcting circuit clock delay |
| CN112737573A (en) * | 2020-12-21 | 2021-04-30 | 南京极景微半导体有限公司 | Clock skew calibration system, method and equipment based on daisy chain and computer storage medium |
| CN114640327A (en) * | 2022-05-11 | 2022-06-17 | 上海燧原科技有限公司 | Clock phase control circuit and chip |
| CN114815965A (en) * | 2022-06-29 | 2022-07-29 | 中星联华科技（北京）有限公司 | Clock signal generation and synchronization method and device |
| CN116418321A (en) * | 2023-03-28 | 2023-07-11 | 成都电科星拓科技有限公司 | Method and circuit for automatically adjusting multiple paths of clocks to keep output delay equal in power-on |
| US11931197B2 (en) | 2019-05-29 | 2024-03-19 | Shanghai United Imaging Healthcare Co., Ltd. | Systems and methods for clock synchronization |
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| CN112257379A (en) * | 2020-10-30 | 2021-01-22 | 上海兆芯集成电路有限公司 | Method for correcting circuit clock delay |
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