CN116418321B - Method and circuit for automatically adjusting multiple paths of clocks to keep output delay equal in power-on - Google Patents
Method and circuit for automatically adjusting multiple paths of clocks to keep output delay equal in power-on Download PDFInfo
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- CN116418321B CN116418321B CN202310318846.9A CN202310318846A CN116418321B CN 116418321 B CN116418321 B CN 116418321B CN 202310318846 A CN202310318846 A CN 202310318846A CN 116418321 B CN116418321 B CN 116418321B
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method and a circuit for automatically adjusting the delay of multi-channel clock output maintenance to be equal during power-on, wherein the method comprises the following steps: based on n paths of output circuits of a target clock chip, the same delay comparison circuits are respectively added between adjacent output circuits, and delay signals with delay information are respectively generated; and calculating delay information among n paths of output signals according to the delay signals, taking the maximum value in the delay information as a reference, and correspondingly delaying the output signals corresponding to the rest delay information to ensure that the finally output n paths of output signals have the same delay, namely no clock offset. The invention can complete clock offset detection in the power-on process of the target clock chip, delay corresponding output, meet the clock offset requirements of all the outputs, and can not cause the influence of power consumption and other performances on the target clock chip.
Description
Technical Field
The invention relates to the technical field of signal processing, in particular to a method and a circuit for automatically adjusting the delay of a multi-channel clock holding output to be equal when power is supplied.
Background
Conventional clock chips all integrate multiple Driver outputs, but in applications require that these Driver outputs guarantee a small skew (referring to clock skew, i.e. delay differences between multiple sub-clock signals generated by the same clock), e.g. skew <10ps, etc. In theory, the same structure can be used in the circuit to make the output delay of each Driver identical, i.e. the multiple output skew is basically 0. However, due to the different layout and routing and process variations, a larger skew may occur in the clock multipath Driver output.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method and a circuit for automatically adjusting the output delay of multiple clocks during power-up to be equal, which can automatically detect each output and perform delay comparison, then adjust the output delay, and optimize clock offset skew, thereby meeting the design requirements.
The technical scheme adopted by the invention is as follows:
a method for automatically adjusting multipath clock to keep output delay equal during power-up comprises the following steps:
s1, n-way output circuits based on target clock chips are arranged in adjacent output circuitsRespectively adding a same delay comparison circuit and respectively generating delay signals a with delay information 01 ,a 12 ,...,a (n-2)(n-1) The method comprises the steps of carrying out a first treatment on the surface of the Wherein n is a positive integer greater than or equal to 2;
s2, according to the delay signal a 01 ,a 12 ,...,a (n-2)(n-1) Calculating n-way output signal CLK out0 ,CLK out1 ,...,CLK out(n-1) Delay information between the two signals, taking the maximum value in the delay information as a reference, and correspondingly delaying output signals corresponding to the rest delay information to enable the finally output n paths of output signals CLK out0 ,CLK out1 ,...,CLK out(n-1) With the same delay, i.e. no clock skew.
Further, adjacent output signals CLK out i And CLK (CLK) out(i+1) The first shunt signal of (2) obtains delay information of the first shunt signal and the second shunt signal through an exclusive OR logic gate, and an analog signal X is output; wherein i is more than or equal to 0 and less than or equal to n-2.
Further, adjacent output signals CLK out i And CLK (CLK) out(i+1) The second split signal of the two is judged by the first D-type trigger DFF1, the signal with smaller delay is input into the delay unit for m times to obtain a signal Y, and the second D-type trigger DFF2 is used for sampling the analog signal X of the signal Y to obtain an adjacent output signal CLK out i And CLK (CLK) out(i+1) The delay information between them indicates the specific delay amount in m preset steps.
Further, after judging the signal with smaller delay in the two by the first D-type trigger DFF1, the signal is input to the delay unit by the multiplexing switch MUX.
Further, when the target clock chip is powered up, an OSC clock is internally generated for step S1 and step S2; after the execution of step S2 is completed, a control signal is generated by the logic circuit to turn off the OSC clock.
A circuit for automatically adjusting multipath clock to keep output delay equal during power-on comprises n-1 identical delay comparison circuits, wherein n is a positive integer greater than or equal to 2; the delay comparison circuitIs arranged between n paths of output circuits of the target clock chip and respectively generates delay signals a with delay information 01 ,a 12 ,...,a (n-2)(n-1) Based on the delay signal a 01 ,a 12 ,...,a (n-2)(n-1) Calculating n-way output signal CLK out0 ,CLK out1 ,...,CLK out(n-1) Delay information between the two signals, taking the maximum value in the delay information as a reference, and correspondingly delaying output signals corresponding to the rest delay information to enable the finally output n paths of output signals CLK out0 ,CLK out1 ,...,CLK out(n-1) With the same delay, i.e. no clock skew.
Further, the delay comparison circuit comprises an exclusive OR gate, adjacent output signals CLK out i And CLK (CLK) out(i+1) The first shunt signal of the (a) obtains delay information of the first shunt signal and the second shunt signal through the exclusive OR logic gate, and an analog signal X is output; wherein i is more than or equal to 0 and less than or equal to n-2.
Further, the delay comparison circuit further comprises a first D-type flip-flop DFF1, a delay unit and a second D-type flip-flop DFF2 which are electrically connected in sequence, and adjacent output signals CLK out i And CLK (CLK) out(i+1) The second split signal of the two is judged by the first D-type trigger DFF1, the signal with smaller delay is input into the delay unit for m times to obtain a signal Y, and the second D-type trigger DFF2 is used for sampling the analog signal X of the signal Y to obtain an adjacent output signal CLK out i And CLK (CLK) out(i+1) The delay information between them indicates the specific delay amount in m preset steps.
Further, the delay comparison circuit further includes a multiplexing switch MUX, and after judging the signal with smaller delay in the two signals, the signal is input to the delay unit through the multiplexing switch MUX.
Further, the delay comparator circuit also comprises a logic circuit, wherein when the target clock chip is powered up, an OSC clock is internally generated for the delay comparator circuit; when the delay comparison circuit is completed, a control signal is generated by the logic circuit to turn off the OSC clock.
The invention has the beneficial effects that:
1. the invention can complete clock offset detection in the power-on process of the target clock chip, delay corresponding output, meet the clock offset requirements of all the outputs, and can not cause the influence of power consumption and other performances on the target clock chip.
2. According to the invention, all the adjacent outputs of the target clock chip are detected, and all the outputs are compared one by one to obtain all the output delay signals, and in addition, the error influence caused by wiring of the detection delay circuit can be reduced as much as possible by detecting the adjacent outputs. Further, the detection accuracy can be improved by reducing the step of the delay unit.
Drawings
Fig. 1 is a schematic diagram of a conventional layout of a clock chip.
FIG. 2 is a schematic diagram of a circuit for automatically adjusting the hold-out delays of multiple clocks according to the present invention.
FIG. 3 is a schematic diagram of a delay comparison circuit of the present invention.
FIG. 4 is a timing diagram of a delay comparison circuit of the present invention.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
As shown in FIG. 1, a clock chip typically includes multiple outputs, 10 outputs CLK in FIG. 1 out0 ,CLK out1 ,...,CLK out10 . In principle, each path of output is output from the clock circuit to the chip bonding pad through the driving module Driver, and each path is the same. However, due to the actual layoutThe 10 outputs may have a large clock skew due to layout and routing effects, plus device mismatch, etc., depending on layout designer and process variations, etc.
As shown in fig. 2, the present embodiment provides a method for automatically adjusting the remaining output delay of a multi-channel clock during power-up, which includes the following steps:
s1, n paths of output circuits based on a target clock chip are respectively added with the same delay comparison circuit between adjacent output circuits, and delay signals a with delay information are respectively generated 01 ,a 12 ,...,a (n-2)(n-1) The method comprises the steps of carrying out a first treatment on the surface of the Wherein n is a positive integer greater than or equal to 2;
s2, according to the delay signal a 01 ,a 12 ,...,a (n-2)(n-1) Calculating n-way output signal CLK out0 ,CLK out1 ,...,CLK out(n-1) Delay information between the two signals, taking the maximum value in the delay information as a reference, and correspondingly delaying output signals corresponding to the rest delay information to enable the finally output n paths of output signals CLK out0 ,CLK out1 ,...,CLK out(n-1) With the same delay, i.e. no clock skew.
As shown in fig. 3 and 4, adjacent output signals CLK out i And CLK (CLK) out(i+1) The first shunt signal of (2) obtains delay information of the first shunt signal and the second shunt signal through an exclusive OR logic gate, and an analog signal X is output; wherein i is more than or equal to 0 and less than or equal to n-2. At the same time, adjacent output signals CLK out i And CLK (CLK) out(i+1) The second split signal of the two is judged by the first D-type trigger DFF1, the signal with smaller delay is input into the delay unit for m times to obtain a signal Y, and the second D-type trigger DFF2 is used for sampling the analog signal X of the signal Y to obtain an adjacent output signal CLK out i And CLK (CLK) out(i+1) The delay information between them indicates the specific delay amount in m preset steps.
Since the delay units are identical and the preset step is small, high accuracy can be achieved. Preferably, the accuracy may be improved by adjusting a minimum preset step of the delay unit. In addition, two adjacent outputs are selected in the target clock chip for comparison, so that wiring of the delay comparison circuit can be reduced, and errors caused by the delay comparison circuit module can be reduced as much as possible.
Preferably, after judging the signal with smaller delay in the two by the first D-type flip-flop DFF1, the signal is input to the delay unit by the multiplexing switch MUX.
Preferably, at power-up of the target clock chip, one OSC clock is internally generated for step S1 and step S2; after the execution of step S2 is completed, a control signal is generated by the logic circuit to turn off the OSC clock, so as to save power consumption and avoid other effects on the chip.
Example 2
As shown in fig. 2, the embodiment provides a circuit for automatically adjusting the delay of the multi-channel clock to be equal to the delay of the multi-channel clock, which comprises n-1 identical delay comparison circuits, wherein n is a positive integer greater than or equal to 2. The delay comparison circuit is arranged between n output circuits of the target clock chip and respectively generates delay signals a with delay information 01 ,a 12 ,...,a (n-2)(n-1) Based on the delay signal a 01 ,a 12 ,...,a (n-2)(n-1) Calculating n-way output signal CLK out0 ,CLK out1 ,...,CLK out(n-1) Delay information between the two signals, taking the maximum value in the delay information as a reference, and correspondingly delaying output signals corresponding to the rest delay information to enable the finally output n paths of output signals CLK out0 ,CLK out1 ,...,CLK out(n-1) With the same delay, i.e. no clock skew.
As shown in fig. 3 and 4, the delay comparison circuit includes an exclusive or logic gate, a first D-type flip-flop DFF1, a multiplexing switch MUX, a delay unit, and a second D-type flip-flop DFF2. Adjacent output signal CLK out i And CLK (CLK) out(i+1) The first shunt signal of (2) obtains delay information of the first shunt signal and the second shunt signal through an exclusive OR logic gate, and an analog signal X is output; wherein i is more than or equal to 0 and less than or equal to n-2. At the same time, adjacent output signals CLK out i And CLK (CLK) out(i+1) Is less delayed by the first D-type flip-flop DFF1The signal Y is obtained by m times of delay of the input delay unit of the multi-way selection switch MUX, and then the analog signal X is sampled by the signal Y through the second D-type trigger DFF2, so as to obtain the adjacent output signal CLK out i And CLK (CLK) out(i+1) The delay information between them indicates the specific delay amount in m preset steps.
Since the delay units are identical and the preset step is small, high accuracy can be achieved. Preferably, the accuracy may be improved by adjusting a minimum preset step of the delay unit. In addition, two adjacent outputs are selected in the target clock chip for comparison, so that wiring of the delay comparison circuit can be reduced, and errors caused by the delay comparison circuit module can be reduced as much as possible.
Preferably, the present embodiment further includes a logic circuit for generating an OSC clock internally for the delay comparison circuit when the target clock chip is powered up; when the delay comparison circuit works, a control signal is generated by the logic circuit to close the OSC clock, so that the power consumption is saved, and other influences on the chip are avoided.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (6)
1. A method for automatically adjusting the output delay of a plurality of paths of clocks to be equal when power is supplied, comprising the following steps:
s1. Target clock chip basednThe circuit output circuit adds a same delay comparison circuit between adjacent output circuits and generates delay signals with delay informationa 01 , a 12 , ..., a (n-2)(n-1) The method comprises the steps of carrying out a first treatment on the surface of the Wherein,nis greater than or equal toA positive integer of 2;
s2, according to the delay signala 01 , a 12 , ..., a (n-2)(n-1) Calculation ofnOutput signalCLK out0 , CLK out1 , ..., CLK out(n-1) Delay information between the two delay information, taking the maximum value in the delay information as a reference, and correspondingly delaying output signals corresponding to the rest delay information to finally outputnOutput signalCLK out0 , CLK out1 , ..., CLK out(n-1) With the same delay, i.e. no clock skew;
adjacent output signalsCLK out i AndCLK out(i+1) the first shunt signal of (2) obtains delay information of the first shunt signal and the second shunt signal through an exclusive OR logic gate, and an analog signal X is output; wherein, 0 is less than or equal toi≤n-2；
Adjacent output signalsCLK out i AndCLK out(i+1) the second divided signal of the first D-type trigger DFF1 judges the signal with smaller delay and inputs the signal into the delay unit for processingmThe secondary delay is carried out to obtain a signal Y, and then the signal Y is used for sampling an analog signal X through a second D-type trigger DFF2 to obtain an adjacent output signalCLK out i AndCLK out(i+1) delay information between, i.e. tomThe preset steps represent specific delay amounts.
2. The method for automatically adjusting the delay of the multi-way clock holding output to be equal according to claim 1, wherein after judging the signal with smaller delay in the two signals by the first D-type trigger DFF1, the signal is input to the delay unit by the multi-way selection switch MUX.
3. The method for automatically adjusting the multiple clock hold output delays to be equal according to claim 1 or 2, wherein when the target clock chip is powered up, an OSC clock is internally generated for calculating delay information in step S1 and step S2; after the execution of step S2 is completed, a control signal is generated by the logic circuit to turn off the OSC clock.
4. A circuit for automatically adjusting multipath clock to keep equal output delay when power is on is characterized by comprisingn-1 identical delay comparison circuit(s),nis a positive integer greater than or equal to 2; the delay comparison circuit is arranged on the target clock chipnBetween adjacent ones of the output circuits and respectively generating delay signals with delay informationa 01 , a 12 , ..., a (n-2)(n-1) Based on the delay signala 01 , a 12 , ..., a (n-2)(n-1) Calculation ofnOutput signalCLK out0 , CLK out1 , ..., CLK out(n-1) Delay information between the two delay information, taking the maximum value in the delay information as a reference, and correspondingly delaying output signals corresponding to the rest delay information to finally outputnOutput signalCLK out0 , CLK out1 , ..., CLK out(n-1) With the same delay, i.e. no clock skew;
the delay comparison circuit comprises an exclusive OR gate, adjacent output signalsCLK out i AndCLK out(i+1) the first shunt signal of the (a) obtains delay information of the first shunt signal and the second shunt signal through the exclusive OR logic gate, and an analog signal X is output; wherein, 0 is less than or equal toi≤n-2；
The delay comparison circuit also comprises a first D-type trigger DFF1, a delay unit and a second D-type trigger DFF2 which are electrically connected in sequence, and adjacent output signalsCLK out i AndCLK out(i+1) the second divided signal of the first D-type trigger DFF1 judges the signal with smaller delay and inputs the signal into the delay unit for processingmThe secondary delay is carried out to obtain a signal Y, and then the signal Y is used for sampling an analog signal X through a second D-type trigger DFF2 to obtain an adjacent output signalCLK out i AndCLK out(i+1) delay information between, i.e. tomThe preset steps represent specific delay amounts.
5. The circuit for automatically adjusting the delay of a multi-way clock holding output to be equal according to claim 4, wherein the delay comparison circuit further comprises a multi-way selection switch MUX, wherein the signal with smaller delay is input to the delay unit through the multi-way selection switch MUX after judging the signal with smaller delay in the two signals through the first D-type trigger DFF 1.
6. The circuit for automatically adjusting multiple clock hold output delays to be equal as in claim 4 or 5, further comprising logic circuitry for generating an OSC clock internally for said delay comparison circuit to calculate delay information when the target clock chip is powered up; when the delay comparison circuit is completed, a control signal is generated by the logic circuit to turn off the OSC clock.
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| CN202310318846.9A CN116418321B (en) | 2023-03-28 | 2023-03-28 | Method and circuit for automatically adjusting multiple paths of clocks to keep output delay equal in power-on |
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| CN202310318846.9A CN116418321B (en) | 2023-03-28 | 2023-03-28 | Method and circuit for automatically adjusting multiple paths of clocks to keep output delay equal in power-on |
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| US10153758B2 (en) * | 2016-04-20 | 2018-12-11 | SK Hynix Inc. | Efficient digital duty cycle adjusters |
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| JPH088730A (en) * | 1994-06-21 | 1996-01-12 | Mitsubishi Electric Corp | Synchronizing clock generation circuit |
| JPH1013219A (en) * | 1996-06-27 | 1998-01-16 | Mitsubishi Electric Corp | Clock signal deviation prevention circuit |
| US6320436B1 (en) * | 1999-02-18 | 2001-11-20 | Stmicroelectronics Limited | Clock skew removal apparatus |
| CN106899290A (en) * | 2017-02-16 | 2017-06-27 | 电子科技大学 | A kind of high accuracy multi-phase clock correcting circuit |
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