CN116418320B - Method and circuit for automatically adjusting delay equality of multipath frequency divider - Google Patents

Method and circuit for automatically adjusting delay equality of multipath frequency divider Download PDF

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CN116418320B
CN116418320B CN202310310595.XA CN202310310595A CN116418320B CN 116418320 B CN116418320 B CN 116418320B CN 202310310595 A CN202310310595 A CN 202310310595A CN 116418320 B CN116418320 B CN 116418320B
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delay
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frequency divider
divider
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CN116418320A (en
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李蓝
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Chengdu Cetc Xingtuo Technology Co ltd
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Chengdu Cetc Xingtuo Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention discloses a method and a circuit for automatically adjusting delay equality of a multipath frequency divider, wherein the method comprises the following steps: based on n-way frequency divider branches of a target clock chip, the same delay comparison circuits are respectively arranged between the ith frequency divider of the adjacent frequency divider branches, and delay signals with delay information are respectively generated; wherein i is more than or equal to 2 and less than or equal to m, and m and n are positive integers more than or equal to 2; and respectively calculating delay information among the ith frequency dividers of the n paths of output signals according to the delay signals, taking the maximum value in the delay information as a reference, and correspondingly delaying the output signals corresponding to the rest delay information, so that each frequency divider of the n paths of output signals finally output has the same delay, namely no clock offset. The invention can detect the output delay of the frequency divider, compare the delay step by step and compensate the delay step by step, thereby avoiding the time sequence error generated when the conventional synchronous processing is carried out due to the overlarge delay of the whole frequency divider.

Description

Method and circuit for automatically adjusting delay equality of multipath frequency divider
Technical Field
The present invention relates to the field of signal processing technologies, and in particular, to a method and a circuit for automatically adjusting delay equality of a multipath frequency divider.
Background
In the clock chip buffer, there are basically multiple outputs, so that to ensure that all outputs have the same skew (refer to clock offset, that is, delay difference between multiple sub-clock signals generated by the same clock), all modules in the clock chip buffer ensure the same skew as much as possible, especially the frequency divider, because different output branch frequency dividers may select different frequency division ratios, so that different branch frequency divider circuits have natural differences for a long time, and different delays will definitely occur.
Disclosure of Invention
In order to solve the problem that the frequency divider has different delays under the condition of different frequency dividing ratios, the invention provides a method and a circuit for automatically adjusting the delay equality of a plurality of frequency dividers, which can automatically adjust the delay to realize that the plurality of frequency dividers have the same clock offset.
The technical scheme adopted by the invention is as follows:
a method for automatically adjusting the delay equality of a multi-way frequency divider, comprising the steps of:
s1, setting the same delay comparison circuit between the ith frequency divider of the adjacent frequency divider branches based on n frequency divider branches of a target clock chip, and generating delay signals with delay information respectively; wherein i is more than or equal to 2 and less than or equal to m, and m and n are positive integers more than or equal to 2;
s2, respectively calculating delay information among the ith frequency divider of the n paths of output signals according to the delay signals, taking the maximum value in the delay information as a reference, and correspondingly delaying the output signals corresponding to the rest delay information, so that each frequency divider of the n paths of output signals finally output has the same delay, namely no clock offset.
Further, when the frequency divider branch of the target clock chip is two, the step S2 includes the following sub-steps:
s201 outputting signal CLK of two-way frequency divider branch 1 And CLK (CLK) 2 Input to the first D-type flip-flop DFF1, sampling the rising edge of the signal, when outputting the signal CLK 1 Is greater than the delay of the output signal CLK 2 When the first D-type flip-flop DFF1 outputs 0, step S202 is executed again; otherwise, outputting 1, and executing step S202;
s202 outputting the signal CLK 1 The signal X is obtained by the first bypass input to the first multiplexer MUX1, and the output signal CLK is outputted 2 The second delay unit is input for delay, and then the delay unit is input to the second multiplexing switch MUX2 to obtain a signal Y, and meanwhile, the signal X and the signal Y are selected through the third multiplexing switch MUX3, so that the signal Y is used as a clock to sample the signal X to obtain a signal Z;
s203 outputting the signal CLK 1 The first delay unit is input to delay and then input to the first multiplexing switch MUX1 to obtain a signal X, and the output signal CLK 2 The signal Y is obtained by inputting the signal X to a second multiplexing switch MUX2 through a second bypass, and the signal X and the signal Y are selected through a third multiplexing switch MUX3, so that the signal X is used as a clock to sample the signal Y to obtain a signal Z;
s204, obtaining a specific delay amount of the signal Z from 0 to 1 by data analysis of the signal Z, thereby obtaining an output signal CLK 1 And CLK (CLK) 2 Between (a) and (b)And feeding back the delay difference to the corresponding frequency divider, and performing equivalent delay processing on the frequency divider with smaller delay.
Further, in step S201, in the output signal CLK 1 And CLK (CLK) 2 Before the first D-type trigger DFF1 is entered to sample the rising edge of the signal, the reset is performed to enable the output signal CLK 1 And CLK (CLK) 2 All with a high-first and a low-second signal.
Further, when the delay between the ith frequency divider is smaller than a preset value and the sum of the delays of the m frequency dividers does not exceed one high-frequency clock cycle, the delay comparison circuit between the ith frequency divider is turned off.
Further, in the power-on completion stage of the target clock chip, generating a clock signal through the oscillator OSC to perform delay detection on the whole frequency divider and complete delay compensation; when the delay compensation is completed, the oscillator OSC is turned off and the divider delay compensation is cured.
A circuit for automatically adjusting the equal delay of a multi-path frequency divider is applied to n-path frequency divider branches of a target clock chip, and comprises (m-1) (n-1) identical delay comparison circuits, wherein m and n are positive integers greater than or equal to 2; the delay comparison circuit is arranged between the ith frequency divider of the adjacent frequency divider branch circuits, i is more than or equal to 2 and less than or equal to m, delay signals with delay information are respectively generated, the delay information between the ith frequency divider of the n paths of output signals is respectively calculated according to the delay signals, the maximum value in the delay information is taken as a reference, the output signals corresponding to the rest delay information are correspondingly delayed, and each frequency divider of the n paths of output signals which are finally output has the same delay, namely no clock offset.
Further, when the divider branch of the target clock chip is two-way, the delay comparison circuit includes a first D-type flip-flop DFF1, a second D-type flip-flop DFF2, a first delay unit, a second delay unit, a first bypass, a second bypass, a first multiplexing switch MUX1, a second multiplexing switch MUX2, and a third multiplexing switch MUX3, the first D-type flip-flop DFF1 is configured to receive the outputs of the two-way divider branchOutput signal CLK 1 And CLK (CLK) 2 And samples the rising edge of the signal.
When outputting the signal CLK 1 Is greater than the delay of the output signal CLK 2 At the same time, the first D-type flip-flop DFF1 outputs 0 and outputs the signal CLK 1 The signal X is obtained by the first bypass input to the first multiplexer MUX1, and the output signal CLK is outputted 2 The signal X and the signal Y are selected by a third multiplexing switch MUX3, so that the signal Y is used as a clock to sample the signal X to obtain a signal Z.
When outputting the signal CLK 1 Is greater than the delay of the output signal CLK 2 At the same time, the first D-type flip-flop DFF1 outputs 1, which outputs the signal CLK 1 The first delay unit is input to delay and then input to the first multiplexing switch MUX1 to obtain a signal X, and the output signal CLK 2 The signal Y is obtained by inputting the second bypass to the second multiplexing switch MUX2, and the signal X and the signal Y are selected by the third multiplexing switch MUX3, so that the signal X is used as a clock to sample the signal Y to obtain the signal Z.
The second D-type flip-flop DFF2 is configured to perform data analysis on the signal Z to obtain a specific delay amount of the signal Z from 0 to 1, thereby obtaining an output signal CLK 1 And CLK (CLK) 2 And the delay difference is fed back to the corresponding frequency divider, and the frequency divider with smaller delay is subjected to equivalent delay processing.
Further, at the output signal CLK 1 And CLK (CLK) 2 Before the first D-type trigger DFF1 is entered to sample the rising edge of the signal, the reset is performed to enable the output signal CLK 1 And CLK (CLK) 2 All with a high-first and a low-second signal.
Further, when the delay between the ith frequency divider is smaller than a preset value and the sum of the delays of the m frequency dividers does not exceed one high-frequency clock cycle, the delay comparison circuit between the ith frequency divider is turned off.
Further, in the power-on completion stage of the target clock chip, generating a clock signal through the oscillator OSC to perform delay detection on the whole frequency divider and complete delay compensation; when the delay compensation is completed, the oscillator OSC is turned off and the divider delay compensation is cured.
The invention has the beneficial effects that:
1. the invention can detect the output delay of the frequency divider, compare the delay step by step and compensate the delay step by step, thereby avoiding the time sequence error generated when the conventional synchronous processing is carried out due to the overlarge delay of the whole frequency divider.
2. The invention carries out delay detection compensation after the target clock chip is electrified, and the module is closed after detection is finished, so that the normal operation of the chip is not influenced.
3. The invention can select to carry out one-time delay detection processing after the multi-stage frequency divider when the frequency divider delay is smaller, and is more flexible.
Drawings
Fig. 1 is a schematic diagram of a two-way divider connection.
Fig. 2 is a schematic diagram of the delay detection principle of the frequency divider of the present invention.
FIG. 3 is a schematic diagram of a delay comparison circuit of the present invention.
FIG. 4 is a timing diagram of the operation of the delay comparison circuit of the present invention.
FIG. 5 is a second timing diagram of the delay comparison circuit of the present invention.
Detailed Description
Specific embodiments of the present invention will now be described in order to provide a clearer understanding of the technical features, objects and effects of the present invention. It should be understood that the particular embodiments described herein are illustrative only and are not intended to limit the invention, i.e., the embodiments described are merely some, but not all, of the embodiments of the invention. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present invention.
Example 1
As shown in fig. 1, the divider output signal CLK 1 And CLK (CLK) 2 Respectively the oscillator passing through two frequency dividersBranch outputs require different division ratio selections because the frequency divider a1, a2, and a3 output frequencies are different from the frequency divider b1, b2, and b3 at different application fields. For example, divider a1, divider a2, and divider a3 are all divide-by-two, while divider b1, divider b2, and divider b3 are all divide-by-three. Since the divide-by-two and divide-by-three circuit structures are completely different, the delays are naturally different, resulting in an output signal CLK 1 And CLK (CLK) 2 With a large clock offset skew.
In a conventional scenario, to meet the same clock offset skew, the output signal CLK 1 And CLK (CLK) 2 The same high frequency clock is synchronously adopted to obtain zero-delay output. However, when the frequency divider delay experienced is large (more than one high frequency synchronous clock cycle), the synchronous output becomes erroneous data, and this approach is not satisfactory for most high speed clock chip applications.
In order to meet most of applications, the present embodiment proposes to perform delay detection and delay compensation on each stage of frequency divider output, so that after several stages of frequency divider output, the overall delay will not exceed the high-frequency synchronous clock period, and then perform synchronous processing on the frequency divider output to obtain the frequency divider output clock signal with zero skew requirement, which is specifically implemented as follows.
As shown in fig. 2, the present embodiment provides a method for automatically adjusting delay equality of a multi-path frequency divider, which includes the following steps:
s1, setting the same delay comparison circuit between the ith frequency divider of the adjacent frequency divider branches based on n frequency divider branches of a target clock chip, and generating delay signals with delay information respectively; wherein i is more than or equal to 2 and less than or equal to m, and m and n are positive integers more than or equal to 2;
s2, respectively calculating delay information among the ith frequency divider of the n paths of output signals according to the delay signals, taking the maximum value in the delay information as a reference, and correspondingly delaying the output signals corresponding to the rest delay information, so that each frequency divider of the n paths of output signals finally output has the same delay, namely no clock offset.
Preferably, as shown in fig. 3, when the divider branch of the target clock chip is two-way, step S2 includes the following sub-steps:
s201 outputting signal CLK of two-way frequency divider branch 1 And CLK (CLK) 2 Is input to a first D-type flip-flop DFF1, which samples the rising edge of the signal (here CLK is seen only 1 And CLK (CLK) 2 The first rising edge due to CLK 1 And CLK (CLK) 2 The clock frequency may be different) when outputting the signal CLK 1 Is greater than the delay of the output signal CLK 2 When the first D-type flip-flop DFF1 outputs 0, step S202 is executed again; otherwise, outputting 1, and executing step S202;
s202 outputting the signal CLK 1 The signal X is obtained by the first bypass input to the first multiplexer MUX1, and the output signal CLK is outputted 2 The signal X and the signal Y are selected through a third multiplexing switch MUX3, so that the signal Y is used as a clock to sample the signal X to obtain a signal Z, and the time sequence is shown in figure 4;
s203 outputting the signal CLK 1 The first delay unit is input to delay and then input to the first multiplexing switch MUX1 to obtain a signal X, and the output signal CLK 2 The signal Y is obtained by inputting the signal X to a second multiplexing switch MUX2 through a second bypass, and the signal X and the signal Y are selected through a third multiplexing switch MUX3, so that the signal X is used as a clock to sample the signal Y to obtain a signal Z, and the time sequence is shown in figure 5;
s204, obtaining a specific delay amount of the signal Z from 0 to 1 by data analysis of the signal Z, thereby obtaining an output signal CLK 1 And CLK (CLK) 2 And the delay difference is fed back to the corresponding frequency divider, and the frequency divider with smaller delay is subjected to equivalent delay processing.
Preferably, in step S201, in the output signal CLK 1 And CLK (CLK) 2 Before the first D-type trigger DFF1 is entered to sample the rising edge of the signal, the reset is performed to enable the output signal CLK 1 And CLK (CLK) 2 All with high-level signal and low-level signal。
Preferably, when the delay between the i-th frequency dividers is smaller than a preset value and the sum of the delays of the m-th frequency dividers does not exceed one high-frequency clock cycle, the delay comparison circuit between the i-th frequency dividers is turned off. Specifically, since in some applications, the delays of the frequency dividers a1 and b1, a2 and b2, and a3 and b3 may be small, the delay comparing circuits between the previous stages of frequency dividers may be turned off directly, and the delay comparing circuits corresponding to the frequency dividers a3 and b3 may be turned on directly. Of course, this is only for the case that the delays of the stage frequency dividers a1 and b1, a2 and b2, and a3 and b3 are small, that is, when the sum of the delays does not exceed one high-frequency clock cycle, the stage frequency dividers must respectively perform delay detection processing when the delay is large, so as to prevent timing errors.
Preferably, in the power-on completion stage of the target clock chip, the clock signal is generated by the oscillator OSC to perform delay detection on the whole frequency divider and complete delay compensation; when the delay compensation is completed, the oscillator OSC is turned off, reducing power consumption and performance impact, and the divider delay compensation is cured, so that the divider no longer has delay skew due to the delay compensation as long as the target clock chip is not powered down.
Example 2
As shown in fig. 2, the present embodiment provides a circuit for automatically adjusting the delay equality of a multi-path frequency divider, which is applied to n-path frequency divider branches of a target clock chip, and includes (m-1) (n-1) identical delay comparison circuits, where m and n are positive integers greater than or equal to 2; the delay comparison circuit is arranged between the ith frequency divider of the adjacent frequency divider branch circuits, i is more than or equal to 2 and less than or equal to m, delay signals with delay information are respectively generated, the delay information between the ith frequency divider of the n paths of output signals is respectively calculated according to the delay signals, the maximum value in the delay information is taken as a reference, the output signals corresponding to the rest delay information are correspondingly delayed, and each frequency divider of the n paths of output signals which are finally output has the same delay, namely no clock offset.
Preferably, the delay comparison circuit comprises a first D-type flip-flop DFF1, a second D-type flip-flop DFF2, and a first delay unit when the divider branch of the target clock chip is two-wayA cell, a second delay unit, a first bypass, a second bypass, a first multiplexing switch MUX1, a second multiplexing switch MUX2 and a third multiplexing switch MUX3, the first D-type flip-flop DFF1 being configured to receive the output signal CLK of the two divider branches 1 And CLK (CLK) 2 And samples the rising edge of the signal.
When outputting the signal CLK 1 Is greater than the delay of the output signal CLK 2 At the same time, the first D-type flip-flop DFF1 outputs 0 and outputs the signal CLK 1 The signal X is obtained by the first bypass input to the first multiplexer MUX1, and the output signal CLK is outputted 2 The signal X and the signal Y are selected through a third multiplexing switch MUX3, so that the signal Y is used as a clock to sample the signal X to obtain a signal Z, and the time sequence is shown in figure 4;
when outputting the signal CLK 1 Is greater than the delay of the output signal CLK 2 At the same time, the first D-type flip-flop DFF1 outputs 1, which outputs the signal CLK 1 The first delay unit is input to delay and then input to the first multiplexing switch MUX1 to obtain a signal X, and the output signal CLK 2 The signal Y is obtained by inputting the signal X to a second multiplexing switch MUX2 through a second bypass, and the signal X and the signal Y are selected through a third multiplexing switch MUX3, so that the signal X is used as a clock to sample the signal Y to obtain a signal Z, and the time sequence is shown in figure 5;
the second D-type flip-flop DFF2 is configured to perform data analysis on the signal Z to obtain a specific delay amount of the signal Z from 0 to 1, thereby obtaining the output signal CLK 1 And CLK (CLK) 2 And the delay difference is fed back to the corresponding frequency divider, and the frequency divider with smaller delay is subjected to equivalent delay processing.
Preferably, at the output signal CLK 1 And CLK (CLK) 2 Before the first D-type trigger DFF1 is entered to sample the rising edge of the signal, the reset is performed to enable the output signal CLK 1 And CLK (CLK) 2 All with a high-first and a low-second signal.
Preferably, when the delay between the i-th frequency dividers is smaller than a preset value and the sum of the delays of the m-th frequency dividers does not exceed one high-frequency clock cycle, the delay comparison circuit between the i-th frequency dividers is turned off. Specifically, since in some applications, the delays of the frequency dividers a1 and b1, a2 and b2, and a3 and b3 may be small, the delay comparing circuits between the previous stages of frequency dividers may be turned off directly, and the delay comparing circuits corresponding to the frequency dividers a3 and b3 may be turned on directly. Of course, this is only for the case that the delays of the stage frequency dividers a1 and b1, a2 and b2, and a3 and b3 are small, that is, when the sum of the delays does not exceed one high-frequency clock cycle, the stage frequency dividers must respectively perform delay detection processing when the delay is large, so as to prevent timing errors.
Preferably, in the power-on completion stage of the target clock chip, the clock signal is generated by the oscillator OSC to perform delay detection on the whole frequency divider and complete delay compensation; when the delay compensation is completed, the oscillator OSC is turned off, reducing power consumption and performance impact, and the divider delay compensation is cured, so that the divider no longer has delay skew due to the delay compensation as long as the target clock chip is not powered down.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.

Claims (8)

1. A method for automatically adjusting the delay equality of a multi-way frequency divider, comprising the steps of:
s1. Target clock chip basednA circuit divider branch, the first of the adjacent divider branchesiThe same delay comparison circuits are respectively arranged between the stage frequency dividers, and delay signals with delay information are respectively generated; wherein, the content of the active ingredients is less than or equal to 2i≤m，mRepresenting the number of stages of the frequency divider,mandnis a positive integer greater than or equal to 2;
s2, respectively calculating according to the delay signalsnOutput signal of wayiDelay information between the stage frequency dividers takes the maximum value in the delay information as a reference, and correspondingly delays output signals corresponding to the rest delay information to finally outputnEach frequency divider of the output signal has the same delay, namely no clock offset;
when the frequency divider branch of the target clock chip is two paths, the step S2 includes the following substeps:
s201, outputting signals of two frequency divider branchesCLK 1 AndCLK 2 input to a first D-type flip-flop DFF1, sampling the rising edge of the signal, and outputting a signalCLK 1 Is greater than the output signalCLK 2 When the first D-type flip-flop DFF1 outputs 0, step S202 is executed again; otherwise, outputting 1, and executing step S202;
s202, outputting the signalCLK 1 The signal X is obtained by the first bypass input to the first multiplexing switch MUX1, and the output signalCLK 2 The second delay unit is input for delay, and then the delay unit is input to the second multiplexing switch MUX2 to obtain a signal Y, and meanwhile, the signal X and the signal Y are selected through the third multiplexing switch MUX3, so that the signal Y is used as a clock to sample the signal X to obtain a signal Z;
s203, outputting the signalCLK 1 The first delay unit is input to delay and then input to the first multiplexing switch MUX1 to obtain a signal X, and the output signalCLK 2 The signal Y is obtained by inputting the signal X to a second multiplexing switch MUX2 through a second bypass, and the signal X and the signal Y are selected through a third multiplexing switch MUX3, so that the signal X is used as a clock to sample the signal Y to obtain a signal Z;
s204, obtaining a specific delay amount of the signal Z from 0 to 1 by data analysis of the signal Z, thereby obtaining an output signalCLK 1 AndCLK 2 the delay difference is fed back to the corresponding frequency divider to perform equivalent delay on the frequency divider with smaller delayAnd (5) managing.
2. The method for automatically adjusting delay equality of a multiple divider according to claim 1, wherein in step S201, in the output signalCLK 1 AndCLK 2 before the first D-type trigger DFF1 is entered to sample the rising edge of the signal, the first D-type trigger DFF1 is reset to output the signalCLK 1 AndCLK 2 all with a high-first and a low-second signal.
3. A method for automatically adjusting delay equality of a multi-way divider according to claim 1 or 2, characterized in that when the firstiThe delay between the stage dividers is less than a predetermined value, andmwhen the delay sum of the stage divider does not exceed one high frequency clock cycle, the first stage is turned offiDelay comparison circuit between stage dividers.
4. The method for automatically adjusting the delay equality of a multi-way frequency divider according to claim 1 or 2, wherein the delay detection is performed on the whole frequency divider and the delay compensation is performed by generating a clock signal through an oscillator OSC at the power-on completion stage of the target clock chip; when the delay compensation is completed, the oscillator OSC is turned off and the divider delay compensation is cured.
5. A circuit for automatically adjusting delay equality of multiple frequency dividers is applied to a target clock chipnThe circuit is characterized by comprisingm-1)(n-1) identical delay comparison circuits,mrepresenting the number of stages of the frequency divider,mandnis a positive integer greater than or equal to 2; the delay comparison circuit is arranged at the first of the adjacent frequency divider branchesiBetween the stage frequency dividers, 2 is less than or equal toi≤mRespectively generating delay signals with delay information, and respectively calculating according to the delay signalsnOutput signal of wayiDelay information between the stage frequency dividers takes the maximum value in the delay information as a reference, and correspondingly delays output signals corresponding to the rest delay information to finally outputnEach frequency divider of the output signal has the same delay, namely no clock offset;
when the divider branch of the target clock chip is two-way, the delay comparison circuit comprises a first D-type trigger DFF1, a second D-type trigger DFF2, a first delay unit, a second delay unit, a first bypass, a second bypass, a first multiplexing switch MUX1, a second multiplexing switch MUX2 and a third multiplexing switch MUX3, wherein the first D-type trigger DFF1 is configured to receive the output signals of the two-way divider branchCLK 1 AndCLK 2 sampling the rising edge of the signal;
when outputting a signalCLK 1 Is greater than the output signalCLK 2 At the time, the first D-type flip-flop DFF1 outputs 0, the output signalCLK 1 The signal X is obtained by the first bypass input to the first multiplexing switch MUX1, and the output signalCLK 2 The second delay unit is input for delay, and then the delay unit is input to the second multiplexing switch MUX2 to obtain a signal Y, and meanwhile, the signal X and the signal Y are selected through the third multiplexing switch MUX3, so that the signal Y is used as a clock to sample the signal X to obtain a signal Z;
when outputting a signalCLK 1 Is greater than the output signalCLK 2 At the time, the first D-type flip-flop DFF1 outputs 1, outputs a signalCLK 1 The first delay unit is input to delay and then input to the first multiplexing switch MUX1 to obtain a signal X, and the output signalCLK 2 The signal Y is obtained by inputting the signal X to a second multiplexing switch MUX2 through a second bypass, and the signal X and the signal Y are selected through a third multiplexing switch MUX3, so that the signal X is used as a clock to sample the signal Y to obtain a signal Z;
the second D-type flip-flop DFF2 is configured to perform data analysis on the signal Z to obtain a specific delay amount of the signal Z from 0 to 1, thereby obtaining an output signalCLK 1 AndCLK 2 and the delay difference is fed back to the corresponding frequency divider, and the frequency divider with smaller delay is subjected to equivalent delay processing.
6. The circuit for automatically adjusting delay equality of a multiple divider according to claim 5, wherein, at the output signalCLK 1 AndCLK 2 before the first D-type trigger DFF1 is entered to sample the rising edge of the signal, the first D-type trigger DFF1 is reset to output the signalCLK 1 AndCLK 2 all with a high-first and a low-second signal.
7. The circuit for automatically adjusting delay equality of a multi-way divider according to claim 5 or 6, wherein when the firstiThe delay between the stage dividers is less than a predetermined value, andmwhen the delay sum of the stage divider does not exceed one high frequency clock cycle, the first stage is turned offiDelay comparison circuit between stage dividers.
8. The circuit for automatically adjusting the delay equality of a multi-way frequency divider according to claim 5 or 6, wherein the delay detection and delay compensation of the whole frequency divider are performed by generating a clock signal through an oscillator OSC during the power-on completion phase of the target clock chip; when the delay compensation is completed, the oscillator OSC is turned off and the divider delay compensation is cured.
CN202310310595.XA 2023-03-28 2023-03-28 Method and circuit for automatically adjusting delay equality of multipath frequency divider Active CN116418320B (en)

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