CN108988858B - Clock distribution system and method - Google Patents
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- CN108988858B CN108988858B CN201810965288.4A CN201810965288A CN108988858B CN 108988858 B CN108988858 B CN 108988858B CN 201810965288 A CN201810965288 A CN 201810965288A CN 108988858 B CN108988858 B CN 108988858B
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/26—Automatic control of frequency or phase; Synchronisation using energy levels of molecules, atoms, or subatomic particles as a frequency reference
Abstract
The invention provides a clock distribution system and a method, wherein the system comprises: at least one first clock buffer chip fans out a clock signal provided by a clock source to a plurality of mutually independent first synchronous output signals and inputs the signals to a second clock buffer chip through a time delay unit; the at least two second clock buffer chips fan out the first synchronous output signals into a plurality of mutually independent second synchronous output signals; the offset measuring unit acquires and compares the clock phases of second synchronous output signals output by the second clock buffer chips; the delay controller determines delay amounts corresponding to the clock phases according to the comparison result of the offset measurement unit; and the at least one time delay unit adjusts the clock phase of the first synchronous output signal input by each second clock buffer chip according to the delay amount. The technical scheme provided by the embodiment of the invention can effectively generate clock skew among different clock buffers and reduce the output error of a clock distribution system.
Description
Technical Field
The embodiment of the invention relates to the technical field of medical diagnosis equipment, in particular to a clock distribution system and a clock distribution method.
Background
Positron Emission Tomography (PET) images the distribution of a radioisotope by detecting pairs of gamma photons of equal energy and opposite directions released by annihilated Positron-Positron electrons. Photons generated by annihilation are detected by different detector modules in the detector ring, and the PET device determines that a pair of photons originates from the same annihilation event based on the arrival of the two photons at the detector in close enough time, e.g., 10ns,4ns, etc.
TOF-PET with a higher signal-to-noise ratio determines the probability of the occurrence of an annihilation event by calculating the difference in arrival times of two photons. If the photon arrival time is detected with errors, the center of the distribution of the estimated annihilation event location is shifted, which is equivalent to providing the image reconstruction with wrong location information, causing a decrease in signal-to-noise ratio for the image reconstruction and even an image error.
The clock distribution system of the current PET system adopts open-loop clock distribution, and adopts a clock buffer with lower skew to carry out clock distribution, but the delay difference between chips caused by the discrete type of clock chip parameters caused by a semiconductor process is inevitable; the whole process is very tedious and time-consuming, and requires the participation of a radioactive source with a specific shape, the requirements on technical personnel are high, and the cost of the whole implementation process is high.
Clock skew often occurs between different clock buffers, often expressed as part to part skew. The delay of different clock buffer chips to the clock signal is different, usually reaching several hundred picoseconds, approaching nanosecond level, in order to realize the direct replacement of components and reduce the output deviation of the clock distribution system, the most important step is to eliminate the influence of part to part skew.
Disclosure of Invention
The embodiment of the invention provides a clock distribution system and a clock distribution method, which aim to solve the technical problem of inaccurate collected data caused by clock skew generated in the clock distribution process and realize the technical effect of reducing the output deviation of a clock distribution system.
In a first aspect, an embodiment of the present invention provides a clock distribution system, where the system includes: the clock source, at least one first clock buffer chip, at least one time delay unit, at least two second clock buffer chips, an offset measurement unit and a delay controller; wherein the content of the first and second substances,
the clock source is used for providing a clock signal;
the first clock buffer chip is connected with the clock source and used for fanning out a plurality of mutually independent first synchronous output signals from the clock signal and inputting the signals to the second clock buffer chip through the time delay unit;
the second clock buffer chip is used for fanning out the first synchronous output signal into a plurality of second synchronous output signals which are independent mutually;
the offset measuring unit is connected with at least one output channel in each second clock buffer chip and used for acquiring and comparing the clock phase of a second synchronous output signal output by each second clock buffer chip;
the delay controller is connected with the offset measuring unit and used for determining delay amount corresponding to each clock phase according to the comparison result of the offset measuring unit;
and the time delay unit is respectively connected with the delay controller, the first clock buffer chip and the second clock buffer chip and is used for adjusting the clock phase of the first synchronous output signal input to each second clock buffer chip according to the delay amount.
Further, the offset measurement unit is further configured to determine a sequence of the acquired clock phases;
and the delay controller is connected with the offset measuring unit and used for determining the delay amount of each time delay unit according to the sequence of each clock phase and the preset error range of each clock phase.
Furthermore, the time delay unit is further configured to adjust the clock phase input to each second clock buffer chip by a preset step length according to the delay amount.
Further, the offset measuring unit is further configured to determine a difference value between the obtained clock phases;
and the delay controller is connected with the offset measuring unit and used for determining the delay amount of each time delay unit according to the difference value of each clock phase.
Furthermore, the second clock buffer chip is also connected to the detector module, and is configured to fan out a plurality of mutually independent second synchronous output signals from the first synchronous output signal to be input to different detector modules as a reference clock.
Further, the wiring parameters between at least one output channel in each second clock buffer chip and the offset measurement unit are the same, wherein the wiring parameters include at least one of a wiring length, a routing type, a lamination type and a carrier material.
In a second aspect, an embodiment of the present invention further provides a clock distribution method, where the method includes:
the method comprises the steps that a clock signal output by a clock source is fanned out by a plurality of mutually independent first synchronous output signals through a first clock buffer chip and is input to a second clock buffer chip;
fanning out the first synchronous output signal into a plurality of mutually independent second synchronous output signals through a second clock buffer chip;
acquiring and comparing the clock phase of a second synchronous output signal output by at least one output channel in each second clock buffer chip through an offset measuring unit;
determining, by a delay controller, a delay amount corresponding to each clock phase according to a comparison result of the offset measurement unit;
and adjusting the clock phase of the first synchronous output signal input into each second clock buffer chip by the time delay unit according to the delay amount.
Further, the obtaining and comparing the clock phase of the second synchronous output signal output by at least one output channel in each second clock buffer chip by the offset measurement unit includes:
determining the sequence of the acquired clock phases through an offset measurement unit;
and determining the delay amount of each time delay unit through the delay controller according to the sequence of each clock phase and the preset error range of each clock phase.
Further, the determining, by the delay controller, the delay amount corresponding to each clock phase according to the comparison result of the offset measurement unit further includes:
and adjusting the clock phase input into each second clock buffer chip by a time delay unit according to the delay amount by a preset step length.
Further, the determining, by the delay controller, a delay amount corresponding to each clock phase according to the comparison result of the offset measurement unit further includes:
determining the obtained difference value of each clock phase through an offset measuring unit;
accordingly, determining, by a delay controller, a delay amount corresponding to each clock phase according to the comparison result of the offset measurement unit, includes
And determining the delay amount of each time delay unit according to the difference value of each clock phase through a delay controller.
According to the technical scheme of the embodiment of the invention, the clock signal of the clock source is fanned out into a plurality of mutually independent second synchronous output signals through the first clock buffer chip and the second clock buffer chip, namely, the clock signal of the same source is converted into a plurality of clock signals for distribution through two-stage distribution, then the clock phases of the acquired second synchronous output signals are compared through the offset measurement unit, further the delay controller determines the delay amount corresponding to each clock phase according to the comparison result of the offset measurement unit, and finally the clock phases of the first synchronous output signals input into each second clock buffer chip are adjusted through the time delay unit according to the delay amount, so that the technical problems that the clock distribution system generates clock offset and needs repeated manual correction and the like are solved, the output offset of the clock distribution system is reduced, the influence of the clock offset between the chips on the accuracy of acquired data is eliminated, and the technical effect of the existing clock distribution system is optimized.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, a brief description is given below of the drawings used in describing the embodiments. It is clear that the described figures are only figures of a part of the embodiments of the invention to be described, not all figures, and that for a person skilled in the art, without inventive effort, other figures can also be derived from them.
Fig. 1 is a schematic structural diagram of a clock distribution system according to an embodiment of the present invention;
fig. 2 is a schematic flowchart of a clock distribution system according to a second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 1 is a flowchart illustrating a schematic structural diagram of a clock distribution system according to an embodiment of the present invention. As shown in fig. 1, the clock distribution system in the present embodiment includes: a clock source 10, at least one first clock buffer chip, at least one time delay unit 60, at least two second clock buffer chips 30, an offset measurement unit 40, and a delay controller 50; the clock source 10 is used for providing a clock signal; the first clock buffer chip is connected with the clock source 10 and used for fanning out a plurality of mutually independent first synchronous output signals from the clock signal and inputting the signals to the second clock buffer chip 30 through the time delay unit 60; a second clock buffer chip 30 for fanning out the first synchronous output signal into a plurality of mutually independent second synchronous output signals; an offset measuring unit 40, connected to at least one output channel of each second clock buffer chip 30, for obtaining and comparing clock phases of second synchronous output signals output by the second clock buffer chips 30; a delay controller 50 connected to the offset measuring unit 40, for determining a delay amount corresponding to each clock phase according to a comparison result of the offset measuring unit 40; the time delay unit 60 is connected to the first delay controller 50, the first clock buffer chip, and the second clock buffer chip 30, respectively, and is configured to adjust a clock phase of the first synchronous output signal input to each second clock buffer chip 30 according to the delay amount.
Wherein, the clock source 10 is preferably a clock source 10 with low jitter and high accuracy. The buffer chip first clock buffer chip 20 and the buffer chip second clock buffer chip 30 are preferably clock buffer chip buffers with low skew and low additional jitter, and the output channels in the chips have low skew levels. The time delay unit 60 may be a programmable time delay unit 60, preferably a programmable time delay unit 60 with a high accuracy of time adjustment. For example, programmable time delay unit 60 may achieve delay accuracies of 10ps and within 10 ps.
The clock distribution system in the embodiment of the present invention may include two or more buffer chips and the second clock buffer chip 30. Further, each buffer chip second clock buffer chip 30 has a plurality of fan-out channels, for example, each buffer chip second clock buffer chip 30 may include one input channel and eight output channels. Preferably, each buffer chip second clock buffer chip 30 has a smaller on-chip output offset. Any one of the output channels of the buffer chip second clock buffer chip 30 may be connected as a feedback branch to the input port of the offset measurement unit 40. Each of the buffer chips the second clock buffer chip 30 has an output channel connected as a feedback branch to the offset measuring unit 40.
It should be noted that the first clock buffer chip may be the same as or different from the second clock buffer chip 30. For example, the buffer chip the first clock buffer chip 20 may include one input channel and four output channels.
In order to reduce the influence of the difference of the feedback branches on the clock offset, it is preferable that the clock phases of the feedback branches are delayed by equal amounts. Specifically, the wiring parameters of the feedback branches may be the same. That is, the wiring parameters between the output channels in each second clock buffer chip 30 and the offset measurement unit 40 are the same. The wiring parameters comprise at least one of wiring length, wiring type, lamination type and carrier material. Taking the implementation on a printed circuit board PCB as an example, the wiring parameters to be controlled include: the PCB routing length, the lamination type, the PCB material type and the like are used for ensuring that the clock delay quantity of each feedback branch is equal.
Optionally, the offset measurement unit 40 may be configured to determine a sequence of the acquired clock phases; and the delay controller 50 is connected with the offset measuring unit 40 and is used for determining the delay amount of each time delay unit 60 according to the sequence of each clock phase and the preset error range of each clock phase.
Alternatively, the offset measurement unit 40 may be further configured to determine a difference value between the acquired clock phases; and the delay controller 50 is connected with the offset measuring unit 40 and used for determining the delay amount of each time delay unit 60 according to the difference value of each clock phase.
Exemplarily, the offset measuring unit 40 may be implemented by a Time Digital Converter (TDC). Alternatively, the TDC unit may be implemented by a carry chain of a Field-Programmable Gate Array (FPGA). At this time, the TDC can be optionally calibrated, and further, the signal input port can be subjected to wiring constraint, so that the advantage of the arrangement is that the extra delay offset measurement unit 40 of the signal caused by the internal routing of the FPGA can be effectively avoided. .
The delay controller 50 can adjust the delay amount of the time delay unit 60 in front of the second clock buffer chip 30 of each buffer chip according to the measurement result of the offset measurement unit 40 to compensate the delay difference of the second clock buffer chip 30 of the buffer chip, thereby achieving the purpose of reducing the output offset between different chips.
On this basis, the time delay unit 60 is also configured to adjust the phase of the clock input to each second clock buffer chip 30 by a preset step size according to the delay amount. For example, the clock phase output by one second clock buffer chip 30 may be used as a reference, and the clock phases output by the remaining second clock buffer chips 30 may be adjusted. The adjustment is performed by 10ps each time until the clock skew outputted by each second clock buffer chip 30 is within a preset range, wherein the adjustment includes advancing or delaying.
On the basis of the above technical solutions, the second clock buffer chip 30 may further be connected to the detector module, and configured to fan out a plurality of mutually independent second synchronous output signals from the first synchronous output signal to be input to different detector modules as a reference clock.
Through the adjustment of the delay amount feedback control in the clock distribution system, the clock phase difference output by each second clock buffer chip 30 can be controlled to the level of the internal offset of a single chip, and can reach the level of less than 45 picoseconds, even can reach the level of 15 picoseconds, and the delay difference of hundreds of picoseconds between chips can be eliminated.
According to the technical scheme of the embodiment of the invention, the clock signal of the clock source is fanned out into a plurality of mutually independent second synchronous output signals through the first clock buffer chip and the second clock buffer chip, namely, the clock signal of the same source is converted into a plurality of clock signals for distribution through two-stage distribution, then the clock phases of the acquired clock signals and the second synchronous output signals are compared through the offset measuring unit, further, the delay controller determines the delay quantity corresponding to each clock phase according to the comparison result of the offset measuring unit, and finally, the clock phases input into the second clock buffer chips are adjusted through the time delay unit according to the delay quantity, so that the technical problems that the clock distribution system generates clock offset and needs repeated manual correction and the like are solved, the output offset of the clock distribution system is reduced, the influence of the clock offset between the chips on the accuracy of acquired data is eliminated, and the technical effect of the existing clock distribution system is optimized.
Of course, in the clock distribution system, in order to meet the requirement of multiple channels, a third clock buffer chip may be further included, and further, the third clock buffer chip may be further connected to the detector module, and configured to fan out a second synchronous output signal to multiple mutually independent third synchronous output signals, and input the third synchronous output signals to different detector modules as a reference clock. Furthermore, a time delay unit may be further disposed on the second clock buffer chip and the third clock buffer chip, and the time delay unit is connected to the offset measurement unit, so as to adjust the clock signal input to the third clock buffer chip by the clock distribution method mentioned in the above technical solution. Therefore, all the schemes of adjusting the clock signal by using the offset measurement unit and the clock delay unit of the embodiments of the present invention are within the scope of the present invention.
It should be noted that the detector modules may be detector units sharing the same reference clock. Taking a PET system as an example, in the PET system, a plurality of detector modules form a PET detector ring, and each PET detector module has a reference clock. Therefore, each detector module can be respectively connected with different second clock buffer chips.
It is to be understood that "first", "second", and "third" of "first clock buffer chip", "second clock buffer chip", and "third clock buffer chip" in the embodiments of the present invention are merely clock buffer chips for distinguishing different levels, and are not limited.
Example two
Fig. 2 is a flowchart illustrating a clock distribution method according to a second embodiment of the present invention. The method is particularly suitable for the case where the clock skew generated in the clock distribution process needs to be adjusted, and can be performed by the clock distribution system provided by the embodiment of the present invention, and the system can be implemented by software and/or hardware.
As shown in fig. 2, the method of this embodiment specifically includes:
s210, fanning out a plurality of mutually independent first synchronous output signals from a clock signal output by a clock source through a first clock buffer chip and inputting the signals to a second clock buffer chip.
As mentioned before, the clock source is preferably a low jitter high accuracy clock source. The first clock buffer chip and the second clock buffer chip are preferably clock buffer chips with low offset and low additional jitter, and the output channels in the chips have low offset levels.
S220, fanning out the first synchronous output signal into a plurality of mutually independent second synchronous output signals through the second clock buffer chip.
And S230, acquiring and comparing the clock phase of the second synchronous output signal output by at least one output channel in each second clock buffer chip through the offset measuring unit.
Optionally, the comparing the clock phase of the second synchronous output signal output by at least one output channel in each second clock buffer chip may be determining the sequence of the acquired clock phases by using an offset measurement unit. In particular, the offset measurement unit may be configured to compare the clock phases output between different second clock buffer chips, i.e. a measure of the chip-to-chip offset. The offset measurement unit may not necessarily give accurate delay difference data, but may need to be able to compare the precedence of two or more clock phases with a higher accuracy. For example, assuming that the clock CH1 is 20ps ahead of the clock CH2, the offset measurement unit does not need to give a measurement result of 20ps, and determines that the result is "clock CH1 is 20ps ahead of clock CH 2".
In addition, the difference value of the acquired clock phases may be determined by the offset measurement unit. Optionally, the clock phase of any one of the second clock buffer chips is used as a reference clock phase, and a difference value between the clock phase of the other second clock buffer chips and the reference clock phase is calculated.
And S240, determining delay amount corresponding to each clock phase according to the comparison result of the offset measuring unit through a delay controller.
For example, the delay amount of each time delay unit may be determined by the delay controller according to the sequence of each clock phase and a preset error range of each clock phase. Specifically, the clock phase of any one of the second clock buffer chips may be used as a target clock phase, and the delay amount of each time delay unit is determined when the difference value between the clock phase to be adjusted and the target clock phase is within the error range according to the sequence between the clock phase to be adjusted and the target clock phase of the remaining second clock buffer chips.
Alternatively, the delay controller may determine the delay amount of each time delay unit according to the difference value of each clock phase. Specifically, the clock phase of any one of the second clock buffer chips may be set as a target clock phase, a difference between the clock phase of the remaining second clock buffer chips and the target clock phase may be calculated, and the difference corresponding to the second clock buffer chip may be set as the delay amount of each time delay unit corresponding to each second clock buffer chip.
And S250, adjusting the clock phase of the first synchronous output signal input into each second clock buffer chip through the time delay unit according to the delay amount.
For example, the clock phase of one of the second clock buffer chips may be used as a target clock phase, and the clock phases corresponding to the remaining second clock buffer chips may be adjusted to the target constant phase.
Specifically, the clock phase input to each second clock buffer chip may be adjusted by a time delay unit in a preset step according to the delay amount. The specific value of the preset step length may be set according to an actual situation, and is not limited herein. For example, the preset step size may be 10 picoseconds, 5 picoseconds, or 2 picoseconds, etc. Of course, the difference value of the clock phases may be directly used as the delay amount of the time delay unit.
The clock distribution system can execute the clock distribution method provided by any embodiment of the invention, and has corresponding functional modules and beneficial effects for executing the clock distribution method. For details of the clock distribution method provided in any embodiment of the present invention, reference may be made to the technical details not described in detail in this embodiment.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments illustrated herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. A clock distribution system, comprising: the clock source, at least one first clock buffer chip, at least one time delay unit, at least two second clock buffer chips, an offset measurement unit and a delay controller; wherein the content of the first and second substances,
a clock source for providing a clock signal;
the first clock buffer chip is connected with the clock source and used for fanning out a plurality of mutually independent first synchronous output signals from the clock signal and inputting the signals to the second clock buffer chip through the time delay unit;
the second clock buffer chip is used for fanning out the first synchronous output signal into a plurality of mutually independent second synchronous output signals;
the offset measuring unit is connected with at least one output channel in each second clock buffer chip in a connecting mode and used for acquiring and comparing the clock phase of the second synchronous output signal output by each second clock buffer chip;
the delay controller is connected with the offset measuring unit and used for determining delay amount corresponding to each clock phase according to the comparison result of the offset measuring unit;
the time delay unit is respectively connected with the delay controller, the first clock buffer chip and the second clock buffer chip and is used for adjusting the clock phase of the first synchronous output signal input to each second clock buffer chip according to the delay amount;
the offset measuring unit is also used for determining the sequence of the acquired clock phases;
and the delay controller is connected with the offset measuring unit and used for determining the delay amount of each time delay unit according to the sequence of each clock phase and the preset error range of each clock phase.
2. The system of claim 1, wherein:
the time delay unit is further used for adjusting the clock phase input into each second clock buffer chip by a preset step length according to the delay amount.
3. The system of claim 1, wherein:
the offset measuring unit is also used for determining the difference value of each acquired clock phase;
and the delay controller is connected with the offset measuring unit and used for determining the delay amount of each time delay unit according to the difference value of each clock phase.
4. The system of claim 1, wherein the second clock buffer chip is further coupled to the detector modules for fanning out the first synchronized output signal into a plurality of independent second synchronized output signals for input to different detector modules as a reference clock.
5. The system of claim 1, wherein: and the wiring parameters between at least one output channel in each second clock buffer chip and the offset measuring unit are the same, wherein the wiring parameters comprise at least one of wiring length, wiring type, lamination type and carrier material.
6. A method for clock distribution, comprising:
the method comprises the steps that a clock signal output by a clock source is fanned out by a plurality of mutually independent first synchronous output signals through a first clock buffer chip and is input to a second clock buffer chip;
fanning out the first synchronous output signal into a plurality of mutually independent second synchronous output signals through a second clock buffer chip;
obtaining and comparing the clock phase of a second synchronous output signal output by at least one output channel in each second clock buffer chip through an offset measuring unit;
determining, by a delay controller, a delay amount corresponding to each clock phase according to a comparison result of the offset measurement unit;
adjusting the clock phase of the first synchronous output signal input into each second clock buffer chip through the time delay unit according to the delay amount;
the obtaining and comparing the clock phase of the second synchronous output signal output by at least one output channel in each second clock buffer chip by the offset measurement unit comprises:
determining the sequence of the acquired clock phases through an offset measurement unit;
and determining the delay amount of each time delay unit through the delay controller according to the sequence of each clock phase and the preset error range of each clock phase.
7. The method of claim 6, wherein determining, by the delay controller, the delay amount corresponding to each clock phase from the comparison of the offset measurement units comprises:
and adjusting the clock phase input into each second clock buffer chip by a time delay unit according to the delay amount by a preset step length.
8. The method of claim 6, wherein determining, by the delay controller, the delay amount corresponding to each clock phase from the comparison of the offset measurement units further comprises:
determining the obtained difference value of each clock phase through an offset measuring unit;
accordingly, determining, by a delay controller, a delay amount corresponding to each clock phase according to a comparison result of the offset measurement unit includes:
and determining the delay amount of each time delay unit according to the difference value of each clock phase through a delay controller.
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| EP3959814A4 (en) | 2019-05-29 | 2022-06-15 | Shanghai United Imaging Healthcare Co., Ltd. | Systems and methods for clock synchronization |
| CN111466936B (en) * | 2020-03-31 | 2021-07-16 | 上海联影医疗科技股份有限公司 | Clock synchronization method and device and computer equipment |
| CN112257379B (en) * | 2020-10-30 | 2023-04-25 | 上海兆芯集成电路有限公司 | Circuit clock delay correction method |
| CN112737573A (en) * | 2020-12-21 | 2021-04-30 | 南京极景微半导体有限公司 | Clock skew calibration system, method and equipment based on daisy chain and computer storage medium |
| CN114640327B (en) * | 2022-05-11 | 2022-09-27 | 上海燧原科技有限公司 | Clock phase control circuit and chip |
| CN114815965B (en) * | 2022-06-29 | 2022-09-20 | 中星联华科技（北京）有限公司 | Clock signal generating and synchronizing method and device |
| CN116418321B (en) * | 2023-03-28 | 2024-03-19 | 成都电科星拓科技有限公司 | Method and circuit for automatically adjusting multiple paths of clocks to keep output delay equal in power-on |
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