CN215266282U - Packaging structure of power semiconductor device - Google Patents
Packaging structure of power semiconductor device Download PDFInfo
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- CN215266282U CN215266282U CN202120763876.7U CN202120763876U CN215266282U CN 215266282 U CN215266282 U CN 215266282U CN 202120763876 U CN202120763876 U CN 202120763876U CN 215266282 U CN215266282 U CN 215266282U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
A packaging structure of a power semiconductor device comprises a lead frame, a plastic package body, a first semiconductor chip, a first pin and a second pin, wherein the back surface of the first semiconductor chip is welded on the lead frame, and the front surface of the first semiconductor chip is electrically connected with a first welding area of the first pin and a second welding area of the second pin through bonding wires; the first semiconductor chip, the bonding wire, the first welding area and the second welding area are packaged on the lead frame through the plastic package body; the first side of the plastic package body is provided with and only extends out of the first leading-out area and the second leading-out area. Therefore, the first lead-out area, the second lead-out area and the lead frame can be arranged at a large enough interval to ensure that the first lead-out area, the second lead-out area and the lead frame are not in short circuit, so that the packaging structure is suitable for packaging of power semiconductors with higher voltage levels, and meanwhile, the surface mounting technology can be used for automatic mounting.
Description
Technical Field
The utility model relates to an packaging structure technical field, concretely relates to power semiconductor device's packaging structure.
Background
The power semiconductor device is mainly used for power supplies and driving loads of various devices, and a general power electronic system needs the power supplies to provide energy for the power electronic system and needs to push loads (motors, relays and the like) to execute processing results, so the power semiconductor device is indispensable for the power electronic system, the application of the power semiconductor device is spread in various industries, and along with the update and the replacement of the power semiconductor device, besides the application field of extra-large power is still governed by thyristors and the like, the power device represented by the Insulated Gate Bipolar Transistor (IGBT) has already occupied a leading position. An IGBT is a voltage-driven three-terminal device that includes a gate, an emitter, and a collector, where the gate and emitter are typically located on the front side of the chip, and the collector is typically located on the back side of the chip.
For the IGBT device, the existing conventional package architecture is still basically used at present, taking the TO-263 conventional package structure as an example, the collector of the IGBT is welded on the base island of the lead frame by soft solder, the gate is connected TO the first pin of the lead frame by an aluminum wire, and the emitter is connected TO the third pin of the lead frame by an aluminum wire. In the conventional structure, a second pin connected to the base island is disposed between the first pin and the third pin, that is, three pins are disposed on the same side of the lead frame, so that the space between two adjacent pins is limited. For a three-terminal active device such as an IGBT, the larger the voltage between the third pin and the second pin is, the more likely a breakdown short circuit is caused between the third pin and the second pin. This results in a TO-263 package that is only suitable for low power drive systems of 220V voltage class, but is difficult TO use for higher voltage class low power drive systems, such as 380V and 480V voltage class power drive systems. It is an object of the present application TO improve the TO-263 package structure TO obtain a package structure suitable for higher voltage class power semiconductors while retaining the advantage of the TO-263 package structure that can be automatically mounted using Surface Mount Technology (SMT).
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem that a packaging structure of power semiconductor device is provided, packaging structure is applicable to the power semiconductor's of higher voltage level encapsulation, and available surface mounting technology carries out automatic subsides simultaneously.
In order to solve the above technical problem, the technical solution adopted by the utility model is to provide a package structure of a power semiconductor device, the package structure includes a lead frame, a plastic package body and a first semiconductor chip, the package structure further includes a first pin and a second pin, the first pin includes a first welding area and a first lead-out area which are connected, the second pin includes a second welding area and a second lead-out area which are connected; the back surface of the first semiconductor chip is welded on the lead frame, and the front surface of the first semiconductor chip is electrically connected with the first welding area of the first pin and the second welding area of the second pin through bonding wires respectively; the first semiconductor chip, the bonding wire, the first welding area and the second welding area are packaged on the lead frame through the plastic package body; the first leading-out area and the second leading-out area are exposed at the first side of the plastic package body, and only the first leading-out area and the second leading-out area extend out of the first side of the plastic package body.
In the utility model provides an in power semiconductor device's packaging structure, the quantity of first semiconductor chip is a plurality of.
The utility model provides an among the packaging structure of power semiconductor device, packaging structure still includes and passes through the plastic-sealed body encapsulate in second semiconductor chip in the lead frame, the back welding of second semiconductor chip on the lead frame, openly through the bonding wire with the first weld zone electric connection of first pin.
The utility model provides an in power semiconductor device's packaging structure, the quantity of second semiconductor chip is a plurality of.
The utility model provides an among the packaging structure of power semiconductor device, the width of first weld zone is greater than the width of second weld zone, first drawing zone includes certainly keeping away from of first weld zone first section of drawing out that one side of second pin is extended with certainly being close to of first weld zone the section is drawn out to the second that one side of second pin is extended.
The utility model provides an among the packaging structure of power semiconductor device, the packaging form that packaging structure is suitable for is TO-263, first draw forth the district first draw forth the size of section and second draw forth the section and be unanimous with the size of the three pin in the standard TO-263 packaging structure respectively.
The utility model provides an among the packaging structure of power semiconductor device, packaging structure still including direct with the third pin that the lead frame is connected, the complete cladding of plastic-sealed body the third pin.
The utility model provides an among the packaging structure of power semiconductor device, the lead frame with the relative one side in first side of plastic-sealed body is equipped with the angle of opening.
In the package structure of the power semiconductor device provided by the present invention, the first semiconductor chip is a three-terminal active device, the front side of the first semiconductor chip has an output terminal and a control terminal, and the back side of the first semiconductor chip has an input terminal; the input end is welded with the lead frame, the output end is electrically connected to a first welding area of the first pin through a bonding wire, and the control end is electrically connected to a second welding area of the second pin through the bonding wire; the second semiconductor chip is a two-terminal active device, the front surface of the second semiconductor chip is provided with an output terminal, and the back surface of the first semiconductor chip is provided with an input terminal; the input end is welded with the lead frame, and the output end is electrically connected to the first welding area of the first pin through a bonding wire.
The utility model provides an among the packaging structure of power semiconductor device, the plastic-sealed body is made by epoxy plastic packaging material, the lead frame is made by copper alloy material, the bonding wire is made by copper line, gold thread, aluminium wire or alloy line.
The utility model discloses still relate to a power module, it includes the base plate and has as above power semiconductor device's packaging structure's power semiconductor device, power semiconductor device paste adorn in on the base plate.
Implement the utility model discloses a power semiconductor device's packaging structure can reach following beneficial effect at least: the packaging structure comprises a lead frame, a plastic package body and a first semiconductor chip, and further comprises a first pin and a second pin, wherein the first pin comprises a first welding area and a first leading-out area which are connected, and the second pin comprises a second welding area and a second leading-out area which are connected; the back surface of the first semiconductor chip is welded on the lead frame, and the front surface of the first semiconductor chip is electrically connected with the first welding area of the first pin and the second welding area of the second pin through bonding wires respectively; the first semiconductor chip, the bonding wire, the first welding area and the second welding area are packaged on the lead frame through the plastic package body; the first leading-out area and the second leading-out area are exposed at the first side of the plastic package body, and only the first leading-out area and the second leading-out area extend out of the first side of the plastic package body. Therefore, a large enough interval can be formed between the first lead-out area and the second lead-out area which are positioned on the same side of the plastic package body, and the phenomenon of breakdown short circuit between the first lead-out area and the second lead-out area is avoided. Therefore, the packaging structure can be suitable for packaging the power semiconductor with higher voltage grade, and can be automatically mounted by a surface mounting process.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts:
fig. 1 is a schematic top view of a package structure according to an embodiment;
FIG. 2 is a cross-sectional view of a package structure according to an embodiment;
fig. 3 is a schematic perspective view of a package structure according to an embodiment;
fig. 4 is a schematic top view of a package structure provided in the second embodiment;
fig. 5 is a cross-sectional view of a package structure according to the second embodiment;
fig. 6 is a schematic perspective view of a package structure according to a second embodiment;
fig. 7 is a schematic top view of a package structure provided in the third embodiment;
fig. 8 is a cross-sectional view of a package structure provided in the third embodiment;
fig. 9 is a schematic perspective view of a package structure according to a third embodiment.
The reference numerals in the detailed description illustrate:
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1 | |
2 |
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3 | |
4 |
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6 | |
5 |
| First welding area | 61 | A first lead-out |
62 |
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51 | Second lead-out |
52 |
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7 | |
8 |
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11 | First lead-out |
621 |
| Second lead-out |
622 |
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Exemplary embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Example one
The embodiment provides a packaging structure of a power semiconductor device. Referring to fig. 1, fig. 1 is a schematic top view of the package structure provided in this embodiment, in which a plastic package body 2 is processed in a perspective manner. As shown in fig. 1, the package structure includes a lead frame 1, a plastic package body 2, a first semiconductor chip 3, a second semiconductor chip 4, a first lead 6 and a second lead 5. The first lead 6 includes a first land 61 and a first lead-out region 62 connected thereto, and the second lead 5 includes a second land 51 and a second lead-out region 52 connected thereto. The back surface of the first semiconductor chip 3 is soldered on the lead frame 1, and the front surface of the first semiconductor chip 3 is electrically connected to the first bonding pad 61 of the first lead 6 and the second bonding pad 51 of the second lead 5 through the bonding wire 8. Here, the first semiconductor chip 3 is a three-terminal active device, the front surface of the first semiconductor chip 3 has an output terminal and a control terminal, and the back surface of the first semiconductor chip 3 has an input terminal; the input terminal is soldered to the lead frame 1, the output terminal is electrically connected to the first bonding region 61 of the first lead 6 through a bonding wire 8, and the control terminal is electrically connected to the second bonding region 51 of the second lead 5 through the bonding wire 8. The back surface of the second semiconductor chip 4 is soldered on the lead frame 1, and the front surface is electrically connected with the first bonding area 61 of the first pin 6 through a bonding wire 8. Here, the second semiconductor chip 4 is a two-terminal active device, the front surface of the second semiconductor chip 4 has an output terminal, and the back surface of the first semiconductor chip 3 has an input terminal; the input terminal is soldered to the lead frame 1, and the output terminal is electrically connected to the first bonding area 61 of the first lead 6 through a bonding wire 8. Referring to fig. 2, fig. 2 is a cross-sectional view of the package structure provided in this embodiment, and as shown in fig. 2, the first semiconductor chip 3, the second semiconductor chip 4, the bonding wire 8, the first bonding pad 61, and the second bonding pad 51 are packaged in the lead frame 1 through the plastic package body 2. Referring to fig. 3, fig. 3 is a schematic perspective view of the package structure provided in this embodiment, as shown in fig. 3, the first lead-out region 62 and the second lead-out region 52 are exposed at the first side of the plastic package body 2, and most importantly, only the first lead-out region 62 and the second lead-out region 52 extend from the first side of the plastic package body 2.
In this embodiment, the package structure is in the form of a TO-263 package.
In this embodiment, referring to fig. 1, a corner 11 is disposed on a side of the lead frame 1 opposite to the first side of the plastic package body 2. The plastic package body 2 is made of epoxy plastic package materials, the lead frame 1 is made of copper alloy materials, and the bonding wire 8 is made of copper wires.
In summary, only the first lead-out region 62 and the second lead-out region 52 extend out from the first side of the plastic package body 2, so that a sufficiently wide space can be configured between the first lead-out region 62 and the second lead-out region 52, and a short circuit phenomenon caused by breakdown does not occur between the first lead-out region 62 and the second lead-out region 52. Therefore, the packaging structure can be suitable for packaging the power semiconductor with higher voltage (less than or equal to 1500V) grade. Meanwhile, the packaging structure is in a TO-263 packaging form, so that the packaging structure can be automatically mounted by using a surface mounting process.
In some other embodiments, the number of the first semiconductor chips 3 and the second semiconductor chips 4 is not limited to 1, and may be more, for example, 2, 3, 4, and the like.
In some other embodiments, the package structure may not include the second semiconductor chip 4.
In some other embodiments, the bonding wires 8 are made of gold wires, aluminum wires, or alloy wires.
Example two
The embodiment provides a packaging structure of a power semiconductor device. Compared with the first embodiment, the difference of the package structure provided by this embodiment is that the structure of the first lead 6 is different. Referring to fig. 4 and fig. 5, fig. 4 is a schematic top view of the package structure provided in the present embodiment, in which a plastic package body 2 is processed in a perspective manner, and fig. 5 is a cross-sectional view of the package structure provided in the present embodiment. As shown in fig. 4 and 5, the first land 61 extends horizontally to one side of the second land 51 such that the width of the first land 61 is greater than the width of the second land 51. Referring to fig. 4 and 6, fig. 6 is a schematic perspective view of the package structure provided in this embodiment, and as shown in fig. 4 and 6, the first lead-out region 62 includes a first lead-out section 621 extending from a side of the first bonding region 61 away from the second pin 5 and a second lead-out section 622 extending from a side of the first bonding region 61 close to the second pin 5. Here, the sizes of the first lead-out region 62, the first lead-out section 621 and the second lead-out section 622 correspond TO the sizes of three pins in a standard TO-263 package structure, respectively. For example, taking an IGBT package as an example, comparing the package structure adopting the present embodiment with a TO-263 package structure, the dimensions of the first lead-out region 62, the first lead-out section 621, and the second lead-out section 622 in the package structure of the present embodiment are the same as the dimensions of the first pin connected TO the gate, the second pin connected TO the collector, and the third pin connected TO the emitter in the TO-263 package structure, respectively. Thus, the package structure of the present embodiment can be consistent with the TO-263 package structure in terms of the outline structure. In addition, the overcurrent capacity of the power semiconductor device, particularly the surface mount device which conducts electricity with the back side heat sink, is mainly determined by the overcurrent capacity of the third pin connected to the emitter, and the overcurrent capacity of the third pin is determined by the width of the third pin and the bonding area of the chip and the third pin. In this embodiment, the first land 61 of the first lead 6 corresponding to the third pin is widened by extending horizontally toward one side of the second land 51, so that the number and the wire diameter of the metal bonding wires 8 that can be bonded by the first land 61 are increased, thereby improving the overcurrent capability of the whole package structure.
EXAMPLE III
The embodiment provides a packaging structure of a power semiconductor device. Compared with the first embodiment, the difference of the package structure provided in this embodiment is that the package structure further includes a third lead 7. Referring to fig. 7, fig. 7 is a schematic top view of the package structure provided in the present embodiment, in which a plastic package body 2 is processed in a perspective manner. As shown in fig. 7, the package structure further includes a third lead 7, and the third lead 7 is disposed between the first lead 6 and the second lead 5. Referring to fig. 8, fig. 8 is a cross-sectional view of the package structure provided in this embodiment, and as shown in fig. 8, the third lead 7 is directly connected to the lead frame 1. Referring to fig. 9, fig. 9 is a schematic perspective view of the package structure provided in this embodiment, and the plastic package body 2 completely covers the third pin 7.
The embodiments of the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, which are only illustrative and not restrictive, and those skilled in the art can make many forms without departing from the spirit and scope of the present invention, which is protected by the following claims.
Claims (11)
1. The packaging structure of the power semiconductor device comprises a lead frame, a plastic package body and a first semiconductor chip, and is characterized by further comprising a first pin and a second pin, wherein the first pin comprises a first welding area and a first leading-out area which are connected, and the second pin comprises a second welding area and a second leading-out area which are connected; the back surface of the first semiconductor chip is welded on the lead frame, and the front surface of the first semiconductor chip is electrically connected with the first welding area of the first pin and the second welding area of the second pin through bonding wires respectively; the first semiconductor chip, the bonding wire, the first welding area and the second welding area are packaged on the lead frame through the plastic package body; the first leading-out area and the second leading-out area are exposed at the first side of the plastic package body, and only the first leading-out area and the second leading-out area extend out of the first side of the plastic package body.
2. The package structure of a power semiconductor device according to claim 1, wherein the number of the first semiconductor chips is plural.
3. The package structure of the power semiconductor device as claimed in claim 1, further comprising a second semiconductor chip packaged in the lead frame by the molding compound, wherein the second semiconductor chip is soldered on the lead frame at a back surface and electrically connected to the first bonding area of the first lead at a front surface by a bonding wire.
4. The package structure of a power semiconductor device according to claim 3, wherein the number of the second semiconductor chips is plural.
5. The package structure of the power semiconductor device according to claim 3, wherein the first semiconductor chip is a three-terminal active device, the front side of the first semiconductor chip has an output terminal and a control terminal, and the back side of the first semiconductor chip has an input terminal; the input end is welded with the lead frame, the output end is electrically connected to a first welding area of the first pin through a bonding wire, and the control end is electrically connected to a second welding area of the second pin through the bonding wire; the second semiconductor chip is a two-terminal active device, the front surface of the second semiconductor chip is provided with an output terminal, and the back surface of the first semiconductor chip is provided with an input terminal; the input end is welded with the lead frame, and the output end is electrically connected to the first welding area of the first pin through a bonding wire.
6. The package structure of a power semiconductor device according to claim 1, wherein a width of the first land is larger than a width of the second land, and the first lead-out region includes a first lead-out section extending from a side of the first land away from the second pin and a second lead-out section extending from a side of the first land near the second pin.
7. The package structure of the power semiconductor device as claimed in claim 6, wherein the package structure is adapted TO a package form of TO-263, and the sizes of the first lead-out region, the first lead-out section and the second lead-out section are respectively consistent with the sizes of three pins in a standard TO-263 package structure.
8. The package structure of the power semiconductor device according to claim 1, further comprising a third lead directly connected to the lead frame, wherein the plastic package body completely covers the third lead.
9. The package structure of the power semiconductor device as claimed in claim 1, wherein a corner is formed on a side of the lead frame opposite to the first side of the plastic package body.
10. The package structure of a power semiconductor device according to claim 1, wherein the plastic package body is made of an epoxy plastic package material, the lead frame is made of a copper alloy material, and the bonding wire is made of a copper wire, a gold wire, an aluminum wire or an alloy wire.
11. A power module comprising a substrate and a power semiconductor device having a package structure of the power semiconductor device according to any one of claims 1 to 10, the power semiconductor device being mounted on the substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120763876.7U CN215266282U (en) | 2021-04-14 | 2021-04-14 | Packaging structure of power semiconductor device |
| PCT/CN2022/076935 WO2022218031A1 (en) | 2021-04-14 | 2022-02-18 | Packaging structure for power semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120763876.7U CN215266282U (en) | 2021-04-14 | 2021-04-14 | Packaging structure of power semiconductor device |
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| CN215266282U true CN215266282U (en) | 2021-12-21 |
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| WO (1) | WO2022218031A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2022218031A1 (en) * | 2021-04-14 | 2022-10-20 | 苏州汇川技术有限公司 | Packaging structure for power semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101174602B (en) * | 2006-10-06 | 2011-10-05 | 万国半导体股份有限公司 | Small shape ic package for high-current semiconductor power device |
| JP2009071059A (en) * | 2007-09-13 | 2009-04-02 | Sanyo Electric Co Ltd | Semiconductor device |
| CN104766843B (en) * | 2015-04-24 | 2017-10-10 | 南京晟芯半导体有限公司 | A kind of high power semiconductor encapsulating structure mounted with SMT techniques |
| US9397029B1 (en) * | 2015-06-29 | 2016-07-19 | Alpha And Omega Semiconductor Incorporated | Power semiconductor package device having locking mechanism, and preparation method thereof |
| CN109727943A (en) * | 2019-02-27 | 2019-05-07 | 无锡新洁能股份有限公司 | A kind of package structure of semiconductor device and its manufacturing method with low thermal resistance |
| CN110164832A (en) * | 2019-05-31 | 2019-08-23 | 无锡电基集成科技有限公司 | High-current semiconductor power device |
| CN215266282U (en) * | 2021-04-14 | 2021-12-21 | 苏州汇川技术有限公司 | Packaging structure of power semiconductor device |
| CN214505484U (en) * | 2021-05-07 | 2021-10-26 | 苏州汇川技术有限公司 | Packaging structure of power semiconductor device and power module |
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- 2021-04-14 CN CN202120763876.7U patent/CN215266282U/en active Active
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022218031A1 (en) * | 2021-04-14 | 2022-10-20 | 苏州汇川技术有限公司 | Packaging structure for power semiconductor device |
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