CN215731660U

CN215731660U - Paster element, paster MOSFET and paster IGBT

Info

Publication number: CN215731660U
Application number: CN202120353539.0U
Authority: CN
Inventors: 周昕; 张景超; 赵善麒
Original assignee: Macmic Science & Technology Holding Co ltd
Current assignee: Macmic Science & Technology Holding Co ltd
Priority date: 2021-02-08
Filing date: 2021-02-08
Publication date: 2022-02-01
Anticipated expiration: 2031-02-08

Abstract

The utility model relates to the field of power device packaging, and particularly discloses a chip element, a chip MOSFET and a chip IGBT, which comprise a packaging body and a metal pin group, wherein the packaging body and a heat dissipation metal sheet form a containing space, a chip unit is arranged in the containing space and connected with the heat dissipation metal sheet, one surface of the packaging body is provided with two metal pins which are configured into a first metal pin and a third metal pin, the first metal pin and the third metal pin are respectively connected with the chip unit, and the heat dissipation metal sheet is configured into a second metal pin. The yield of the product is improved.

Description

Paster element, paster MOSFET and paster IGBT

Technical Field

The utility model relates to the field of power device packaging, in particular to a patch element, a patch MOSFET and a patch IGBT.

Background

An Insulated Gate Bipolar Transistor (IGBT for short) is a composite fully-controlled voltage-driven power semiconductor device composed of BJT (Bipolar Transistor) and MOS (Insulated Gate field effect Transistor), and has the advantages of both high input impedance of MOSFET and low on-state voltage drop of GTR (power Transistor). The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is large; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT integrates the advantages of the two devices, and has small driving power and reduced saturation voltage; the IGBT is a core device for energy conversion and transmission, is commonly called as a CPU of a power electronic device, and is widely applied in the fields of rail transit, smart power grids, aerospace, electric automobiles, new energy equipment and the like.

The IGBT single tube is one of series of IGBT products and plays an important role in the fields of photovoltaic inverters, welding machines and the like all the time, the traditional IGBT single tube packaging mode mainly adopts plug-in type packaging of TO-220, TO-3P, TO-247 and the like, and the IGBT single tube packaging method has the advantages that the product is simple TO install and replace; with the development of miniaturization and lightness and thinness of electronic equipment products, the traditional IGBT single tube is difficult to meet the requirements due to large volume, and has to be developed to a surface mount type package with smaller volume; the existing patch type IGBT (such as the patent application number "CN 201922294673.3", named as a patch type IGBT chip ") is provided with three Z-shaped metal pins which are arranged in parallel, and the pins are easily connected with each other to form a short circuit due to the growth of electroplated layer tin whisker or foreign matters in the using process.

SUMMERY OF THE UTILITY MODEL

The utility model provides a novel patch element, aiming at solving the problem that in the prior art, three parallel Z-shaped metal pins are arranged on the patch element, and the pins are easily connected with each other to form a short circuit due to the growth of electroplated layer tin whisker or foreign matters in the using process.

The technical scheme adopted by the utility model is as follows:

a patch element comprising:

the packaging body and the heat dissipation metal sheet form a containing space, a chip unit is arranged in the containing space, and the chip unit is connected with the heat dissipation metal sheet;

the chip comprises a metal pin group, wherein two metal pins are arranged on one surface of the packaging body and are configured into a first metal pin and a third metal pin, the first metal pin and the third metal pin are respectively connected with the chip unit, and the heat dissipation metal sheet is configured into a second metal pin.

Furthermore, the heat dissipation metal sheet comprises a first heat dissipation part and a second heat dissipation part, the first heat dissipation part is connected with the second heat dissipation part, an accommodating space is formed between the first heat dissipation part and the packaging body, and the second heat dissipation part protrudes out of the packaging body.

Further, the ends of the first metal pin and the third metal pin are in the same horizontal plane as the second metal pin.

Furthermore, the first metal pins are connected with the chip unit through a first routing part, and the third metal pins are connected with the chip unit through a second routing part.

Furthermore, the area of the second routing part is larger than that of the first routing part.

Specifically, the patch element includes a carrier region, the carrier dimension is set to 10.1mm by 5.4mm, the first wire-bonding portion dimension is set to 1.4mm by 1.4mm, and the second wire-bonding portion dimension is 7.1mm by 1.4 mm.

The utility model provides a novel surface-mounted MOSFET, aiming at solving the problem that three parallel Z-shaped metal pins are arranged in the conventional MOSFET, and the pin connection is extremely short-circuited easily due to the growth of electroplated layer tin whisker or foreign matters in the use process.

A patch MOSFET comprises the patch element, wherein the first metal pin is configured as a grid electrode, the second metal pin is configured as a drain electrode, and the third metal pin is configured as a source electrode.

Further, the chip unit comprises a first chip, a first PAD of the first chip is connected with the first wire bonding part, a second PAD of the first chip is connected with the second wire bonding part, and a third PAD of the first chip is connected with the metal heat sink.

The utility model provides a novel patch IGBT, aiming at solving the problem that three parallel Z-shaped metal pins are arranged in the existing IGBT, and the pin connection short circuit is easily caused by the growth of electroplated layer tin whisker or foreign matters in the use process.

A patch IGBT comprises the patch element, wherein the first metal pin is configured to be a grid electrode, the second metal pin is configured to be a collector electrode, and the third metal pin is configured to be an emitter electrode.

Further, the chip unit comprises a first chip and a second chip, the first chip is arranged on the left side, a first PAD of the first chip is connected with the first wire bonding part, a second PAD of the first chip is connected with the second wire bonding part, a third PAD of the first chip is connected with the metal heat radiating fin, the second chip is arranged on the right side, the second chip is configured to be a diode, an anode PAD of the diode is connected with the second wire bonding part, and a cathode PAD of the diode is connected with the metal heat radiating fin.

Compared with the prior art, the utility model has the beneficial effects that:

1. the patch IGBT provided by the utility model utilizes the heat dissipation metal sheet as the second metal pin, so that the middle pin of the existing IGBT is saved, and the pin spacing is further increased;

2. the patch IGBT provided by the utility model can increase the areas of the first wire bonding part and the second wire bonding part due to the omission of the middle pin of the existing IGBT, so that the device can be ensured to have enough current capacity on the basis of volume reduction;

3. the size of the carrying area is increased, namely the size of the carrying area is 10.1 x 5.4mm, so that the structure provided by the utility model can be suitable for packaging chips with more specifications;

4. the chip unit arrangement structure can meet the requirement that the distance from the first PAD of the first chip to the first wire bonding part is short, and avoids the problem that an element is easy to fail due to the fact that the distance from the first PAD of the first chip to the first wire bonding part is too long, additional stray inductance is introduced, voltage spikes in the turn-off process are improved, and the risk of element failure is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a front view of a patch element provided by an embodiment of the present invention;

fig. 2 is a rear view of a patch element provided by an embodiment of the present invention;

fig. 3 is a side view of a patch element provided by an embodiment of the present invention;

fig. 4 is a bottom view of a patch element provided by an embodiment of the present invention;

fig. 5 is a schematic view of an internal structure of a patch element according to an embodiment of the present invention.

In the drawing, 11 is a first surface of the package, 12 is a second surface of the package, 13 is a third surface of the package, 14 is a fourth surface of the package, 21 is a second heat dissipation portion of the heat dissipation metal plate, 22 is a first heat dissipation portion of the heat dissipation metal plate, 31 is a first metal pin, 32 is a third metal pin, 33 is a first wire bonding portion, 34 is a second wire bonding portion, 4 is a carrier region, 51 is a first chip, and 52 is a second chip.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

The relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description. Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

In the description of the present invention, it is to be understood that the orientation or positional relationship indicated by the orientation words such as "front, rear, upper, lower, left, right", "lateral, vertical, horizontal" and "top, bottom", etc. are usually based on the orientation or positional relationship shown in the drawings, and are only for convenience of description and simplicity of description, and in the case of not making a reverse description, these orientation words do not indicate and imply that the device or element being referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore, should not be considered as limiting the scope of the present invention; the terms "inner and outer" refer to the inner and outer relative to the profile of the respective component itself.

Spatially relative terms, such as "above … …," "above … …," "above … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, devices described as "above" or "on" other devices or configurations would then be oriented "below" or "under" the other devices or configurations. Thus, the exemplary term "above … …" can include both an orientation of "above … …" and "below … …". The device may be otherwise variously oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

It should be noted that the terms "first", "second", and the like are used to define the components, and are only used for convenience of distinguishing the corresponding components, and the terms have no special meanings unless otherwise stated, and therefore, the scope of the present invention should not be construed as being limited.

The embodiment provides a chip component, which includes a package and a metal lead group, wherein, as shown in fig. 1 and fig. 2, the package and a heat dissipation metal sheet form a receiving space, a chip unit is disposed in the receiving space, the chip unit is connected to the heat dissipation metal sheet, two metal leads are disposed on one side of the package, the two metal leads are configured as a first metal lead 31 and a third metal lead 32, the first metal lead 31 and the third metal lead 32 are respectively connected to the chip unit, and the heat dissipation metal sheet is configured as a second metal lead.

It should be noted that, as shown in fig. 1, the chip component provided in this embodiment omits the middle pin of the existing chip component, and further increases the pin pitch, and the utility model can solve the problem of short circuit caused by the growth of tin whisker of the electroplated layer or foreign matter, thereby reducing the risk of product failure and improving the yield of products; in addition, as the middle pin is omitted in the embodiment, the creepage distance between the pins can be effectively increased, and the withstand voltage is increased, the embodiment can be suitable for packaging 1200V high-voltage chips, and the traditional packaging structure (three pin structure) is only suitable for packaging products below 600V.

Specifically, as shown in fig. 1 to 4, the package provided in this embodiment includes six surfaces, which are respectively configured as a first surface 11 of the package, a second surface 12 of the package, a third surface 13 of the package, a fourth surface 14 of the package, a fifth surface of the package, and a sixth surface of the package, where the fourth surface 14 of the package is provided with two openings, the two openings are respectively configured with a first opening and a third opening, the first opening is used to expose the first metal pin 31, the third opening is used to expose the third metal pin 32, the third surface 13 of the package is provided with a second opening, and the second opening is provided with a heat dissipation metal sheet.

Further, as shown in fig. 2, the heat dissipation metal sheet includes a first heat dissipation part 22 and a second heat dissipation part 21, the first heat dissipation part 22 is connected to the second heat dissipation part 21, the first heat dissipation part 22 forms an accommodation space with the package, and the second heat dissipation part 21 protrudes out of the package.

Further, as shown in fig. 3, the first metal pin 31 and the third metal pin 32 are respectively formed by bending a strip-shaped metal sheet twice, and the bending twice makes the strip-shaped metal sheet be bent into a first section, a second section and a third section, where the first section and the second section form an obtuse angle, the second section and the third section form an obtuse angle, and the first section and the third section are parallel.

Further, the ends of the first metal pin 31 and the third metal pin 32 are at the same level as the second metal pin.

Further, as shown in fig. 5, the first metal pins 31 are connected to the chip unit through first wire bonding portions 34, and the third metal pins 32 are connected to the chip unit through second wire bonding portions 35.

Specifically, the area of the first wire bonding part 34 and the area of the second wire bonding part 35 can be adjusted according to the wire bonding requirement so as to be suitable for the wire bonding requirement, and therefore, the area of the first wire bonding part 34 and the area of the second wire bonding part 35 are not limited too much.

Preferably, in order to provide better current capacity to the element, the area of the second wire Bonding part 35 is set to be larger than that of the first wire Bonding part 34 in the embodiment, so that enough Bonding aluminum wires can be ensured in a smaller package volume.

Preferably, in order to make this embodiment be suitable for the packaging of chips with more specifications, the size of the chip carrying region 4 in this embodiment is set to 10.1mm by 5.4mm, the size of the first wire bonding portion 33 is set to 1.4mm by 1.4mm, and the size of the second wire bonding portion 34 is 7.1mm by 1.4 mm.

It should be noted that the above dimensions are suitable for the TO-263 package, so that the present embodiment can be suitable for the package of 10A/1200V IGBT chip, 15A/1200V IGBT chip, 20A/650V IGBT chip, 30A/650V IGBT chip, 40A/650V IGBT chip, and 3A/1500V MOSFET chip.

As a specific application of this embodiment, this embodiment provides a patch MOSFET, which includes the above-mentioned patch element, and the difference is that in this embodiment, the first metal pin 31 is configured as a gate, the second metal pin is configured as a drain, and the third metal pin 32 is configured as a source.

Further, the chip unit includes a first chip 51, a first PAD of the first chip 51 is connected to the first wire bonding portion 33, a second PAD of the first chip 51 is connected to the second wire bonding portion 34, and a third PAD of the first chip 51 is connected to the metal heat sink.

It should be noted that, in the embodiment, the first chip 51 is a MOSFET chip, the first PAD of the first chip 51 is configured as a gate PAD, the second PAD of the first chip 51 is configured as a source PAD, and the third PAD of the first chip 51 is a drain PAD, and the chip unit arrangement structure provided in the embodiment can meet the requirement that the distance from the first PAD of the first chip 51 to the first wire bonding portion 33 is short, so as to avoid the problem that an element is easy to fail due to an extra stray inductance introduced by an excessively long line distance from the first PAD of the first chip 51 to the first wire bonding portion 33, and a voltage spike in a turn-off process is increased, and the embodiment can reduce the risk of element failure.

As another specific application of this embodiment, this embodiment provides a patch IGBT including the patch element described above, with the difference that the first metal pin 31 is configured as a gate, the second metal pin is configured as a collector, and the third metal pin 32 is configured as an emitter.

Further, as shown in fig. 5, the chip unit includes a first chip 51 and a second chip 52, the first chip 51 is disposed on the left side, a first PAD of the first chip 51 is connected to the first wire bonding portion 33, a second PAD of the first chip 51 is connected to the second wire bonding portion 34, a third PAD of the first chip 51 is connected to the metal heat sink, the second chip 52 is disposed on the right side, the second chip 52 is configured as a diode, an anode PAD of the diode is connected to the second wire bonding portion 34, and a cathode PAD of the diode is connected to the metal heat sink.

It should be noted that, the first chip 51 is an IGBT chip, the first PAD of the first chip 51 is configured as a gate PAD, the second PAD of the first chip 51 is configured as a collector PAD, the third PAD of the first chip 51 is configured as an emitter PAD, and the second chip 52 is a diode, the chip unit arrangement structure provided by this embodiment can meet the requirement that the distance from the first PAD of the first chip 51 to the first wire bonding portion 33 is short, and avoid introducing extra stray inductance due to too long line distance from the first PAD of the first chip 51 to the first wire bonding portion 33, improving a voltage spike in a turn-off process, and causing an element failure easily, and this embodiment can reduce a risk of an element failure.

In conclusion, the patch element, the patch MOSFET and the patch IGBT provided by the embodiment can be directly attached and welded on the surface of the circuit board without additionally installing a radiator, so that the size of the circuit board can be reduced, and the layout of the circuit board is more flexible.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and equivalent alternatives or modifications according to the technical solution of the present invention and the inventive concept thereof should be covered by the scope of the present invention.

Claims

1. A patch element, comprising:

the chip comprises a metal pin group, wherein two metal pins are arranged on one surface of the packaging body, the two metal pins are configured to be a first metal pin (31) and a third metal pin (32), the first metal pin (31) and the third metal pin (32) are respectively connected with the chip unit, and the heat dissipation metal sheet is configured to be a second metal pin.

2. A patch element according to claim 1, wherein the heat sink metal sheet comprises a first heat sink part (22) and a second heat sink part (21), the first heat sink part (22) is connected to the second heat sink part (21), the first heat sink part (22) forms an accommodation space with the package body, and the second heat sink part (21) protrudes from the package body.

3. A patch element according to claim 1, wherein the ends of the first metal pin (31) and the third metal pin (32) are at the same level as the second metal pin.

4. A patch element according to claim 1, wherein the first metal pins (31) are connected to the chip unit via first wire bonding portions (33) and the third metal pins (32) are connected to the chip unit via second wire bonding portions (34).

5. A patch element as claimed in claim 4, wherein the second wire bonding portion (34) has a larger area than the first wire bonding portion (33).

6. A patch element as claimed in claim 4, wherein the patch element comprises a carrier region (4), the carrier region (4) being dimensioned to

10.1mm 5.4mm, the size of the first wire bonding portion (33) is set to be 1.4mm, and the size of the second wire bonding portion (34) is 7.1mm 1.4 mm.

7. A patch MOSFET comprising a patch element according to any of claims 1-6, characterized in that the first metal pin (31) is configured as a gate, the second metal pin is configured as a drain and the third metal pin (32) is configured as a source.

8. A patch MOSFET according to claim 7, characterized in that the chip unit comprises a first chip (51), that a first PAD of the first chip (51) is connected to a first wire bonding portion (33), that a second PAD of the first chip (51) is connected to a second wire bonding portion (34), and that a PAD of the first chip (51) is connected to a metal heat sink.

9. A patch IGBT comprising a patch element according to any of claims 1-6, characterized in that the first metal pin (31) is configured as gate, the second metal pin is configured as collector, and the third metal pin (32) is configured as emitter.

10. The patch IGBT according to claim 9, wherein the chip unit includes a first chip (51) and a second chip (52), the first chip (51) is disposed on the left side, a first PAD of the first chip (51) is connected to the first wire bonding portion (33), a second PAD of the first chip (51) is connected to the second wire bonding portion (34), a third PAD of the first chip (51) is connected to the metal heat sink, the second chip (52) is disposed on the right side, the second chip (52) is configured as a diode, an anode PAD of the diode is connected to the second wire bonding portion (34), and a cathode PAD of the diode is connected to the metal heat sink.