CN215181965U - Test fixture and test system - Google Patents

Abstract

The application discloses test fixture and test system relates to test technical field. The test fixture 10 includes: a flying probe array 11 and a detection device 12; the flying-needle array 11 includes n flying needles 01; the detection device 12 comprises a memory for storing a test program, the memory is provided with n pins meeting a first memory interface specification, and the n pins correspond to n test points meeting the first memory interface specification on the tested device 13; the roots of the n flying pins 01 are electrically connected with the n pins, and n is a positive integer.

Description

Test fixture and test system

Technical Field

The application relates to the technical field of testing, in particular to a testing jig and a testing system.

Background

The device under test is typically subjected to performance testing and, after passing the test, enters the next production stage or is supplied to the customer.

Taking testing a computer device as an example, in general, the computer device needs to be fixedly connected to a designated detection device through a data line and the like, then the computer device needs to start an operating system stored in a certain memory, and after the operating system is completely started, the detection device performs a corresponding test on the performance of the computer device.

In the testing process, because the communication connection between the tested device and the detection device needs more steps or the connection mode is more complex, the testing efficiency is low.

SUMMERY OF THE UTILITY MODEL

The embodiment of the application provides a test fixture and a test system, and the pin extension on the detection equipment is designed into a flying probe array, so that the non-fixed contact connection between the detection equipment and the tested equipment can be realized through the flying probe array, the subsequent test can be carried out, and the test efficiency can be improved. The technical scheme at least comprises the following scheme:

according to an aspect of the present application, there is provided a test fixture, including: a flying probe array and a detection device;

the flying probe array comprises n flying probes;

the detection equipment comprises a memory for storing a test program, wherein the memory is provided with n pins meeting the interface specification of the first memory, and the n pins correspond to n test points meeting the interface specification of the first memory on the tested equipment;

the roots of the n flying pins are electrically connected with the n pins, and n is a positive integer.

According to an aspect of the present application, there is provided a test system including: according to the test fixture and the lifter, the flying probe array is fixedly connected with the lifter.

The beneficial effects brought by the technical scheme provided by the embodiment of the application at least comprise:

the pin extension on the detection equipment is designed into the flying probe array, and the non-fixed contact connection between the detection equipment and the tested equipment can be realized through the flying probe array so as to carry out subsequent testing and improve the detection efficiency. That is, when the device to be tested needs to be tested, the pins on the testing device and the pins on the device to be tested are electrically connected through the flying probe array, so that the testing device can realize the rapid test on the device to be tested; after the test is completed, the flying needle array is removed from the device under test so that the device under test can quickly proceed to the next stage of production or supply to the consumer.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a schematic structural diagram of a device under test provided by an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram illustrating a sequence of operating system boot priorities provided by an exemplary embodiment of the present application;

FIG. 3 is a diagram illustrating the boot loading steps of an operating system provided by an exemplary embodiment of the present application;

fig. 4 is a schematic structural diagram of a test fixture according to an exemplary embodiment of the present application;

FIG. 5 is a schematic diagram of a connection between a device under test and a detection device provided by an exemplary embodiment of the present application;

fig. 6 is a schematic usage diagram of a test fixture according to an exemplary embodiment of the present application.

The various reference numbers in the drawings are illustrated below:

10-testing the fixture;

11-flying needle array;

12-a detection device;

13-a device under test;

01-flying needle.

Detailed Description

Unless defined otherwise, all technical terms used in the examples of the present application have the same meaning as commonly understood by one of ordinary skill in the art.

In the embodiments of the present application, reference to "front" and "rear" is made to front and rear as shown in the drawings. "first end" and "second end" are opposite ends.

To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic structural diagram of the device under test 13. Illustratively, the device under test 13 includes a processor 101 and n memories 102, where the memory 102 stores at least one program code, and the program code is loaded and executed by the processor 101.

The processor 101 includes one or more processing cores, and the processor 101 executes various functional applications and information processing by running software programs and modules. The memory 102 may be implemented by any type of volatile or non-volatile storage device or combination thereof.

Illustratively, the memory 102 includes, but is not limited to, at least one of: nand Flash Memory (Nand Flash), Serial Peripheral Interface (SPI) Memory, Embedded multimedia Card (eMMC), and Secure Digital Card (SDMMC).

Among them, an Operating System (OS) of the device under test 13 is stored in one of the memories 102. An operating system is a computer program that manages the hardware and software resources of a computer. Illustratively, the operating system includes, but is not limited to, at least one of the following: windows system, Mac system, Linux system, Chrome OS system, UNIX operating system.

In the process of starting and loading the operating system, the interfaces of the n memories 102 are sequentially accessed according to the preset starting priority, after the memory 102 with a certain starting priority detects timeout, the memory 102 with the next starting priority is continuously accessed until the memory 102 with the operating system is accessed, and the system program is loaded in the memory 102.

Optionally, referring to fig. 2, the start priority order of the operating system is as follows: 8-bit Async Nand Flash interface, 8-bit Toggle Flash interface, SPI interface, eMMC interface and SDMMC interface. Both the Async Nand Flash and the Toggle Nand Flash belong to one mode of a computer Nand Flash device.

The above sequence of the start priority is only an example, and is not limited to the present application, and the sequence may be adjusted according to actual needs.

For example, the memory 102 includes a memory 1, a memory 2, and a memory 3, and the boot priorities of the three memories are sequentially lowered, and the operating system is stored in the memory 2. When the device under test 13 starts up the operating system, the memory 1 is preferentially accessed; as the memory 1 does not store the operating system, the memory 2 is continuously accessed after the memory 1 detects timeout; since the memory 2 has an operating system stored therein, the device under test 13 will load the system program in the memory 2.

In addition, the boot loading procedure of the operating system is different according to the type of the operating system. Referring to fig. 3, taking the case that the operating system is a Linux system, the method includes the following four boot loading steps: reading a Boot Loader (Boot Loader); boot Parameters (Boot Parameters); loading a Kernel (Kernel); the file system (Boot file) is started.

Wherein the boot loader is a piece of applet that runs before the operating system kernel runs. Through the small program, hardware equipment can be initialized, and a mapping chart of a memory space is established, so that the software and hardware environment of the operating system is brought into a proper state, and a correct environment is prepared for a kernel which finally calls the operating system.

After detecting the memory 102 storing the operating system, the device under test 13 sequentially performs the boot loading step in the memory 102 to completely boot the operating system.

Fig. 4 shows a schematic structural diagram of the test fixture 10 according to the embodiment of the present application. Illustratively, the test fixture 10 includes: a flying probe array 11 and a detection device 12, n is a positive integer.

The flying probe array 11 comprises n flying probes 01, the flying probe array 11 is composed of one or more movable test probes, and the n flying probes 01 are used for connecting the detection device 12 and the device under test 13, so that the detection device 12 can detect the device under test 13.

The device under test 13 may be a Printed Circuit Board (PCBA) that has already been assembled. For example, the device under test 13 is a Central Processing Unit (CPU) board.

Specifically, the flying needle 01 is controlled to move on the device under test 13, so that the needle tip of the flying needle 01 contacts the test point to be tested, and the detection device 12 can form a communication connection with the device under test 13 through the flying needle 01.

Optionally, the tips of the n flying needles 01 contact test points on the device under test 13, where the test points are one or more pins on the device under test 13 that conform to the first memory interface specification.

The number, shape, length, material, arrangement order and mode of the flying needles 01 can be set according to actual needs, and the application is not limited herein.

Illustratively, the detection device 12 includes a memory for storing a test program, the memory has n pins conforming to a first memory interface specification, and the n pins correspond to n test points conforming to the first memory interface specification on the device under test 13; the roots of the n flying pins 01 are electrically connected with the n pins, and n is a positive integer.

Wherein, the test program is used for performing performance detection on the device under test 13. Specifically, the detection device 12 starts a test program, and the flying probe 01 is electrically connected to a pin on the detection device 12, so that the test program enables the device under test 13 to be loaded and run, thereby implementing performance detection on the device under test 13.

The n pins correspond to n test points on the device under test 13 that meet the first memory interface specification, and the first memory interface may be considered to be a memory interface supported by the device under test 13. Equivalently, the device under test 13 supports a first memory interface, n pins on a memory included in the detection device 12 conform to the first memory interface specification, and the detection device 12 can form a communication connection with the device under test 13 through the electrical connection of the n pins and the flying pin 01.

There are many implementations of electrical connection of the flying pin 01 and the pin, such as direct contact of the flying pin 01 and the pin. Illustratively, the electrical connection between the flying probe 01 and the pin is an alternative implementation as follows: the n flying needles 01 are connected with the n pins through n conducting wires. Wherein, the first end and the pin of wire are connected, and the second end of wire sets up in the root of flying needle 01.

Referring to fig. 4, the wire is arranged along the extension direction of flying needle 01, and specifically, the wire extends outwards from the root of flying needle 01 until being connected with the pin on detection device 12. Because the wire has a conductive function, under the condition of electrifying, a communicated circuit is formed between the flying needle 01 and the pin through the wire. After flying probe 01 makes contact with a test point on device under test 13, detection device 12 may communicate with device under test 13 through a path between flying probe 01 and a pin.

Optionally, in order to ensure the safety of the test, an insulating material is arranged outside the flying needle 01, and the needle tip of the flying needle 01 is exposed outside the insulating material.

For example, flying probe 01 includes leads for connecting to corresponding pins on sensing device 12 to enable sensing device 12 to form a communication link with device under test 13 via flying probe 01. Wherein, flying needle 01 wraps up insulating material outward to make the lead wire not contact with the external world directly. Meanwhile, the lead wire extends to the needle tip of the flying needle 01. Since the tip is exposed out of the insulating material, the lead can make direct contact with the test point on the device under test 13.

Taking n pins meeting the SPI interface specification on the detection device 12 and the device under test 13 being a CPU motherboard as an example, in the test fixture 10 provided in the embodiment of the present application, the roots of n flying pins 01 are electrically connected to the n pins. The detection device 12 includes a memory for storing a test program, and the test program is used for performing a performance test on the CPU board.

In addition, to realize the communication connection between the detection device 12 and the device under test 13, a via pad may be provided on the test point of the device under test 13. During the test, the tip of the flying needle 01 contacts the through-hole pad of the test point to connect the test device 12 with the test point, so that the test program can be loaded in the device under test 13. Subsequently, after the inspection is completed, the flying pin 01 is removed from the via pad to disconnect the inspection apparatus 12 from the inspected point.

To sum up, in the test fixture 10 provided in the embodiment of the present application, the pin on the detection device 12 is extended to be designed as the flying probe array 11, and the flying probe 01 in the flying probe array 11 can realize the non-fixed contact connection between the detection device 12 and the device under test 13, so as to perform the subsequent test, thereby improving the detection efficiency.

That is, when the device under test 13 needs to be tested, the pins on the detection device 12 and the pins on the device under test 13 are electrically connected through the flying probe array 11, so that the detection device 12 can realize a rapid test on the device under test 13; after the test is completed, the flying-pin array 11 is removed from the device under test 13 to allow the device under test 13 to quickly enter the next stage of production or supply to the consumer.

Illustratively, the device under test 13 also supports a second memory interface.

The second memory interface corresponds to a memory on the device under test 13 for storing an operating system; the boot priority of the first memory interface is higher than the boot priority of the second memory interface, which is used to indicate the order in which the device under test 13 loads programs from different memories at power-up.

Illustratively, the detection device 12 includes a memory that stores a test program having a start-up duration that is less than the start-up duration of the operating system.

According to the foregoing, the boot loading procedure of the operating system differs according to the type of the operating system. Referring to fig. 3, taking the case that the operating system is a Linux system, the method includes the following four boot loading steps: boot Loader; boot Parameters; kernel; boot Filesystem.

In the embodiment of the present application, taking the tested device 13 as a CPU motherboard as an example, if the connectivity of the I2S interface of the CPU motherboard needs to be tested, when the CPU motherboard reads in Boot Loader, through a General Purpose input/output port (GPIO), the test program stored in the memory in the detection device 12 can implement a fast test on the I2S interface, and it is not necessary to wait for the CPU motherboard to complete the complete start of the operating system and then detect the connectivity of the I2S interface.

In the starting process, the operating system accesses the interfaces of the storage devices in sequence according to the preset starting priority, and after the detection of the storage device with a certain starting priority is overtime, the system program is loaded from the storage device with the next starting priority.

According to the foregoing, the starting priority order of the operating systems can be set according to actual needs. Referring to fig. 2, the boot priority of the operating system may be in the following order: 8-bit Async Nand Flash, 8-bit Toggle Nand Flash, SPI interface, eMMC interface and SDMMC interface.

In the embodiment of the present application, the starting priority of the first memory interface is higher than the starting priority of the second memory interface, and after the detection device 12 is connected to the device under test 13 through the flying probe 01, the operating system will access the interface of the first memory preferentially.

In addition, in the case where the device under test 13 supports a plurality of memory interfaces, a plurality of performance detections for the device under test 13 may be achieved by replacing the detection device 12, or replacing and using a memory included in the detection device 12.

Taking the example that the device under test 13 supports 5 memory interfaces, the 5 memory interfaces include: an 8-bit Async Nand Flash interface, an 8-bit Toggle Nand Flash interface, an SPI interface, an eMMC interface and an SDMMC interface, wherein the starting priority corresponding to 5 memory interfaces is gradually reduced; the detection device 12 includes 5 memories, and the 5 memories store different detection programs. Optionally, a detection program for implementing full-function software detection of the device under test 13 is stored in a certain memory of the detection device 12, and the start priority corresponding to the memory interface is ranked at the last bit.

In the use process of the test fixture, for the memory included in the detection device 12, the n pins on the memory are changed according to the first memory interface. That is, the specific connections of the n flying pins and the n pins are different due to the difference of the first memory interface.

In accordance with the foregoing, the first memory interface includes, but is not limited to, one of the following: a Nand Flash interface; an SPI interface; an eMMC interface; and (4) SDMMC interface.

Illustratively, in order to make the pins on the device under test 13 and the pins on the detection device 12 form a one-to-one correspondence, the flying probe 01 and the physical signals indicated by the pins on the device under test 13 are in a one-to-one correspondence. The physical signal corresponding to the flying probe 01 is equivalent to the physical signal corresponding to the pin on the device under test 13.

According to the difference of the first memory interface, the specific connection of the n flying pins and the n pins is realized in four optional ways:

the first memory interface is a Nand Flash interface.

The Nand flash memory is one of flash memories, adopts a nonlinear macro-unit mode inside the Nand flash memory and provides a cheap and effective solution for realizing a solid-state large-capacity memory. The Nand flash memory has the advantages of large capacity, high rewriting speed and the like, is suitable for storing a large amount of data, and is widely applied.

Under the condition that the first memory interface is a Nand flash interface, the n flying pins and the n pins have the following connection modes:

the Nand Flash interface comprises two rows of pins, the first row of pins comprises a ready/busy pin, a read enabling pin, a chip enabling pin, a command latch enabling pin, an address latch enabling pin, a write enabling pin and a write protection pin, and the second row of pins comprises a data input/output pin;

the n flying needles 01 comprise two rows of flying needles, the first row of flying needles comprises a first flying needle, a second flying needle, a third flying needle, a fourth flying needle, a fifth flying needle, a sixth flying needle and a seventh flying needle, and the second row of flying needles comprises an eighth flying needle;

the root of the first flying probe is connected with the ready/busy pin, the root of the second flying probe is connected with the read enable pin, the root of the third flying probe is connected with the chip enable pin, the root of the fourth flying probe is connected with the command latch enable pin, the root of the fifth flying probe is connected with the address latch enable pin, the root of the sixth flying probe is connected with the write enable pin, the root of the seventh flying probe is connected with the write protection pin, and the root of the eighth flying probe is connected with the data input/output pin.

Specifically, the pins of the Nand Flash interface have the following functions and definitions:

Ready/Busy (R/B) pin: for detecting whether the operation is completed after sending the program/erase command, busy indicating that the program/erase operation is still in progress, ready indicating that the operation is completed.

Read Enable (RE) pin: the data port is used for opening a data path and outputting data in series;

chip Enable (CE) pin: before operating Nand Flash, a designated chip needs to be selected, and then operation is carried out;

command Latch Enable (CLE) pin: before a command is input, a CLE enable needs to be set in a mode register, wherein CLE is high and represents a command period;

address Latch Enable (ALE) pin: before inputting an address, an ALE (address enable) needs to be set in a mode register, wherein the ALE is high and represents an address period;

write Enable (WE) pin: the device is responsible for writing data, addresses or instructions into Nand Flash;

write Protect (WP) pin: the Flash memory is used for inhibiting programming and erasing operations of a Flash array; specifically, the pin is effective at a high level, and at the moment, writing and reading are forbidden; when the power supply is in a low level, the power supply is disabled, and can be read and written;

data Input/Output (I/O) pin: for inputting addresses/data/commands, and for outputting data.

The number of the data input/output pins can be set according to actual needs. For example, the Nand Flash interface includes 8 data input/output pins. Accordingly, the number of the first flying pins varies with the number of the data input/output pins.

In addition, the Nand Flash interface further comprises a power supply pin, a voltage pin, a grounding pin and the like. The Nand Flash interface has various types and modes, and the types and the number of pins are different according to the different types and modes of the Nand Flash interface. Based on this, the number of flying pins 01 is also affected, resulting in a change in the connection manner of the flying pins 01 and the pins. Optionally, the number of the flying pins 01 and the corresponding connection with the pins can be adjusted according to actual needs according to different pins of the Nand Flash interface, and the application is not limited herein.

Taking the device under test 13 as a CPU motherboard for example, the roots of the n flying pins 01 are electrically connected to the pins. Subsequently, the needle points of the n flying needles 01 move on the CPU main board until the needle points contact the corresponding test points.

With the help of the n flying pins 01, the pins on the CPU mainboard are electrically connected with the pins on the detection equipment 12, so that the CPU mainboard can start the test program on the detection equipment 12, namely, the CPU mainboard can load the test program based on the Nand Flash interface.

And the second memory interface is an SPI interface.

Under the condition that the first memory interface is an SPI (serial peripheral interface), the n flying pins and the n pins are connected in the following mode:

the SPI interface includes: a data input/output pin, a clock pin and a chip select signal pin;

the n flying needles 01 include: a first flying probe, a second flying probe and a third flying probe;

the root of the first flying probe is connected with a data input/output pin, the root of the second flying probe is connected with a clock pin, and the root of the third flying probe is connected with a chip selection signal pin.

Specifically, the pins of the SPI interface have the following functions and definitions:

data input/output (I/O) pins: for implementing the input or output of data, the specific role of which depends on the instruction (read or write) sent and the relative position in the time-sequential frame;

clock (Clock, CLK) pin: for analog to digital conversion;

chip Select signal (CS) pin: the low level is active for gating the read-write cycle to achieve processing of the data information.

The number of the data input/output pins can be set according to actual needs. For example, the SPI interface includes 4 data input/output pins. Accordingly, the number of the first flying pins varies with the number of the data input/output pins.

Similar to the Nand Flash interface, the SPI interface further includes a power pin, a voltage pin, a ground pin, and the like. The types and the number of the pins are different according to the types and the modes of the SPI interfaces. Based on this, the number of flying pins 01 is also affected, resulting in a change in the connection manner of the flying pins 01 and the pins. Optionally, according to the difference of the pin of the SPI interface, the number of the flying pins 01 and the corresponding connection with the pin can be adjusted according to actual needs, and the application is not limited herein.

Taking the device under test 13 as a CPU motherboard for example, the roots of the n flying pins 01 are electrically connected to the pins. Subsequently, the needle points of the n flying needles 01 move on the CPU main board until the needle points contact the corresponding test points.

And thirdly, the first memory interface is an eMMC interface.

When the first memory interface is an eMMC interface, the n flying pins and the n pins have the following connection modes:

the eMMC interface includes: a data input/output pin, a command pin, a clock pin and a data strobe pin;

the n flying needles (01) comprise: the first flying probe, the second flying probe, the third flying probe and the fourth flying probe;

the root of the first flying probe is connected with the data input/output pin, the root of the second flying probe is connected with the command pin, the root of the third flying probe is connected with the clock pin, and the root of the fourth flying probe is connected with the data gating pin.

The pins of the eMMC interface have the following functions and definitions:

data input/output (I/O) pins: for enabling input or output of data;

command (CMD) pin: command and response multiplexing pins;

clock (CLK) pin: for analog to digital conversion;

data Strobe (DS) pin: the data signal is output in a prescribed mode, and the frequency of the signal changes following the frequency of CLK.

The number of the data input/output pins can be set according to actual needs. For example, the eMMC interface includes 4 data input/output pins. Accordingly, the number of the first flying pins varies with the number of the data input/output pins.

Similar to the Nand Flash interface, the eMMC interface further includes a power pin, a voltage pin, a ground pin, and the like. Optionally, according to the difference of the pins of the eMMC interface, the number of the flying pins 01 and the corresponding connection with the pins may be adjusted according to actual needs, and the present application is not limited herein.

And fourthly, the first memory interface is an SDMMC interface.

SDMMC (secure Digital Memory card) is a secure Digital card, which is a Memory device based on a semiconductor flash Memory.

In the case that the first memory interface is an SDMMC interface, the n flying pins and the n pins have the following connection modes:

the SDMMC interface includes: a data input/output pin, a command pin, and a clock pin;

the n flying needles (01) comprise: a first flying probe, a second flying probe and a third flying probe;

the root of the first flying probe is connected with the data input/output pin, the root of the second flying probe is connected with the command pin, and the root of the third flying probe is connected with the clock pin.

The pins of the SDMMC interface have the following functions and definitions:

data input/output (I/O) pins: for enabling input or output of data;

command (CMD) pin: command and response multiplexing pins;

clock (CLK) pin: for analog to digital conversion.

The number of the data input/output pins can be set according to actual needs. For example, the SDMMC interface includes 4 data input/output pins. Accordingly, the number of the first flying pins varies with the number of the data input/output pins.

Similar to the Nand Flash interface, the SDMMC interface further includes a power pin, a voltage pin, a ground pin, and the like. Optionally, according to different pins of the SDMMC interface, the number of the flying pins 01 and the corresponding connection with the pins may be adjusted according to actual needs, which is not limited herein.

In light of the foregoing, the present application presents one exemplary embodiment as follows:

taking the example that the detection device 12 includes the first chip, fig. 5 shows a schematic diagram of the connection between the device under test 13 and the detection device 12.

The first chip has 3 types of pins, which are respectively: a data input/output pin, a clock pin, and a chip select signal pin. The number of the data input/output pins is 4, namely a DI (D0) pin, a DO (D1) pin, a WP (D2) pin and a HOLD (D3) pin; the clock pin is shown as the CLK pin and the chip select signal pin is shown as the CS pin.

The tested device 13 supports a GPIO3 interface, a Nand Flash interface, an eMMC interface, an SFC interface and an SPI interface. The device under test 13 includes the following six pins: a U11 pin, a V12 pin, a Y12 pin, a Y11 pin, a W11 pin, and a V11 pin.

The U11 pin is used as an A0 pin conforming to GPIO3 interface specification, a D0 pin conforming to Nand Flash interface specification, a D0 pin conforming to eMMC interface specification and an SIO0 pin conforming to SFC interface specification; the V12 pin is used for serving as an A1 pin conforming to GPIO3 interface specification, a D1 pin conforming to Nand Flash interface specification, a D1 pin conforming to eMMC interface specification and an SIO1 pin conforming to SFC interface specification; the Y12 pin is used for serving as an A2 pin conforming to GPIO3 interface specification, a D2 pin conforming to Nand Flash interface specification, a D2 pin conforming to eMMC interface specification and an SIO2 pin conforming to SFC interface specification; the Y11 pin is used for serving as an A3 pin conforming to GPIO3 interface specification, a D3 pin conforming to Nand Flash interface specification, a D3 pin conforming to eMMC interface specification and an SIO3 pin conforming to SFC interface specification; the W11 pin is used for serving as an A4 pin conforming to GPIO3 interface specification, a D4 pin conforming to Nand Flash interface specification, a D4 pin conforming to eMMC interface specification and a CLK pin conforming to SFC interface specification; the V11 pin is used to serve as an a5 pin compliant with GPIO3 interface specification, a D5 pin compliant with Nand Flash interface specification, a D5 pin compliant with eMMC interface specification, and a CSN0 pin compliant with SFC interface specification.

Taking the detecting device 12 including the first chip as an example, fig. 6 shows a schematic usage diagram of the test fixture.

Wherein the device under test 13 includes the following six pins: a U11 pin, a V12 pin, a Y12 pin, a Y11 pin, a W11 pin, and a V11 pin, which are referred to above. Meanwhile, the first chip has 6 pins conforming to the SPI interface specification, which are a DI (D0) pin, a DO (D1) pin, a WP (D2) pin, a HOLD (D3) pin, a CLK pin, and a CS pin, respectively. Wherein, the DI (D0) pin, the DO (D1) pin, the WP (D2) pin and the HOLD (D3) pin are data input/output pins; the CLK pin is a clock pin and the CS pin is a chip select signal pin.

Referring to fig. 6, taking the DI (D0) pin of the first chip as an example, a wire is disposed on the flying pin, a first end of the wire is connected to the DI (D0) pin, a second end of the wire is disposed at the root of the flying pin, and the tip of the flying pin contacts with the U01 port on the flying pin, so that the DI (D0) pin and the U11 pin form a communication connection.

Similarly, the other pins of the first chip and the other pins on the device under test 13 may form a one-to-one corresponding connection through wires, so that a communication connection is formed between the detection device 12 and the device under test 13, and the device under test 13 may load a test program on the detection device 12 to perform a performance test.

To sum up, the test fixture 10 provided in the embodiment of the present application designs the pin extension on the detection device 12 as the flying pin array 11, and the flying pin 01 in the flying pin array 11 can implement the non-fixed contact connection between the detection device 12 and the device under test 13, so as to implement the performance detection of the device under test 13.

In addition, under the condition that the device under test 13 includes at least two memories, the start priority of the first memory interface is set, so that the device under test 13 can start the test program in the detection device 12 preferentially without completely starting the operating system, thereby reducing the waiting time in the detection process and relatively improving the detection efficiency.

Meanwhile, the embodiment of the application also provides four different choices of the first memory interface and provides a corresponding connection mode of the flying probe 01 and the pin.

Illustratively, the embodiment of the present application further provides a testing system, where the testing system includes the testing fixture 10 and the elevator as in any of the above embodiments, and the flying probe array 11 is fixedly connected to the elevator.

Specifically, the flying needle 01 is fixed on a lifter, the contact and separation of the flying needle 01 and the tested device 13 are controlled through the falling and lifting of the lifter, so as to realize the automatic use of the flying needle array 11 on the production line,

in addition, for fixing the detection device 12, the test system provided by the embodiment of the application further includes a jig plate, and the detection device 12 is fixed on the jig plate.

In the present application, it is to be understood that the terms "first", "second", etc. are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated.

All the above optional technical solutions may be combined arbitrarily to form optional embodiments of the present application, and are not described herein again.

The above description is only exemplary of the present application and should not be taken as limiting, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims (10)

1. A test fixture, characterized in that the test fixture (10) comprises: a flying probe array (11) and a detection device (12);

the flying needle array (11) comprises n flying needles (01);

the detection device (12) comprises a memory for storing a test program, the memory is provided with n pins conforming to a first memory interface specification, and the n pins correspond to n test points conforming to the first memory interface specification on the device to be tested (13);

the roots of the n flying pins (01) are electrically connected with the n pins, and n is a positive integer.

2. The test fixture of claim 1, wherein the first memory interface is a Nand Flash interface;

the Nand Flash interface comprises two rows of pins, the first row of pins comprises a ready/busy pin, a read enabling pin, a chip enabling pin, a command latch enabling pin, an address latch enabling pin, a write enabling pin and a write protection pin, and the second row of pins comprises a data input/output pin;

the n flying needles (01) comprise two rows of flying needles, the first row of flying needles comprises a first flying needle, a second flying needle, a third flying needle, a fourth flying needle, a fifth flying needle, a sixth flying needle and a seventh flying needle, and the second row of flying needles comprises an eighth flying needle;

the root of the first flying probe is connected with the ready/busy pin, the root of the second flying probe is connected with the read enable pin, the root of the third flying probe is connected with the chip enable pin, the root of the fourth flying probe is connected with the command latch enable pin, the root of the fifth flying probe is connected with the address latch enable pin, the root of the sixth flying probe is connected with the write enable pin, the root of the seventh flying probe is connected with the write protection pin, and the root of the eighth flying probe is connected with the data input/output pin.

3. The test fixture of claim 1, wherein the first memory interface is a Serial Peripheral Interface (SPI) interface;

the SPI interface comprises: a data input/output pin, a clock pin and a chip select signal pin;

the n flying needles (01) comprise: a first flying probe, a second flying probe and a third flying probe;

the root of the first flying probe is connected with the data input/output pin, the root of the second flying probe is connected with the clock pin, and the root of the third flying probe is connected with the chip selection signal pin.

4. The test fixture of claim 1, wherein the first memory interface is an embedded multimedia card (eMMC) interface;

the eMMC interface includes: a data input/output pin, a command pin, a clock pin and a data strobe pin;

the n flying needles (01) comprise: the first flying probe, the second flying probe, the third flying probe and the fourth flying probe;

the root of the first flying probe is connected with the data input/output pin, the root of the second flying probe is connected with the command pin, the root of the third flying probe is connected with the clock pin, and the root of the fourth flying probe is connected with the data gating pin.

5. The test fixture of claim 1, wherein the first memory interface is a secure digital card (SDMMC) interface;

the SDMMC interface comprises: a data input/output pin, a command pin, and a clock pin;

the n flying needles (01) comprise: a first flying probe, a second flying probe and a third flying probe;

the root of the first flying probe is connected with the data input/output pin, the root of the second flying probe is connected with the command pin, and the root of the third flying probe is connected with the clock pin.

6. The test fixture of any one of claims 1 to 5,

the device under test (13) further supports a second memory interface corresponding to a memory on the device under test (13) for storing an operating system;

the start-up priority of the first memory interface is higher than the start-up priority of the second memory interface, the start-up priority being used to indicate an order in which the device under test (13) loads programs from different memories at power-up start-up.

7. The test fixture according to any one of claims 1 to 5, wherein the n flying pins (01) are connected to the n pins through n wires.

8. The testing fixture according to any one of claims 1 to 5, wherein the flying needle (01) is provided with an insulating material, and a tip of the flying needle (01) is exposed out of the insulating material.

9. A test system, characterized in that the test system comprises a test fixture (10) according to any one of claims 1 to 8 and a lift, the flying-pin array (11) being fixedly connected to the lift.

10. The test system according to claim 9, further comprising a jig plate, the detection device (12) being fixed to the jig plate.

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