CN213691455U - Memory, electronic device and test system thereof - Google Patents
Memory, electronic device and test system thereof Download PDFInfo
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- CN213691455U CN213691455U CN201990000295.9U CN201990000295U CN213691455U CN 213691455 U CN213691455 U CN 213691455U CN 201990000295 U CN201990000295 U CN 201990000295U CN 213691455 U CN213691455 U CN 213691455U
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
A memory and its electronic installation and test system, wherein the memory is dynamic random access memory, including DRAM memory and non-volatile memory; the DRAM memory exchanges data with the outside through a DRAM data exchange interface; the nonvolatile memory exchanges data with the outside through a nonvolatile memory data exchange interface; the nonvolatile memory is used for storing the characteristic parameter information of the DRAM memory, and the memory meeting the requirements of different devices on the DRAM memory can be customized in a targeted manner; the method can be used continuously for memories with some memory units failed.
Description
Technical Field
The utility model relates to a DRAM (dynamic Random Access memory) is the integrated circuit design, encapsulation and the test technology field of dynamic Random Access memory, and concretely relates to embeds there is the dynamic Random Access memory of characteristic parameter information, contains the electron device of this memory, memory test system, memory test method and memory application method.
Background
In the prior art, the application range of a dynamic random access memory, namely a DRAM chip, is very wide, and the requirements of various CPUs on the DRAM chips matched with the CPUs are different, so that higher requirements are put forward on the adaptability of the DRAM chips.
In the prior art, each DRAM memory cell in the DRAM has its own optimal related circuit parameter setting range, and the conventional method is to select a circuit parameter range as a test standard for a CPU platform, and a standard DRAM is used as a standard component for a customer.
In the prior art, the characteristic parameter information of a DRAM chip is usually not reserved in the DRAM chip, and a CPU needs to acquire the characteristic parameter information of the DRAM in advance and judge whether the characteristic parameter information is matched for use or not; the CPU and DRAM fit is relatively rigid and inflexible. And if the damage of part of the memory cells occurs in the DRAM chip, the whole chip can not be used continuously.
The utility model discloses a DRAM is through built-in a nonvolatile memory, the characteristic parameter information of memory storage to the characteristic parameter information with the storage shares with outside CPU or other external equipment, makes outside CPU or other external equipment can with the memory better in coordination, more nimble, even there is some memory cell to become invalid, also can continue to use DRAM.
The following is a name explanation.
DDR SDRAM is the abbreviation for Double Data Rate Synchronous Random Access Memory, Chinese meaning Double-Rate Synchronous Dynamic Random Access Memory.
LPDDR SDRAM is an abbreviation for Low Power Double Data Rate Dynamic Random Access Memory, Chinese meaning Low Power Double Data Rate Synchronous Dynamic Random Access Memory.
EEPROM is an abbreviation for english Electrically erasable programmable only memory, and chinese means an Electrically erasable programmable read only memory.
The chinese meaning of NOR FLASH is NOR-type nonvolatile FLASH.
NAND FLASH the chinese meaning is nand type non-volatile flash memory.
eMCP is an abbreviation for English Embedded Multi-Chip Package, and the Chinese meaning is: packaging an embedded multi-chip; is a chip packaging form; such as: the eMCP 254b, 254b represents 254 solder balls as signal interfaces.
LPDDR is the English Low Power Double Data Rate abbreviation, Chinese meaning: low power consumption double rate; LPDDR SDRM for short; is a chip packaging form; in LPDDR 2168 b, LPDDR 3178 b, LPDDR 4200 b, LPDDR 4366 b, the addition of a number b means that different numbers of solder balls are used as signal interfaces; the LPDDR2, LPDDR3, LPDDR4 and LPDDR5 refer to LPDDR SDRAM chip package forms of the second generation, the third generation, the fourth generation and the fifth generation respectively.
MCP is an abbreviation for English Multi-Chip Package, with the Chinese meaning: packaging multiple chips; is a chip packaging form; MCP162b, wherein 162b means 162 solder balls as signal interfaces.
DDR is an abbreviation for Double Data Rate in english, meaning in chinese: double rate; is the abbreviation of DDR SDRAM; DDR is also a form of chip packaging; among DDR 378 b, DDR 478 b and DDR 5170 b, DDR3, DDR4 and DDR5 refer to third, fourth and fifth generation DDR SDRAM chip package forms, and the following numbers plus b mean that different numbers of solder balls are used as signal interfaces.
CPU is the abbreviation of English Central Processing Unit, and the meaning of Chinese is: a central processing unit.
CAS Latency is an abbreviation for column address string Latency in english, meaning in chinese: the column address strobe is time delayed. Where CAS is an abbreviation for column address string, indicating either column address valid or column address strobe.
RCD in tRCD is an abbreviation for the english RAS to CAS Delay, also described as: tRCD, RAS to CAS Delay, Active to CMD; the Chinese meaning of tRCD is the row-to-column addressing delay time; the smaller the number, the better the performance. When a memory is read, written or refreshed, a delay clock cycle needs to be inserted between the two pulse signals. In the JEDEC specification, which is the parameter ranked second, performance can be improved by reducing this delay. However, if the value is set too low or too high, the system will be unstable, and if the performance over-clocking is not good, the value may be set as a default value for the memory or an attempt may be made to increase the tRCD value.
RAS in tRAS is an abbreviation for Min RAS Active Time in english, also described as: tRAS, Active to Precharge Delay, Row Active Time, Precharge Wait State, Row Active Delay, Row Precharge Delay, RAS Active Time; chinese meaning of tRAS: the shortest period of memory column active to precharge. The adjustment of this parameter is determined by the specific situation, and this parameter is determined according to the actual situation, and it is not necessarily said that the larger or smaller is the better. If the period of tRAS is too long, the system will degrade performance due to unnecessary waiting. Decreasing the tRAS cycle results in the activated row address entering the inactive state earlier. If the period of tRAS is too short, the burst transfer of data may not be completed due to lack of sufficient time, which may cause lost data or corrupted data. This value is typically set to CAS latency + tRCD +2 clock cycles. If CAS latency has a value of 2 and tRCD has a value of 3, the optimal tRAS value should be set to 7 clock cycles. To improve system performance, the value of tRAS should be reduced as much as possible, but should be increased if a memory error or crash occurs.
RP in tRP is an abbreviation for the english Row Precharge Time, also described as: tRP, RAS Precharge, Precharge to active; chinese meaning of tRP: memory row address controller precharge time ". The smaller the precharge parameter, the faster the memory read/write speed. tRP is used to set the charging time required for RAS before another row can be activated. Setting the tRP parameter too long results in too long of a delay for all row activations, and setting to 2 can reduce the precharge time and thus activate the next row more quickly. However, setting tRP to 2 is a high requirement for most memories, and may cause data loss before the row is activated, and the memory controller may not successfully complete the read and write operations. For desktop computers, it is recommended that the value of the precharge parameter be set to 2 clock cycles, which is the best setting. If it is lower than this, it will be degraded because each activation of the immediately adjacent bank will require 1 clock cycle, which will affect the read and write performance of the DDR memory. This value is set to 3 clock cycles only in the case where the tRP value is 2 and system instability occurs. In general, tRP values suggest values between 2 and 5. A value of 2 would yield the highest performance, a value of 4 would yield the best stability at overclock, and a value of 5 would be too conservative. Most memories cannot use a value of 2 and overclocking is required to achieve this parameter.
Chinese meaning of Fast RAS To CAS Delay: a delay time from a row address trigger signal to a column address trigger signal; typically the time between RAS descent to CAS descent.
AC in tAC is an abbreviation for Access time from CLK in english, and chinese meaning of tAC is the maximum number of input clocks at the maximum CAS latency.
CL in tCL is the abbreviation of the English CAS Latency Control, also described as tCL, CL, CAS Latency Time, CAS Time Delay; tCL chinese meaning: latency time of memory read-write operation of the address controller in the front row; the delay time required by the memory to access data is referred to, and simply, the response speed of the memory after receiving the instruction of the CPU is referred to; the smaller the number, the shorter the time required for the reaction.
RC in tRC is an abbreviation for what should be Row Cycle Time, and the Chinese meaning indicates "SDRAM Row Cycle Time", which is the minimum number of clock cycles required for the entire process including precharging a Row cell to activation. The calculation formula is as follows: a row cycle time (tRC) ═ minimum row active time (tRAS) + row precharge time (tRP). Therefore, before setting this parameter, it is necessary to know what the tRAS value and the tRP value are. If the tRC time is too long, performance may be degraded by waiting an unnecessary delay to activate a new address after the completion of a full clock cycle. Then once the value is set too small, a new cycle can be initiated before the activated row cells are sufficiently charged. In this case, data loss and corruption still result. Therefore, it is preferable to set the tRC as tRAS + tRP, and if the value of tRAS of your memory module is 7 clock cycles and the value of tRP is 4 clock cycles, the ideal value of tRC should be set to 11 clock cycles.
CPC is an abbreviation for English Command Per Clock, the number of instructions executed Per Clock cycle in Chinese meaning, also called the instruction rate, is also translated into: the first command is delayed. Also generally described as DRAM Command Rate, CMD Rate, etc. Due to the current addressing of DDR memories, P-Bank selection (via CS chip select signal) is performed first, and then L-Bank/row activation and column address selection. The meaning of this parameter is how much time, in clock cycles, a specific addressed L-Bank/row activate command can be issued after the P-Bank has been selected. Obviously, the shorter the CPC, the better.
ROM is an abbreviation for English read only memory, the Chinese meaning is: a read only memory.
RAM is the abbreviation of English RAM access memory, and Chinese meaning is: and a random access memory.
IROM is the abbreviation of English internal read only memory, and Chinese meaning is: internal ROM, refers to ROM that is integrated into the system-on-chip.
IRAM is an abbreviation for English internal ramdom access memory, the Chinese meaning is: internal RAM, refers to RAM integrated inside the system on chip.
SoC is an English system on chip abbreviation, and Chinese means: system-on-chip, also known as system-on-chip, means that it is a product, an integrated circuit with a dedicated target, which contains the complete system and has the entire content of embedded software.
BL0 is an abbreviation of BootLoader0 in English, and Chinese means the solidified starting code in IROM; the start code is used to initialize the system clock, set the watchdog, initialize the heap and stack, and load BL 1.
BL1 is the abbreviation of English BootLoader1, and the Chinese meaning refers to the maximum 16K code of the head of uboot binary file automatically copied from the external memory, namely ROM, in IRAM, and the code segment is used for initializing RAM, closing Cache, setting stack, and loading BL 2.
BL2 is an abbreviation of the english BootLoader2, chinese meaning refers to the complete code of uboot executed in memory after code redirection, which is used to initialize other peripherals, loading the OS (operating system) kernel.
BootLoader is the write-in of Booter and Loader: the former means that the embedded system hardware is initialized to run, at least partially, and functions similarly to the bios (basic Input Output system) in the PC; the latter means that the embedded operating system image is loaded into memory and jumps past runs.
In the embedded system, there is usually no firmware program like BIOS, so the load and boot task of the whole system is completely completed by BootLoader. For example, in an embedded system based on an ARM7TDMI kernel, the system usually starts to execute at the address 0x00000000 when being powered on or reset, and the BootLoader program of the system is usually arranged at the address.
In short, BootLoader is a small program that runs before the operating system kernel runs. Through the small program, hardware equipment can be initialized, and a mapping chart of a memory space is established, so that the software and hardware environment of the system is brought to a proper state, and a correct environment is prepared for finally calling an operating system kernel.
SUMMERY OF THE UTILITY MODEL
In order to avoid the defects of the prior art, the utility model designs a memory with a built-in nonvolatile memory, which is a dynamic random access memory; in the non-volatile memory, there is stored characteristic parameter information of the memory, and these stored characteristic parameter information can be shared with an external device, so that the external device can cooperate with the memory to continue to use the memory even if there is a partial memory cell failure.
The technical solution of the technical problem to be solved in the present invention is that a memory is a dynamic random access memory, which includes a DRAM memory and a DRAM data exchange interface for data exchange between the DRAM memory and the outside; the method is characterized in that:
the nonvolatile memory is used for storing the characteristic parameter information of the DRAM memory;
the data exchange interface of the nonvolatile memory is used for exchanging data between the nonvolatile memory and the outside.
The characteristic parameter information stored in the non-volatile memory includes a CAS Latency parameter, a tRCD parameter, a tRP parameter, and a tRAS parameter.
The characteristic parameter information stored in the nonvolatile memory further includes a Fast RAS To CAS Delay parameter, a tAC parameter, and a tCL parameter.
The characteristic parameter information stored in the nonvolatile memory further includes address index information of the defective memory cell, and the address index information is used for positioning an address partition where the defective memory cell is located.
The DRAM memory comprises a DDR SDRAM memory used for computers and servers.
The DDR SDRAM memory comprises a third generation DDR SDRAM memory namely DDR3 SDRAM memory, a fourth generation DDR SDRAM memory namely DDR4 SDRAM, and a fifth generation DDR SDRAM memory namely DDR5 SDRAM.
The DRAM memory, including LPDDR SDRAM memory for mobile terminals.
The LPDDR SDRAM memories include a second generation LPDDR SDRAM memory, i.e., LPDDR2 SDRAM memory, a third generation LPDDR SDRAM memory, i.e., LPDDR3 SDRAM, a fourth generation LPDDR SDRAM memory, i.e., LPDDR4 SDRAM, and a fifth generation LPDDR SDRAM memory, i.e., LPDDR5 SDRAM.
The non-volatile memory includes any one or more of EEPROM memory, NOR FLASH memory, and NAND FLASH memory.
The non-volatile memory data exchange interface includes an I2C interface.
The packaging specifications of the memory comprise LPDDR 2168 b, LPDDR 3178 b, LPDDR 4200 b, LPDDR 4366 b, eMCP 221b, eMCP 254b, MCP162b, DDR 378 b, DDR 478 b and DDR 5170 b; the idle pin in the package is utilized as a volatile memory data exchange interface.
The technical solution of the present invention to be solved by the above technical problem is also a memory test system, including a test host for test control and a test interface board for providing a memory test interface; the interface on the test interface board comprises a test board DRAM data exchange interface and a test board nonvolatile memory data exchange interface; the test board DRAM data exchange interface on the test interface board is used for being butted with the DRAM data exchange interface of the memory to be tested; the test board nonvolatile memory data exchange interface on the test interface board is used for being butted with the nonvolatile memory data exchange interface of the memory to be tested; the test host controls the test board to be connected with the DRAM data exchange interface of the memory to be tested and acquires the characteristic parameter information of the memory to be tested; the test host writes the characteristic parameter information into the nonvolatile memory of the memory through the data exchange interface of the nonvolatile memory of the test board, so that the characteristic parameter information is carried in the memory.
The interface on the test interface board also comprises a test control data exchange interface; the test control data exchange interface is simultaneously connected with the test board DRAM data exchange interface and the test board nonvolatile memory data exchange interface; the test host controls the test board DRAM data exchange interface to be connected with the DRAM data exchange interface of the memory to be tested through the test control data exchange interface, and obtains the characteristic parameter information of the memory to be tested; the test host writes the characteristic parameter information into the nonvolatile memory of the memory through the test control data exchange interface and the test board nonvolatile memory data exchange interface, so that the characteristic parameter information in the memory is self-contained.
The technical solution of the technical problem to be solved by the present invention may also be that, an electronic device equipped with the above memory includes a CPU in a main control system, the CPU includes a CPU-DRAM data exchange interface and a CPU nonvolatile memory data exchange interface; the CPU-DRAM data exchange interface is used for being butted with a DRAM data exchange interface of the memory to realize data exchange between the CPU and the memory; the CPU nonvolatile memory data exchange interface is used for being in butt joint with the nonvolatile memory data exchange interface of the memory; the CPU obtains characteristic parameter information of each unit of the memory connected with the CPU through a data exchange interface of the CPU nonvolatile memory, and the CPU performs drive control on the memory according to the characteristic parameter information of the memory.
Compared with the prior art, the beneficial effects of the utility model are that: characteristic parameter information stored by the nonvolatile memory can specifically customize memories meeting respective requirements according to the requirements of different devices on the DRAM; the method can be used continuously for memories with some memory units failed.
Drawings
FIG. 1 is a schematic diagram of an architecture of a memory;
FIG. 2 is an architecture diagram of a memory test system;
FIG. 3 is a schematic diagram of a connection architecture of a memory and a test system thereof;
FIG. 4 is a schematic diagram of a test flow of a memory;
FIG. 5 is a flow chart illustrating an application of the memory in the electronic device;
FIG. 6 is a schematic flow chart of the memory online test in the electronic device;
FIG. 7 is one of application scenarios of the memory, which is a schematic diagram of the memory architecture of the mobile phone terminal; the CPU in the figure is the CPU of the mobile phone terminal, and IRAM, IROM, RAM and ROM are arranged in the CPU; the RAM part is applied with the memory designed by the utility model;
FIG. 8 is a flow chart illustrating a mobile phone booting process in the prior art;
fig. 9 is a schematic flow chart of a mobile phone starting process after the memory designed by the present invention is applied; fig. 9 adds a step to fig. 8, namely before the kernel boot system is run, a step is performed, in which the memory characteristic parameter data stored in the non-volatile storage medium is loaded and the RAM driver is configured accordingly.
Detailed Description
The following detailed description of embodiments of the present invention will be made with reference to the accompanying drawings.
In one embodiment of the memory shown in fig. 1, the memory is a dynamic random access memory, including a DRAM memory, and a DRAM data exchange interface for data exchange between the DRAM memory and the outside; the nonvolatile memory is used for storing the characteristic parameter information of the DRAM memory; the data exchange interface of the nonvolatile memory is used for exchanging data between the nonvolatile memory and the outside.
The characteristic parameter information stored in the non-volatile memory includes a CAS Latency parameter, a tRCD parameter, a tRP parameter, and a tRAS parameter. The characteristic parameter information stored in the nonvolatile memory further includes a Fast RAS To CAS Delay parameter, a tAC parameter, and a tCL parameter.
The characteristic parameter information stored in the nonvolatile memory further includes address index information of the defective memory cell, and the address index information is used for positioning an address partition where the defective memory cell is located.
The purpose of setting the address index information is to facilitate the characteristic parameter information in the nonvolatile memory to be released to an external device for use, so that the address partition of the defective memory cell can be accurately pointed out.
It should be noted that, since the storage capacities of the DRAM and the EEPROM are different, especially the storage capacity of the EEPROM is limited, the effective area needs to be scaled. The strategy of the address partition used by the address index information can be distinguished according to the requirement of the actual application end.
The common address index information correspondence strategy includes the following:
for example, in one embodiment, assuming that a memory cell of a DRAM memory has a memory address, B (B >6) memory cells are set as an address partition, and if the 6 th memory cell has a defect and is a defective memory cell, the first region is marked as being defective, and the address index information records the location of the defective memory cell in the first region; if the nth memory cell is defective, marking the C-th area as defective, wherein C is rounded (n/B) + 1; the address index information records the location of the defective memory cell in the C-th area. The value B of the set address partition size can be dynamically adjusted according to the EEPROM storage capacity. That is, when the EEPROM has a large storage capacity, the address partitions can be taken as small as possible, and each small address partition can be more finely mapped; when the EEPROM storage capacity is small, the address partition can be as large as possible, and the characteristic parameter information can be recorded as much as possible within a reasonable quantity range. A balance is achieved between space utilization of DRAM memory and EEPROM storage capacity.
For another example, in another embodiment, assume that a DRAM memory is divided into 8 banks by two chip select signals (CS0, CS1), each bank consisting of rows and columns of capacitive cells; the address index information may be indexed by taking a bank as a unit, and the address index information is the bank corresponding to each parameter.
In some embodiments not shown in the figures, the DRAM memory comprises DDR SDRAM memory for computers and servers. The DDR SDRAM memory comprises a third generation DDR SDRAM memory namely DDR3 SDRAM memory, a fourth generation DDR SDRAM memory namely DDR4 SDRAM, and a fifth generation DDR SDRAM memory namely DDR5 SDRAM.
In some embodiments, not shown in the figures, the DRAM memory comprises LPDDR SDRAM memory for mobile terminals. The LPDDR SDRAM memories include a second generation LPDDR SDRAM memory, i.e., LPDDR2 SDRAM memory, a third generation LPDDR SDRAM memory, i.e., LPDDR3 SDRAM, a fourth generation LPDDR SDRAM memory, i.e., LPDDR4 SDRAM, and a fifth generation LPDDR SDRAM memory, i.e., LPDDR5 SDRAM.
In some embodiments not shown in the figures, the non-volatile memory includes any one or more of EEPROM memory, NOR FLASH memory, and NAND FLASH memory. The non-volatile memory data exchange interface includes an I2C interface.
In embodiments not shown in some figures, the memory package specifications include LPDDR 2168 b, LPDDR 3178 b, LPDDR 4200 b, LPDDR 4366 b, eMCP 221b, eMCP 254b, MCP162b, DDR 378 b, DDR 478 b, and DDR 51 5170 b; the idle pin in the package is utilized as a volatile memory data exchange interface.
In the embodiment of a memory test system shown in fig. 2 and 3, the memory test system comprises a test host for test control and a test interface board for providing a memory test interface; the interface on the test interface board comprises a test board DRAM data exchange interface and a test board nonvolatile memory data exchange interface; the test board DRAM data exchange interface on the test interface board is used for being butted with the DRAM data exchange interface of the memory to be tested; the test board nonvolatile memory data exchange interface on the test interface board is used for being butted with the nonvolatile memory data exchange interface of the memory to be tested; the test host controls the test board to be connected with the DRAM data exchange interface of the memory to be tested and acquires the characteristic parameter information of the memory to be tested; the test host writes the characteristic parameter information into the nonvolatile memory of the memory through the data exchange interface of the nonvolatile memory of the test board, so that the characteristic parameter information is carried in the memory.
In the embodiment of the memory test system shown in fig. 2 and 3, the interface on the test interface board further includes a test control data exchange interface; the test control data exchange interface is simultaneously connected with the test board DRAM data exchange interface and the test board nonvolatile memory data exchange interface; the test host controls the test board DRAM data exchange interface to be connected with the DRAM data exchange interface of the memory to be tested through the test control data exchange interface, and obtains the characteristic parameter information of the memory to be tested; the test host writes the characteristic parameter information into the nonvolatile memory of the memory through the test control data exchange interface and the test board nonvolatile memory data exchange interface, so that the characteristic parameter information in the memory is self-contained.
In the embodiment of a memory test method shown in fig. 4, step 11 is: putting a memory to be tested into a test interface board in a memory test system; step 12: the test host sends a test instruction to the memory to be tested and starts the test; step 13: the test host scans the memory to be tested to obtain the characteristic parameter information of the memory; step 14: the test host writes the acquired characteristic parameter information of the memory into a nonvolatile memory in the memory through a nonvolatile memory data exchange interface; step 141: and the test host classifies the memories according to the acquired characteristic parameter information of the memories, and writes the classified data of the memories and the characteristic parameter information into the nonvolatile memories in the memories through the nonvolatile memory data exchange interfaces.
In some embodiments of a memory test method not shown in the figures includes,
step A5: the test host sets the characteristic parameter information to be acquired according to the external instruction, and writes the specified characteristic parameter information into the nonvolatile memory according to the requirement of the external instruction. That is, in the test, the characteristic parameters that are desired to be stored in the non-volatile memory can be flexibly configured in the test program according to the customized requirements of the customer, and the characteristic parameters can include the applicable voltage range of the memory, and the writing and reading information of the memory is set. Step a5 may be before step 12 or step 13, or after step 12 or step 13, and may be started as long as the test host and the memory under test have established electrical connection.
In an embodiment of the electronic device equipped with the above memory, not shown in the drawings, comprises a CPU in the main control system, the CPU comprising a CPU-DRAM data exchange interface and a CPU non-volatile memory data exchange interface; the CPU-DRAM data exchange interface is used for being butted with a DRAM data exchange interface of the memory to realize data exchange between the CPU and the memory; the CPU nonvolatile memory data exchange interface is used for being in butt joint with the nonvolatile memory data exchange interface of the memory; the CPU obtains characteristic parameter information of each unit of the memory connected with the CPU through a data exchange interface of the CPU nonvolatile memory, and the CPU performs drive control on the memory according to the characteristic parameter information of the memory.
As shown in fig. 6, a method for testing a memory based on the electronic device includes, in step 21: the CPU sends a test instruction to the memory to be tested and starts a test; step 22: the CPU controls and scans the memory to be tested to acquire new characteristic parameter information; step 23: and the CPU writes the acquired new characteristic parameter information into a nonvolatile memory in the memory through a nonvolatile memory data exchange interface to cover the characteristic parameter information originally stored in the nonvolatile memory.
In a memory testing method based on the electronic device, which is not shown in the drawings, the method further includes step 231: the CPU classifies the memories according to the acquired new characteristic parameter information, and writes classification data and the characteristic parameter information of the memories into the nonvolatile memories in the memories through the data exchange interfaces of the nonvolatile memories; step 24: and the CPU reconfigures the driving parameters of the memory according to the acquired new characteristic parameter information.
Not shown in the drawings, an embodiment of a method for memory application comprises the steps 31: the setting memory is a dynamic random access memory and comprises a DRAM memory and a nonvolatile memory, wherein the nonvolatile memory is used for storing characteristic parameter information of the DRAM memory; step 32: and setting a terminal applying the memory, wherein the terminal comprises an application terminal CPU.
As shown in fig. 5, an embodiment of the method for applying a memory further includes step 33: an application terminal CPU sends an instruction to a memory to acquire characteristic parameter information stored in a nonvolatile memory of the memory; step 34: and the application terminal CPU performs drive control on the memory according to all the acquired characteristic parameter information of the memory. The CPU drives the exchange of data between the memory and the CPU.
As shown in fig. 7 and 8, in the starting process of the mobile phone terminal without the application of the present invention, the starting code BL0 is stored in the IROM of the CPU of the terminal, the CPU will go to run BL0 in the IROM after powering on, and is used to initialize the system clock, set the watchdog, initialize the stack and stack, and finally load the BL1 stored in the ROM to the IRAM to execute, at this time, the RAM can be initialized, the Cache is closed, the stack is set, then the BL2 stored in the ROM is loaded, and the BL2 is responsible for initializing other peripherals, and finally load the OS kernel code stored in the ROM to the RAM, and then run the kernel program starting system.
As shown in fig. 7, BL1 and BL2 are distinguished, but not merged together to execute, because IRAM is small, only tens of K in size, and uboot is not completely coded, so that IRAM is divided into two parts, the large part is moved to RAM to run, BL1 initializes memory (RAM) and tells BL2 the basic information (several chip selects, total memory size) of the memory, BL2 assembles the information into the result body of a device tree (device tree), and finally transfers the device tree to the kernel, and starts the kernel. After the kernel is started, the device tree information is analyzed to carry out various specific settings, wherein the memory information including available regions and region size information is taken from the device tree, and the available regions are reported to the system to be used by the system.
Specifically, the step of the CPU reading the characteristic parameter information in the non-volatile memory and configuring the corresponding memory driver may be completed at any point after the step of running BL0 and before the kernel is started. Namely, the steps of reading the characteristic parameter information in the non-volatile memory and configuring the corresponding memory driver may be completed before step BL1 or in step BL1, or may be completed in step BL2 or after. The above steps of reading the characteristic parameter information and configuring the corresponding memory driver are completed before the kernel program is started as long as the system is booted up.
As shown in fig. 9, in the application embodiment of a memory applied to a mobile phone terminal, during the starting process of the system, after step BL2, the RAM is initialized, that is, the characteristic parameter information stored in the non-volatile memory is transferred to the CPU, so that the CPU establishes a new memory driver based on the characteristic parameter information.
In the test method and application of the dynamic random access memory chip (DRAM memory chip) in the prior art, the chip test mode (pattern) is mainly to write and read each access address for a plurality of times, namely, sequential scanning and random scanning after setting the highest and lowest voltage values; the chip grade is classified according to a set voltage range and the read-write times, and is used as a standard storage IC component to be supplied to an application terminal, such as a mobile phone; the higher the chip grade is, the smaller the voltage application range, the more the read-write scanning times are, the better the compatibility of the application platform, namely various CPUs is, but the test yield is low and the cost is high.
When the application terminal is designed and developed, the DRAM memory chip with the corresponding grade is selected, and the DRAM memory chip is adapted by adjusting the software and the hardware of the system, so that the higher the grade of the chip is, the better the adaptability is, the higher the cost is, the development period is prolonged, and the development cost is increased. In the period of few development platforms and not intense competition, the price of the DRAM memory chip can be balanced by prolonging the development time. With the aggravation of market competition, the increase of platforms, the shortening of the period of launching new models by each platform and the personalized customer requirements, the development period of the new models of the application terminals is greatly compressed. The standardized supply mode of the existing DRAM memory chip is not more and more suitable for the compatibility and customization requirements of the current market, and a new DRAM memory chip solution is urgently needed.
In the utility model, the characteristic parameter information of the DRAM memory is recorded in the nonvolatile memory integrated in the same chip with the DRAM memory, and is used for the CPU to call and adjust the driving parameter value of the CPU to the optimal parameter, so that the matching range between the CPU and the DRAM memory is greatly expanded, and the matching range is more flexible; the availability ratio of the DRAM memory can be increased from 70 percent to more than 90 percent. Under the background that the functions and the performances of the CPU are increasingly powerful, the mode greatly improves the comprehensive efficiency of the electronic device and can obtain better balance between the cost efficiency.
The above only is the embodiment of the present invention, not limiting the scope of the present invention, and all the equivalent structures or equivalent processes that are made by using the contents of the specification and the drawings of the present invention or directly or indirectly applied to other related technical fields are included in the same way in the protection scope of the present invention.
Claims (14)
1. The memory is a dynamic random access memory and comprises a DRAM memory and a DRAM data exchange interface used for data exchange between the DRAM memory and the outside; the method is characterized in that:
the nonvolatile memory is used for storing the characteristic parameter information of the DRAM memory;
the data exchange interface of the nonvolatile memory is used for exchanging data between the nonvolatile memory and the outside.
2. The memory of claim 1, wherein:
the characteristic parameter information stored in the non-volatile memory includes a CAS Latency parameter, a tRCD parameter, a tRP parameter, and a tRAS parameter.
3. The memory of claim 2, wherein:
the characteristic parameter information stored in the nonvolatile memory further includes a Fast RAS To CAS Delay parameter, a tAC parameter, and a tCL parameter.
4. The memory of claim 2, wherein:
the characteristic parameter information stored in the nonvolatile memory further includes address index information of the defective memory cell, and the address index information is used for positioning an address partition where the defective memory cell is located.
5. The memory of claim 1, wherein:
the DRAM memory comprises a DDR SDRAM memory used for computers and servers.
6. The memory of claim 5, wherein:
the DDR SDRAM memory comprises a third generation DDR SDRAM memory namely DDR3 SDRAM memory, a fourth generation DDR SDRAM memory namely DDR4 SDRAM, and a fifth generation DDR SDRAM memory namely DDR5 SDRAM.
7. The memory of claim 1, wherein:
the DRAM memory, including LPDDR SDRAM memory for mobile terminals.
8. The memory of claim 7, wherein:
the LPDDR SDRAM memories include a second generation LPDDR SDRAM memory, i.e., LPDDR2 SDRAM memory, a third generation LPDDR SDRAM memory, i.e., LPDDR3 SDRAM, a fourth generation LPDDR SDRAM memory, i.e., LPDDR4 SDRAM, and a fifth generation LPDDR SDRAM memory, i.e., LPDDR5 SDRAM.
9. The memory of claim 1, wherein:
the non-volatile memory includes any one or more of EEPROM memory, NOR FLASH memory, and NAND FLASH memory.
10. The memory of claim 1, wherein:
the non-volatile memory data exchange interface includes an I2C interface.
11. The memory of claim 1, wherein:
the packaging specifications of the memory comprise LPDDR 2168 b, LPDDR 3178 b, LPDDR 4200 b, LPDDR 4366 b, eMCP 221b, eMCP 254b, MCP162b, DDR 378 b, DDR 478 b and DDR 5170 b; the idle pin in the package is utilized as a volatile memory data exchange interface.
12. A memory test system, characterized by:
the device comprises a test host used for test control and a test interface board used for providing a memory test interface;
the interface on the test interface board comprises a test board DRAM data exchange interface and a test board nonvolatile memory data exchange interface;
the test board DRAM data exchange interface on the test interface board is used for being butted with the DRAM data exchange interface of the memory to be tested;
the test board nonvolatile memory data exchange interface on the test interface board is used for being butted with the nonvolatile memory data exchange interface of the memory to be tested;
the test host controls the test board to be connected with the DRAM data exchange interface of the memory to be tested and acquires the characteristic parameter information of the memory to be tested; the test host writes the characteristic parameter information into the nonvolatile memory of the memory through the data exchange interface of the nonvolatile memory of the test board, so that the characteristic parameter information is carried in the memory.
13. The memory test system of claim 12, wherein:
the interface on the test interface board also comprises a test control data exchange interface; the test control data exchange interface is simultaneously connected with the test board DRAM data exchange interface and the test board nonvolatile memory data exchange interface;
the test host controls the test board DRAM data exchange interface to be connected with the DRAM data exchange interface of the memory to be tested through the test control data exchange interface, and obtains the characteristic parameter information of the memory to be tested;
the test host writes the characteristic parameter information into the nonvolatile memory of the memory through the test control data exchange interface and the test board nonvolatile memory data exchange interface, so that the characteristic parameter information in the memory is self-contained.
14. An electronic device equipped with the memory of any one of claims 1 to 11, characterized in that:
the electronic device comprises a CPU in a main control system, wherein the CPU comprises a CPU-DRAM data exchange interface and a CPU nonvolatile memory data exchange interface;
the CPU-DRAM data exchange interface is used for being butted with a DRAM data exchange interface of the memory to realize data exchange between the CPU and the memory;
the CPU nonvolatile memory data exchange interface is used for being in butt joint with the nonvolatile memory data exchange interface of the memory; the CPU obtains characteristic parameter information of each unit of the memory connected with the CPU through a data exchange interface of the CPU nonvolatile memory, and the CPU performs drive control on the memory according to the characteristic parameter information of the memory.
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| PCT/CN2019/082581 WO2020199242A1 (en) | 2019-04-04 | 2019-04-12 | Memory and electronic apparatus therefor and test system, test method and application method therefor |
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| CN113488101B (en) * | 2021-09-07 | 2021-12-28 | 北京紫光青藤微系统有限公司 | System for testing drive capability of NOR Flash chip and electronic equipment |
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| KR20130032772A (en) * | 2011-09-23 | 2013-04-02 | 삼성전자주식회사 | Hybrid memory device, computer system including the same, and method of reading and writing data in the hybrid memory device |
| CN103810113B (en) * | 2014-01-28 | 2016-07-06 | 华中科技大学 | A kind of fusion memory system of nonvolatile storage and dynamic random access memory |
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| US10241727B1 (en) * | 2015-10-15 | 2019-03-26 | Rambus Inc. | Hybrid memory module with improved inter-memory data transmission path |
| US10628049B2 (en) * | 2017-07-12 | 2020-04-21 | Sandisk Technologies Llc | Systems and methods for on-die control of memory command, timing, and/or control signals |
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