BR102014024441A2 - method for parameter optimization on system and device startup using the same - Google Patents

Abstract

Method for parameter optimization on system and device initialization using the same method for parameter optimization and associated apparatus are provided. The method performs a dram write calibration to obtain a write parameter after a dram read calibration fails, where the dram read calibration writes test data to a specific dram address with a default write parameter. and tries to find a read parameter for reading data from dram. replaces the default write parameter stored in nonvolatile memory with the write parameter obtained, where the default write parameter is stored in the boot loader.

Description

METHOD FOR PARAMETER OPTIMIZATION IN SYSTEM INITIALIZATION AND APPARATUS USING THE SAME

GROUNDS

TECHNICAL FIELD

[001] The invention relates to system initialization, and in particular to a method for parameter optimization on system initialization and apparatus utilizing the same.

DESCRIPTION OF RELATED TECHNIQUE

[002] During system startup on an embedded system, a Dynamic Random Access Memory (DRAM) must be started before loading instructions and data from nonvolatile memory (eg flash memory) into the DRAM. Conventionally, embedded systems obtain different access parameters appropriate for different PCB (printed circuit board) schemes from their nonvolatile memories. This requires engineers to generate a new set of default pop-up parameters in the manual form and to rn ργργ to a client of vt w J— JL 1— CΛ fw 'Ca VU ~ L_ V »/ XX ti JL-w -I— XLLC * X XI tCX XX UX Ci. —U v · * X. θ 'X— XX Vt · *' Ç * -A— CX νΧΧ V lv— * -X. -X- X X w V — X V-a to store them in nonvolatile memory arranged in the specific PCB scheme. Conventional technique requires engineer resources and nonvolatile memory space. Therefore, there is a need for a built-in system that provides the automatic access parameter calibration capability of a DRAM on it at system startup.

BRIEF SUMMARY

[003] The invention describes a method for parameter optimization at system startup, performed by a microcontroller in fetching and executing instructions from a boot loader is disclosed to include at least the following steps. A DRAM write calibration is performed to obtain a write parameter after a DRAM read calibration fails, where the DRAM read calibration writes test data to a specific DRAM address with a default write parameter and attempts find a read parameter for reading data from the DRAM. The default write parameter stored in nonvolatile memory is replaced with the write parameter obtained, where the default write parameter is stored in the boot loader.

[004] The invention further describes a method for parameter optimization at system startup, performed by a microcontroller in seeking and executing instructions from a boot loader, is disclosed to include at least the following steps. A first DRAM read calibration is performed, wherein the microcontroller writes test data to a specific DRAM address with a default write parameter and attempts to find a read parameter for reading data from the DRAM. A DRAM write calibration is performed to obtain a new write parameter and a read parameter after the first DRAM write calibration fails.

[005] The invention also describes a parameter boot apparatus for system initialization and is disclosed to include at least one non-volatile memory storing a boot loader, and a microcontroller. The microcontroller is configured to duplicate the first boot loader portion from nonvolatile memory in a Static Random Access Memory (SRAM), fetch and execute instructions from the first boot loader portion from the SRAM to perform a load calibration. DRAM write then to get a write parameter after a first DRAM read calibration fails, where the first DRAM read calibration writes test data to a specific DRAM address with a default write parameter and tries to find a read parameter for reading data from the DRAM. The microcontroller is configured to further replace the default write parameter stored in the first portion of the non-volatile memory boot loader with the write parameter obtained.

[006] A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[007] The invention can be fully understood by reading the following detailed description and examples with reference to the accompanying drawings, in which: Figure 1 shows a hardware architecture of an apparatus according to one embodiment of the invention; Figure 2 is a flow chart showing an initialization process according to one embodiment of the invention; Figure 3 is a schematic diagram illustrating DQS and DQ after DRAM read calibration;

Figures 4A and 4B illustrate a flowchart of a method of a DRAM reading calibration according to an embodiment of the invention; Figure 5 is a schematic diagram illustrating a left margin of the data window on the DQ line according to one embodiment of the invention; Figure 6 is a schematic diagram illustrating a right edge of the data window on the DQ line according to one embodiment of the invention; Figure 7 illustrates a flowchart showing a method of a DRAM access calibration according to an embodiment of the invention; and Figure 8 illustrates a schematic diagram of a binary file according to one embodiment of the invention.

DETAILED DESCRIPTION

The following is intended to illustrate the general principles of the present invention and should not be taken in a limiting sense. The scope of the invention is mpl h nr H pf nr mi nadn nor rpf orpnri λ A q rpi vi ndi rsrops snpXris A. IL Vx * JL AW -L- VA U * JL X 11 -J— xx LA \ - / KL L / X, -L. -L- v »X * w X X —J—. LA LA Λ— V-r ~ X ~. V -X. X X VA -X- V- * LA VL LA X X V ** x X LA LX · [009] Figure 1 shows a hardware architecture of an apparatus 10 according to one embodiment of the invention. The apparatus 10 may be implemented in a SOC (System On a Chip), which contains at least one microcontroller 110, one SRAM (Static Random Access Memory) 150 and one non-volatile memory 170. A DRAM 130 may be positioned inside or outside the SOC. Microcontroller 110 coupled with DRAM 130, SRAM 150, and nonvolatile memory 170 via a bus 190 to access relevant instructions and data and is configured to perform computational and control tasks to be described below during a system startup when performing instructions with relevant data. The boot system is the initial set of operations that a computer system performs after power to the microcontroller 110 is turned on or when the apparatus 10 is restarted. The process can begin when device 10 is turned on, or when it is restarted, and ends when device 10 is ready to perform its normal operations. Nonvolatile memory 170, such as NOR flash memory, NAND flash memory, EMMC (Embedded Multimedia Card) flash memory, etc., is a nonvolatile storage device where values will not be lost when the power is turned off. . A boot loader 171 and system firmware (not shown) are stored in nonvolatile memory 170, each of which contains instructions and data relevant for system boot. SRAM 150 can provide a smaller storage capacity, for example 16K bytes, than offered by DRAM 130. It should be understood that SRAM 150 is not large enough to store the entire boot loader 171. Therefore, the boot loader 171 171 can be divided into two portions, wherein a first portion contains at least instructions, a default write parameter, and a default read parameter for access to DRAM 130, and a second portion contains instructions and data relevant to the remaining operations of the DRAM 130. system boot. It may be advantageous that placing the default write parameter on the first portion of the boot loader 171 avoids the storage space of nonvolatile memory 170 from being unnecessarily consumed. It should be understood that the non-volatile memory space allocation 170 may be a multiple of a block size. For example, a block of NAND flash memory is 512K bytes. Although the write parameter and default read parameter require some bytes, for example, two bytes, it allocates an additional 512K bytes in nonvolatile memory 170 to store the default write parameter when the default write parameter is stored in a file. separate and independent from boot loader 171. As a result, the second portion of boot loader 171 (that is, most instructions with relevant data) can be loaded into DRAM 130 for execution after DRAM 130 has been successfully started.

[010] An exemplary scatter file of a binder defining the first portion of boot loader 171 is shown as follows. CHARGER 0x0 {RO +0 {Int.o (Init, + FIRST) * (+ RO)} RW + 0 {* (+ RW + ZI)} DRAWN 0x00009800 FIXED PADVALUE OxFFFFFFFF (* (DRAMP)}} [011] With With reference to the scatter file, the first portion of boot loader 171 has sections RO (read only), RW (read and write), ZI (zero), and DRAMP Figure 8 illustrates a schematic diagram of a binary file according to with an embodiment of the invention Section RO 810 is provided for storing at least instructions for starting DRAM 130.

For example, section 820 includes an RW section for storing initialized variables, such as global variables, and a ZI section for storing uninitialized variables. The DRAMP 8AM section starts from a predefined address 0x9800 and is provided to store the default read and write parameters. The byte array or similar but different data structure can be declared by instructions stored in section RO 810, and is mapped to section DRAMP 830 to indicate the default read and write parameters. Exemplary source code is as follows: static unsígned int _au4DramParams [DRAM_PARAMS_SIZES] _attribute_ ((section (“D RA M PA RAM”))) = {0, 1, 2, 3, 4, 5, 6, 7,} Unsígned int DRAMGeíParameter (char ulParamldx) {return _an4DramParams [ulParamldx]; } [012] The byte array stores a standard 32-bit write parameter indicating a no-step DQS output delay, and a standard 32-bit read parameter indicating an eight-step DQS input delay. Details of DQS output delay and DQS input delay will be discussed in the following paragraphs.

Figure 2 is a flowchart showing an initialization process according to one embodiment of the invention. After the system is powered on (step S211), the first portion of boot loader 171 is doubled from nonvolatile memory 170 to SRAM 150, which is instructed by microcontroller 110 (step S213). Microcontroller 110 fetches and executes instructions from the first portion of boot loader 171 of SRAM 150 to perform a DRAM read calibration with the default write parameter of the first portion of boot loader 171 (step S215). The default write parameter may indicate a DQS output delay for writing data to DRAM memory 130, denoted as a number of steps ranging from 0 to 15 or from 0 to 31, for example, and each step may be 15 picoseconds. DQS can be a bidirectional strobe signal. DRAM controller (not shown) can trigger DQS by signaling DRAM 130 to obtain data on the DQ line in DQS transitions, referred to as a strobe signal for data write operations. Figure 3 is a schematic diagram illustrating DQS and DQ after DRAM read calibration. DRAM read calibration encounters a DQS output delay for reading data from DRAM 130, such that the centers of the rising edges and the falling edges of the DQS can occur substantially at the data window centers 310. on the DQ line.

[014] Details of step S215 are discussed below. Figures 4A and 4B illustrate a flowchart of a method of a DRAM reading calibration according to an embodiment of the invention. The process, performed by microcontroller 110, begins writing test data to a specific DRAM address 130 with the default write parameter recorded in the first portion of boot loader 171 (step S411). Steps S421 through S435 are performed to, for example, incrementally increment a DQ input delay for reading data from DRAM 130 while a DQS input delay is maintained until data fails to be read, and writes an amount. resulting from increments of a magnitude indicating a left margin of data window 310. First, an input delay of DQS DELAYdqs in is initialized. For example, the DQS DELAYDQS_in input delay for reading data from DRAM 130 is set to zero, which is maintained until the magnitude indicating the left margin of data window 310 is found, (step S421) and a delay of DQ input DELAYdq in is set to zero (step S423). An inline DRAM controller 110 may trigger DQS by suggesting that microcontroller 110 fetch data on the DQ line by detecting a rising edge and a falling edge of the DQS, referred to as a strobe signal for data read operations. An inspection cycle including S425 through S433 runs repeatedly until the data fails to be read. In the inspection cycle, microcontroller 110 attempts to read data at the specified address from DRAM 130 with the defined DQS and DQ input delays (step S425}, determines whether the data reading matches the test data (step S431 ) and increments the DQ DELAYDQ_in input delay by one step for the next run (step S433) when reading data matches the test data (the "Yes" Path of step S431), otherwise when reading data does not match the test data (the "No" path from step S431), the inspection cycle is skipped and the magnitude MARGINieft indicating the left margin of the data window 310 is set to the resulting DQ input delay DELAYDq in (Step S435) Figure 5 is a schematic diagram illustrating the left margin inspection of data window 310 on the DQ line according to one embodiment of the invention With the DQ DELAYDQ_in input delay increments from the moments you have it , the data window 310 is later gradually shifted. After m executions, data cannot be read because data is not available on the DQ line.

Thus, a magnitude indicating the left margin of data window 310 is defined as m. Referring to Figure 4Δ. Steps S441 to S455 are performed to gradually increment the DQS input delay for reading data from DRAM 130 while the DQ input delay is maintained until the data cannot be read, and write an incremental amount as a result. magnitude indicating a right margin of data window 310. Initially, an input delay of DQ DELAYDQ_in is set to zero, which is maintained until the magnitude indicating the right margin of data window 310 is found, (step S441) and a DQS input delay DELAYDQS_in for reading data from DRAM 130 be set to zero (step S443). An inspection cycle including S445 to S453 runs repeatedly until data fails to be read. In the inspection cycle, the microcontroller 110 attempts to read data at the specified address from DRAM 130 with the defined DQS and DQ input delays (step S445), determines whether the data reading matches the test data (step S451 ) and increments the input delay of DQS DELAYDQs_in by one step for the next run (step S453) when reading data coincides with the test data (the "Yes" Path of step S451). Otherwise, when the data reading does not match the test data (the "No" path from step S451), the inspection cycle is skipped and the MARGINright magnitude indicating the right margin of data window 310 is set as the delay. DQS input file DELAYDQS_in (step S455). Figure 6 is a schematic diagram illustrating the right edge inspection of data window 310 on the DQ line according to one embodiment of the invention. With the DQS DELAYDQS_in input delay increments of moments t0, ti to tn, the rising and falling edges of the DQS signal are gradually shifted later. After n offset executions, the data is no longer read because the data is not ready on the DQ line. Thus, magnitude indicating the right margin of data window 310 is set to n. Note that left margin determination was performed by steps S421 to S435 and right margin determination performed by steps S441 to S455 can be changed, and the invention should not be limited thereto. Referring to Figure 4B. After the magnitudes indicating the left and right margins of data window 310 are determined, a length of data window LENDw is determined as the sum of magnitudes MARGINleft and MARGINright (step S461). It is then determined whether the given LENDw data window exceeds a predefined threshold (step S463). The limit, for example, can be preset to 8 when the maximum allowed travel steps is 16, and 16 when the maximum allowed travel steps is 32. If so (the "Yes" path of step S463), DRAM read calibration is determined to be successful (step S471) and the final DQS input delay DELAYDQS_in is set to an integer according to the determined magnitudes MARGINieft and MARGINright to achieve the above objective (step S473 ); otherwise (the "No" path from step S463), it is determined that the DRAM read calibration fails (step S481). It should be understood that the final DQS input delay can be considered as a calibrated read parameter stored in SRAM 150 and nonvolatile memory 170 to replace the old ones respectively.

[015] Referring to Figure 2. After performing the DRAM read calibration (step S215), it is determined whether the DRAM read calibration with the default write parameter was successful (step S217). If so (the "Yes" path of step S217), the second portion of boot loader 171 is doubled from nonvolatile memory 170 to DRAM 130 by microcontroller 110 (step S251), and the instructions of the second portion of boot loader 171 are fetched from DRAM 130 by microcontroller 110, and executed to perform the remainder of the system boot (step S253). When performing DRAM read calibration with the default write parameter is not successful (the "No" path from step S217), microcontroller 110 performs a DRAM write calibration (step S231). Details of step S231 are discussed as follows.

Figure 7 illustrates a flowchart showing a method of a DRAM write calibration according to an embodiment of the invention. The process, performed by the microcontroller 110, initializes an output delay of DQS DELAYDQS_out. For example, it sets the DQS output delay DELAYdqs out to write data in DRAM from 130 to zero (step S711). An inspection cycle including S713 through S725 is performed repeatedly until a predefined condition is met. In the inspection cycle, microcontroller 110 writes test data to a specific address in DRAM 130 with the set DQS output delay DELAYDQS_0ut (S713), and performs a modified DRAM read calibration with the set DQS output delay DELAYdqs Qut (step S715). The substantially modified DRAM read calibration incorporates with steps S411 through S461, and S473. The data window scan performed at step S463 and consequent determination performed at steps S471 and S481 can be removed from the modified DRAM read calibration. On top of that, step S411 is modified to write test data to a specific DRAM address with the DQS output delay set DELAYDQs_outr instead of the default. Step S473 is modified to be the next step of S461 without intervening steps S463 and S471 and to set the DQS input delay DELAYDQS_in (ie a temporary result) to an integer according to the given magnitudes MARGINieft and MARGINrig} lt. Microcontroller 110 then determines whether the LENDW data window determined in the modified DRAM read calibration exceeds a predefined threshold (that is, the default condition) (step S721). When the predefined condition is not met (the "no" branch of step S721), microcontroller 110 increments the DELAYDQS__out DQS output delay by one step (step S723), and determines whether the DELAYDQS_0ut incremented DQS output delay is equal. to the default maximum value (for example, 8) (step S725). If so (the "yes" branch of step S725), microcontroller 110 determines that DRAM write calibration fails; otherwise (the "NO" branch of step S725), and microcontroller 110 writes test data to a specific address in DRAM 130 with the DQS output delay set DELAYdqs out (S713), and performs DRAM read calibration. modified with the output delay of set DELAYdqs out (step S715). When the predefined condition is met (the "yes" branch of step S721), the inspection cycle is skipped out. Preferably, after the inspection cycle, the DQS DELAYDQs_out output delay and updated DQS DELAYDQS_in input delay are stored in SRAM 150 and / or nonvolatile memory 170 for later use.

[017] Referring to Figure 2. After DRAM write calibration is completed, that is, DRAM 130 is available for access, the default write parameter of the first portion of boot loader 171, which is stored in SRAM 150 , is replaced by a new one (step S233). In addition, the default write parameter of the first portion of boot loader 171, which is stored in nonvolatile memory 170, is replaced by a new one (step S235). The new write parameter is obtained by performing DRAM write calibration. Then, the second portion of boot loader 171 is doubled from nonvolatile memory 170 to DRAM 130 by microcontroller 110 (step S251). Microcontroller 110 fetches and executes instructions from the second portion of DRAM 130 to complete system initialization (step S253). Although Figure 2 has been described with the determination of step S217, it should be noted that the determination may be omitted and the invention should not be limited thereto. That is, regardless of the result of the DRAM read calibration, steps S231 to S235 can always be performed after the DRAM read calibration.

Although the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various similar modifications and arrangements. Therefore, the scope of the appended claims should be assigned with the broadest interpretation to encompass all such modifications and similar arrangements.

Claims (21)

Parameter optimization method, performed by a microcontroller for seeking and executing instructions from a boot loader, characterized in that it comprises: performing a DRAM write calibration to obtain a write parameter; and replacing the default write parameter stored in nonvolatile memory with the write parameter obtained, where the default write parameter is placed in the boot loader. Method according to claim 1, characterized in that the default write parameter associates with a DQS output delay. Method according to claim 2, characterized in that the DRAM write calibration comprises: initializing the DQS output delay; gradually writing test data to the specific address in the DRAM with the DQS output delay to determine the data window for reading data from the DRAM, and incrementing the DQS output delay until the data window exceeds a threshold; and determining the resulting DQS output delay as the write parameter obtained. Method according to claim 1, characterized in that the read parameter associates with a DQS input delay. Method according to claim 1, characterized in that the DRAM write calibration is performed after a DRAM read calibration fails, and the DRAM read calibration writes test data to a specific address of DRAM. a DRAM with a default write parameter and attempts to find a read parameter for reading data from the DRAM. Parameter optimization method, performed by a microcontroller for seeking and executing instructions from a boot loader, characterized by the fact that it comprises: performing a first DRAM read calibration, where the microcontroller writes test data to an address specific to a DRAM with a default write parameter and attempts to find a read parameter for reading data from the DRAM; and perform a DRAM write calibration to update a write parameter and read parameter after the first DRAM read calibration fails. A method according to claim 6 further comprising: replacing a standard read parameter stored in non-volatile memory with the read parameter, wherein the standard read parameter is included in the first portion of the loader boot time. Method according to claim 6, characterized in that the DRAM write calibration comprises: initializing a DQS output delay; gradually write test data to a specific DRAM address with the DQS output delay, trying to find a data window for reading data from the DRAM, and increment the DQS output delay until the data window exceeds a threshold. ; determining the DQS output delay as the write parameter; and determining a DQS input delay according to the data window as the read parameter. A method according to claim 8, further comprising: replacing a default write parameter stored in non-volatile memory with the write parameter obtained, wherein the default write parameter is placed in the loader. startup. Method according to claim 8, characterized in that the resulting data window is found by the following steps: writing test data to the specific DRAM address with the obtained write parameter; set a DQ input delay to zero and a DQS input delay to zero; gradually read test data written from the specific DRAM address, and increment the DQ input delay by one step until the write test data fails to be read from the DRAM; determining steps of the DQ input delay as a first magnitude indicating a left margin of a data window on a DQ line; reset the DQ input delay to zero and the DQS input delay to zero; gradually read the test data written from the specific DRAM address, and increment the DQS input delay until the written test data fails to be read from the DRAM memory; and determining steps of the DQS input delay as a second magnitude indicating a right margin of the data window on the DQ line. Method according to claim 10, characterized in that the read parameter obtained is used to align the center of a rising edge and a falling edge of a DQS signal with a center of a data window. in the DQ line substantially. 12. Parameter optimization apparatus, characterized in that it comprises: a non-volatile memory storing a boot loader; and a microcontroller being configured to duplicate a first boot loader portion from nonvolatile memory in a Static Random Access Memory (SRAM), fetch and execute a plurality of instructions from the first boot loader portion from SRAM to perform a DRAM write calibration to obtain a write parameter, and replace the default write parameter stored in the first portion of the non-volatile memory boot loader with the write parameter. Apparatus according to claim 12, characterized in that the microcontroller is further configured to replace a default read parameter stored in non-volatile memory with the read parameter obtained, wherein the default read parameter is placed in the first portion of the boot loader. Apparatus according to claim 12, characterized in that the microcontroller is further configured to further replace the default write parameter stored in the first portion of the boot loader from the SRAM with the write parameter obtained. Apparatus according to claim 12, characterized in that the default write parameter indicates a DQS output delay. Apparatus according to claim 15, characterized in that the performance of DRAM write calibration comprises setting the DQS output delay to zero; gradually write test data to a specific DRAM address with the DQS output delay set, try to find a data window for reading data from DRAM, and increment the DQS output delay until the data window exceeds one. limit; and determining the resulting DQS output delay as the write parameter. Apparatus according to claim 12, characterized in that the microcontroller further performs DRAM write calibration after a first DRAM read calibration fails, wherein the first DRAM read calibration writes test data to is a specific address of a DRAM with a default write parameter and attempts to find a read parameter for reading data from the DRAM. Apparatus according to claim 17, characterized in that the read parameter indicates a DQS input delay. Apparatus according to claim 17, characterized in that the microcontroller is further configured to fetch and execute instructions from the first portion of the boot loader from the SRAM to perform a second DRAM read calibration with the parameter of write to get a read parameter. Apparatus according to claim 19, characterized in that the microcontroller is further configured to duplicate a second portion of the boot loader from non-volatile memory to DRAM memory upon completion of the second DRAM read calibration. . Apparatus according to claim 20, characterized in that the read parameter is used to align a center of the rising edge and the falling edge of a DQS signal with a center of a data window on the line. of DQ substantially.