CN213024374U - Test circuit for compatibility of main control chip and storage chip - Google Patents
Test circuit for compatibility of main control chip and storage chip Download PDFInfo
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- CN213024374U CN213024374U CN202021524254.0U CN202021524254U CN213024374U CN 213024374 U CN213024374 U CN 213024374U CN 202021524254 U CN202021524254 U CN 202021524254U CN 213024374 U CN213024374 U CN 213024374U
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Abstract
The application provides a master control chip and compatible test circuit of memory chip, apply to memory chip test technical field, with XU4 platform, master control chip and memory chip all install and carry out the test of inside line of walking in same circuit, test circuit includes XU4 platform module and test platform module, through XU4 platform module and test platform module electric current and data conduction, with the mode transmission signal that solves XU4 platform through external connection to master control chip and NAND Flash slow technical problem of speed rate in the time, get rid of the use of external signal line, promote data transmission rate.
Description
Technical Field
The present application relates to the field of memory chip testing technologies, and in particular, to a circuit for testing compatibility between a main control chip and a memory chip.
Background
For compatibility verification of the main control chip and the NAND Flash (non-volatile Flash memory chip), the verification method is that an instruction is input to the main control chip through an XU4 platform, and the NAND Flash is controlled through the main control chip. Under the existing conditions, the XU4 platform can only be connected with the main control chip and the NAND Flash in an external wiring mode, but the external wiring has great interference on signals, and the data transmission rate can only reach about 50 MHz.
For the problem of large external wiring signal interference, the following reasons are summarized:
1. the dupont line is too long, which can attenuate signals;
2. the transmission rate of signals is affected by different DuPont wire lengths and different impedances;
3. the dupont line has poor quality and can affect the signal.
Disclosure of Invention
The application provides a compatible test circuit of main control chip and memory chip solves XU4 platform and transmits the too slow technical problem of speed when mode through the outside wiring to main control chip and NAND Flash, gets rid of the use of external signal line, promotes data transmission rate.
The application adopts the following technical means for solving the technical problems:
the application provides a pair of master control chip and compatible test circuit of memory chip, all install XU4 platform, master control chip and memory chip and carry out the test of inside line of walking in same circuit, test circuit includes:
the XU4 platform module comprises a CPU processor, a data transmission circuit, a storage medium, a power supply module, a first connecting seat and a second connecting seat, wherein the data transmission circuit is connected with the storage medium in series and is connected with the CPU processor, a first pin of the power supply module is connected with the CPU processor, a second pin of the power supply module is connected with the first connecting seat, and the CPU processor is connected with the second connecting seat;
the test platform module comprises a power supply conversion circuit, a master control chip, an object socket to be tested, a third connecting seat and a fourth connecting seat, wherein the third connecting seat is connected with the first connecting seat through an I/O (input/output) line and a power line, the fourth connecting seat is connected with the second connecting seat through an I/O line, the third connecting seat is connected with the power supply conversion circuit through an I/O line and a power line, the power supply conversion circuit is respectively connected with the master control chip and the object socket to be tested, the fourth connecting seat is connected with the master control chip, and the master control chip is connected with the object socket to be tested.
Further, the data transmission circuit is connected with an external PC terminal.
Furthermore, the storage medium comprises a burning circuit and a storage device, and the burning circuit and the storage device are respectively connected with the CPU processor, the data transmission circuit and the power module.
Furthermore, the burning circuit is connected with an external PC end.
Further, the power conversion circuit includes a first voltage conversion circuit and a second voltage conversion circuit;
the first voltage conversion circuit comprises a first transformer U2 and a plurality of capacitors, a 1 st pin of the first transformer U2 is connected with a third connecting seat to access a load current with 5V voltage, a 5 th pin of the first transformer U2 is connected with a main control chip and an object socket in series to output a load current with 3.3V, and the capacitors are connected in parallel and respectively connected to the 1 st pin or the 5 th pin of the first transformer U2;
the second volt conversion circuit comprises a second transformer U3 and a plurality of capacitors, a 1 st pin of the second transformer U3 is connected with a third connecting seat to be connected with a load current of 5V voltage, a 5 th pin of the second transformer U3 is connected with a main control chip in series to output the load current of 1.8V, and the capacitors are connected to the 1 st pin or the 5 th pin of the second transformer U3 in parallel respectively.
Further, the test platform module further comprises a reset button, and the reset button is connected with the main control chip.
The application provides a master control chip and memory chip compatible test circuit has following beneficial effect:
the application provides a pair of master control chip and compatible test circuit of memory chip all installs XU4 platform, master control chip and memory chip and carries out the test of inside line of walking in same circuit, and test circuit includes:
the XU4 platform module comprises a CPU processor, a data transmission circuit, a storage medium, a power supply module, a first connecting seat and a second connecting seat, wherein the data transmission circuit is connected with the storage medium in series and is connected with the CPU processor;
the test platform module comprises a power supply conversion circuit, a main control chip, an object socket to be tested, a third connecting seat and a fourth connecting seat, wherein the third connecting seat is connected with the first connecting seat through an I/O (input/output) line and a power line, the fourth connecting seat is connected with the second connecting seat through an I/O line, the third connecting seat is connected with the power supply conversion circuit through an I/O line and a power line, the power supply conversion circuit is respectively connected with the main control chip and the object socket to be tested, the fourth connecting seat is connected with the main control chip, and the main control chip is connected with the object socket to be tested.
The technical problem that the speed is too low when the XU4 platform transmits signals to the main control chip and the NAND Flash in an external wiring mode is solved, the use of an external signal line is eliminated, and the data transmission speed is improved; in addition, the master control chip and the NAND Flash to be tested are combined on the same circuit, the wire length is reduced in an internal wiring mode when the PCB is drawn, and meanwhile, the equal-length and equal-width processing is carried out on each data transmission line and each clock signal line, so that the transmission quality of signals is improved; the Socket is used for loading NAND Flash to replace a direct welding mode, so that the test board can be used for multiple times, and the use value is improved; the connecting seat capable of being directly connected to the XU4 platform is adopted, so that the signal transmission in an external wiring mode is avoided, and the signal quality is improved.
Drawings
FIG. 1 is a schematic circuit block diagram of an embodiment of a circuit for testing compatibility between a main control chip and a memory chip according to the present invention;
fig. 2 is a circuit diagram of a power conversion circuit according to an embodiment of a test circuit for compatibility between a main control chip and a memory chip.
The implementation, functional features and advantages of the present application will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It is noted that the terms "comprises," "comprising," and "having" and any variations thereof in the description and claims of this application and the drawings described above are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus. In the claims, the description and the drawings of the specification of the present application, relational terms such as "first" and "second", and the like, may be used solely to distinguish one entity/action/object from another entity/action/object without necessarily requiring or implying any actual such relationship or order between such entities/actions/objects.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Referring to fig. 1, a circuit diagram of a circuit for testing compatibility between a main control chip 115 and a memory chip in an embodiment of the present application is shown;
according to the main control chip 115 and memory chip compatibility test circuit provided by the application, the XU4 platform, the main control chip 115 and the memory chip are all installed in the same circuit to test internal wiring;
the test circuit includes:
the XU4 platform module comprises a CPU processor 106, a data transmission circuit 109, a storage medium, a power supply module 103, a first connecting seat 107 and a second connecting seat 110, wherein the data transmission circuit 109 is connected with the storage medium in series and is connected with the CPU processor 106, a first pin of the power supply module 103 is connected with the CPU processor 106, a second pin of the power supply module 103 is connected with the first connecting seat 107, and the CPU processor 106 is connected with the second connecting seat 110;
the test platform module comprises a power conversion circuit, a main control chip 115, an object socket 116 to be tested, a third connecting seat 111 and a fourth connecting seat 113, wherein the third connecting seat 111 is connected with the first connecting seat 107 through an I/O line and a power line, the fourth connecting seat 113 is connected with the second connecting seat 110 through an I/O line, the third connecting seat 111 is connected with the power conversion circuit through an I/O line and a power line, the power conversion circuit is respectively connected with the main control chip 115 and the object socket 116 to be tested, the fourth connecting seat 113 is connected with the main control chip 115, and the main control chip 115 is connected with the object socket 116 to be tested.
The data transmission circuit 109 is connected with the external PC terminal 108 to externally monitor the interactive device.
The storage medium includes a burning circuit 105 and a storage device 104, the burning circuit 105 and the storage device 104 are respectively connected to the CPU 106, the data transmission circuit 109 and the power module 103, and the burning circuit 105 is connected to the external PC terminal 108, and burns a test script into the storage device 104 for storage and record in a test process.
Referring to fig. 2, the power conversion circuit includes a first voltage conversion circuit and a second voltage conversion circuit;
the first voltage conversion circuit comprises a first transformer U2 and a plurality of capacitors, a 1 st pin of the first transformer U2 is connected with the third connecting seat 111 to be connected with a load current of 5V voltage, a 5 th pin of the first transformer U2 is connected with the main control chip and the object socket in series to output the load current of 3.3V, and the capacitors are connected to the 1 st pin or the 5 th pin of the first transformer U2 in parallel respectively;
the second volt conversion circuit comprises a second transformer U3 and a plurality of capacitors, a 1 st pin of the second transformer U3 is connected with the third connecting seat 111 to be connected with a load current of 5V voltage, a 5 th pin of the second transformer U3 is connected with the main control chip in series to output the load current of 1.8V, and the plurality of capacitors are connected to the 1 st pin or the 5 th pin of the second transformer U3 in parallel respectively.
In one embodiment, the test platform module further comprises a reset button, the reset button is connected TO the main control chip 115, and when the TO0 pin of the main control chip 115 is set TO low potential, the system will enter the test mode. In test mode, the reset button 114 is pressed and the system is reset.
The invention also provides a method for testing the compatibility of the main control chip 115 and the memory chip, which is implemented by adopting the test circuit and comprises a power supply test method and a data interaction test method, wherein,
the power supply test method comprises the following steps: the power module 103 outputs a first on-load current corresponding to 5V to the first socket 107, and the first socket 107 transmits the first on-load current from the XU4 platform 101 to the third socket 111 of the test platform 102 through the power line and the I/O line; the third connecting seat 111 correspondingly outputs the first on-load current to the power conversion module 112, the power conversion module 112 converts the first on-load current into a second on-load current of 3.3V and a third on-load current of 1.8V, outputs the second on-load current and the third on-load current to the main control chip 115, and outputs the second on-load current to the object socket 116 to be tested;
the data interaction testing method comprises the following steps: the CPU 106 outputs the test command in the emmc protocol to the second socket 110, the second socket 110 outputs the test command from the XU4 platform part 101 to the fourth socket 113 of the test platform part 102 through the I/O line, and the fourth socket 113 outputs the test command to the main control chip 115.
In one embodiment, the steps of the power conversion module 112 converting the first on-load current into a second on-load current of 3.3V and a third on-load current of 1.8V, outputting the second on-load current and the third on-load current to the main control chip 115, and outputting the second on-load current to the object under test socket 116 include:
converting the first loaded current into a second loaded current by using a first voltage-to-digital conversion circuit, and respectively outputting the second loaded current to the main control chip 115 and the socket 116 to be tested so as to supply power to the main control chip 115 and the socket 116 to be tested;
and after the main control chip 115 acquires the test instruction and the third on-load current, the test instruction is output to the socket 116 of the object to be tested through the third on-load current, and a compatibility signal correspondingly fed back by the socket 116 of the object to be tested is acquired, so that whether the main control chip 115 is compatible with the socket 116 of the object to be tested is judged.
To sum up, the application provides a compatible test circuit of main control chip 115 and memory chip, all installs XU4 platform, main control chip 115 and memory chip in same circuit and carries out the test of inside line of walking, and test circuit includes:
the XU4 platform module comprises a CPU processor 106, a data transmission circuit 109, a storage medium, a power supply module 103, a first connecting seat 107 and a second connecting seat 110, wherein the data transmission circuit 109 is connected with the storage medium in series and is connected with the CPU processor 106, a first pin of the power supply module 103 is connected with the CPU processor 106, a second pin of the power supply module 103 is connected with the first connecting seat 107, and the CPU processor 106 is connected with the second connecting seat 110;
the test platform module comprises a power conversion circuit, a main control chip 115, an object socket 116 to be tested, a third connecting seat 111 and a fourth connecting seat 113, wherein the third connecting seat 111 is connected with the first connecting seat 107 through an I/O line and a power line, the fourth connecting seat 113 is connected with the second connecting seat 110 through an I/O line, the third connecting seat 111 is connected with the power conversion circuit through an I/O line and a power line, the power conversion circuit is respectively connected with the main control chip 115 and the object socket 116 to be tested, the fourth connecting seat 113 is connected with the main control chip 115, and the main control chip 115 is connected with the object socket 116 to be tested.
The technical problem that the speed is too low when the XU4 platform transmits signals to the main control chip 115 and the NAND Flash in an external wiring mode is solved, the use of an external signal line is eliminated, and the data transmission speed is improved; in addition, the main control chip 115 and the NAND Flash to be tested are combined on the same circuit, the wire length is reduced in an internal wiring mode when the PCB is drawn, and meanwhile, the equal-length and equal-width processing is carried out on each data transmission line and each clock signal line, so that the transmission quality of signals is improved; the Socket is used for loading NAND Flash to replace a direct welding mode, so that the test board can be used for multiple times, and the use value is improved; the connecting seat capable of being directly connected to the XU4 platform is adopted, so that the signal transmission in an external wiring mode is avoided, and the signal quality is improved.
Although embodiments of the present application have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the application, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. The utility model provides a master control chip and compatible test circuit of memory chip which characterized in that, all install XU4 platform, master control chip and memory chip and carry out the test of inside line of walking in same circuit, test circuit includes:
the XU4 platform module comprises a CPU processor, a data transmission circuit, a storage medium, a power supply module, a first connecting seat and a second connecting seat, wherein the data transmission circuit is connected with the storage medium in series and is connected with the CPU processor, a first pin of the power supply module is connected with the CPU processor, a second pin of the power supply module is connected with the first connecting seat, and the CPU processor is connected with the second connecting seat;
the test platform module comprises a power supply conversion circuit, a master control chip, an object socket to be tested, a third connecting seat and a fourth connecting seat, wherein the third connecting seat is connected with the first connecting seat through an I/O (input/output) line and a power line, the fourth connecting seat is connected with the second connecting seat through an I/O line, the third connecting seat is connected with the power supply conversion circuit through an I/O line and a power line, the power supply conversion circuit is respectively connected with the master control chip and the object socket to be tested, the fourth connecting seat is connected with the master control chip, and the master control chip is connected with the object socket to be tested.
2. The main control chip and memory chip compatibility test circuit of claim 1, wherein the data transmission circuit is connected to an external PC terminal.
3. The main control chip and memory chip compatibility test circuit as claimed in claim 1, wherein the storage medium comprises a burning circuit and a storage device, and the burning circuit and the storage device are respectively connected to the CPU processor, the data transmission circuit and the power module.
4. The main control chip and memory chip compatibility test circuit as claimed in claim 3, wherein the burning circuit is connected to an external PC terminal.
5. The main control chip and memory chip compatibility test circuit according to claim 1, wherein the power conversion circuit comprises a first voltage conversion circuit and a second voltage conversion circuit;
the first voltage conversion circuit comprises a first transformer U2 and a plurality of capacitors, a 1 st pin of the first transformer U2 is connected with a third connecting seat to access a load current with 5V voltage, a 5 th pin of the first transformer U2 is connected with a main control chip and an object socket in series to output a load current with 3.3V, and the capacitors are connected in parallel and respectively connected to the 1 st pin or the 5 th pin of the first transformer U2;
the second volt conversion circuit comprises a second transformer U3 and a plurality of capacitors, a 1 st pin of the second transformer U3 is connected with a third connecting seat to be connected with a load current of 5V voltage, a 5 th pin of the second transformer U3 is connected with a main control chip in series to output the load current of 1.8V, and the capacitors are connected to the 1 st pin or the 5 th pin of the second transformer U3 in parallel respectively.
6. The main control chip and memory chip compatibility test circuit according to claim 1, wherein the test platform module further comprises a reset button, and the reset button is connected with the main control chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021524254.0U CN213024374U (en) | 2020-07-27 | 2020-07-27 | Test circuit for compatibility of main control chip and storage chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202021524254.0U CN213024374U (en) | 2020-07-27 | 2020-07-27 | Test circuit for compatibility of main control chip and storage chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114550795A (en) * | 2022-03-24 | 2022-05-27 | 深圳市耀星微电子有限公司 | Platform development system for testing LPDDR4 particles and control method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114550795A (en) * | 2022-03-24 | 2022-05-27 | 深圳市耀星微电子有限公司 | Platform development system for testing LPDDR4 particles and control method |
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