CN215005739U

CN215005739U - Bus board level protocol verification circuit

Info

Publication number: CN215005739U
Application number: CN202120742248.0U
Authority: CN
Inventors: 宋晓荣; 张大伟; 屈粮富; 马慧娟
Original assignee: Tianjin Puzhixin Network Measurement And Control Technology Co ltd
Current assignee: Tianjin Puzhixin Network Measurement And Control Technology Co ltd
Priority date: 2021-04-12
Filing date: 2021-04-12
Publication date: 2021-12-03
Anticipated expiration: 2031-04-12

Abstract

A bus board level protocol verification circuit comprises a test mother board and a daughter board interface circuit, wherein the test mother board comprises an NI board circuit and a relay control circuit; the NI board card circuit and the relay control circuit are connected with the daughter board interface circuit; the relay control circuit comprises an expansion chip for expanding a channel, and the relay control circuit controls and switches an external relay to complete different test contents and reduce the waste of resources; the digital channels of the NI board card circuit are all subjected to equal length processing in the PCB, so that the problem that signal testing or testing item testing is unstable due to different signal transmission time caused by the length between signal lines of high-speed signals is avoided.

Description

Bus board level protocol verification circuit

Technical Field

The utility model belongs to the technical field of bus board level test technique and specifically relates to a bus board level agreement verification circuit.

Background

The 1553B bus board-level protocol chip is a data bus with determinability and reliable transmission, and is widely applied to the fields of airplanes, vehicles, ship-borne carriers and the like; the 1553B bus board level protocol chip mainly comprises three aspects: the system comprises a remote terminal, a bus controller and a bus monitor; different 1553B bus board level protocol chips have different test contents; the same test content is uniformly carried out on the chips in the market, so that the resource waste is caused, and the NI board card is easy to have the unstable test condition of the test items; therefore, the utility model discloses a to three kinds of chips under test of 61580, 65170 and 63825, need select different test function according to the different functions of chip, and guarantee the stable circuit of NI integrated circuit board test.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to overcome prior art's not enough, provide a bus board level agreement verification circuit.

The utility model provides a its technical problem take following technical scheme to realize:

a bus board level protocol verification circuit comprises a test motherboard, wherein the test motherboard comprises an NI board circuit and a relay control circuit, an NI case is electrically connected with the test motherboard, and the NI case transmits and controls signals of the test motherboard.

Preferably, the NI card connector further comprises a daughter board interface circuit, wherein the daughter board interface circuit comprises a connector, and the NI card circuit is connected to the daughter board interface circuit.

Preferably, the relay control circuit is connected with the daughter board interface circuit, the relay control circuit comprises an expansion chip for expanding the channel, and the relay control circuit controls and switches the external relay to complete different test contents and reduce resource waste.

Preferably, the daughter board interface circuit is connected to a source test instrument, and the model of the source test instrument is PXIe-4139.

Preferably, the daughter board interface circuit comprises an oscilloscope interface circuit, the oscilloscope is connected with the oscilloscope interface circuit through an SMA cable, and the SMA cable adopts a high-speed cable to avoid the test signal distortion phenomenon caused by cable attenuation.

Preferably, the oscilloscope interface circuit comprises a jump cap, and the oscilloscope can be switched on selectively according to needs.

Preferably, the NI board circuit includes two digital boards; the type of the digital board card is PXIe-6571.

Preferably, the connector model is TFM-150-12-L-D-A.

Preferably, the digital channels of the NI board card circuit are all processed in the PCB in equal length, so that the problem that signal test or test item test is unstable due to different signal transmission time caused by the length between signal lines of high-speed signals is avoided.

Preferably, the daughter board interface circuit is connected to the chip to be tested through a test daughter board.

The utility model has the advantages that:

1. the utility model relates to a bus board level agreement verification circuit, including test mother board, daughter board interface circuit, the test mother board includes NI integrated circuit board circuit and relay control circuit, NI machine case with the test mother board electric connection, the NI machine case carries out transmission control with the signal of test mother board; the NI board card circuit and the relay control circuit are connected with the daughter board interface circuit; the relay control circuit comprises an expansion chip used for expanding a channel, and the relay control circuit controls and switches an external relay to complete different test contents and reduce resource waste.

2. The utility model discloses in equal length processing is all done to NI integrated circuit board circuit's digital channel in PCB, avoids because high-speed signal arouses signal transmission time different because length between the signal line to cause signal test or test item test unstable.

Drawings

Fig. 1 is a circuit connection block diagram of the present invention;

fig. 2 is a circuit connection diagram of the NI board of the present invention;

FIG. 3 is a daughter board interface circuit connection diagram of the present invention;

fig. 4 is a connection diagram of the relay control circuit of the present invention;

FIG. 5 is a connection diagram of the interface circuit of the oscilloscope of the present invention;

fig. 6 is a circuit diagram of a transformer module according to the present invention;

fig. 7 is a connection diagram of a relay module according to the present invention;

fig. 8 is a connection diagram of the daughter board chip according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As shown in fig. 1 and fig. 2, a circuit is verified to bus board level agreement, including the test motherboard, the test motherboard includes NI integrated circuit board circuit and relay control circuit, NI machine case with test motherboard electric connection, NI machine case will the signal of test motherboard transmits control.

Furthermore, the digital channels of the NI board card circuit are all subjected to equal length processing in the PCB, so that the problem that signal testing or test item testing is unstable due to different signal transmission time caused by the length between signal lines of high-speed signals is avoided.

Further, as shown in fig. 3, the NI card further includes a daughter board interface circuit, where the daughter board interface circuit includes a connector, and the NI card circuit is connected to the daughter board interface circuit; specifically, the connector model is TFM-150-12-L-D-A; the NI board card circuit comprises two digital board cards; the type of the digital board card is PXIe-6571; the S0_ DIO pin and the S1_ DIO pin of the NI board correspond to the S0_ DIO pin and the S1_ DIO pin of the daughter board interface circuit, respectively.

Further, as shown in fig. 4, the relay control circuit is connected to the daughter board interface circuit, the relay control circuit includes an expansion chip for expanding a channel, and an external relay is controlled by the relay control circuit; specifically, the extended chip signal is PCA9056, and an S0_ IO pin of the relay control circuit is connected to an S0_ IO pin of the daughter board interface circuit.

Further, the daughter board interface circuit is connected with a source test instrument, and the model of the source test instrument is PXIe-4139.

Further, as shown in fig. 5, the daughter board interface circuit includes an oscilloscope interface circuit, the oscilloscope is connected to the oscilloscope interface circuit through an SMA cable, and the SMA cable adopts a high-speed cable, so as to avoid a test signal distortion phenomenon caused by cable attenuation; the oscilloscope interface circuit comprises a jump cap, and the oscilloscope can be switched in according to the requirement.

Further, as shown in fig. 6, a test daughter board is also included; the test daughter board comprises a transformer module circuit connected with the oscilloscope interface circuit, wherein the model of the transformer module circuit is PM-DB2725EX, and the transformer module circuit is used for adjusting the voltage ratio between the test daughter board and the tested chip.

Specifically, the test daughter board chip is BU 61580; the S0_ DIO pin and the S1_ DIO pin of the test daughter board chip are respectively and correspondingly connected with the S0_ DIO pin and the S1_ DIO pin of the daughter board interface circuit; the JP _ TP1A _ XA pin, the JP _ TP1A _ XB pin and the JP _ TP1A _ XC pin of the transformer module circuit are respectively and correspondingly connected with the JP _ TP1A _ XA pin, the JP _ TP1A _ XB pin and the JP _ TP1A _ XC pin of the oscilloscope interface circuit.

Further, as shown in fig. 7, the test daughter board further includes a relay module, where the relay module is mainly used to switch the chip to be tested and the test resources, and since the oscilloscope channel or the signal generator channel is not enough, the relay module is required to switch the resources for measurement.

Further, as shown in fig. 8, the test daughter board is connected to the chip to be tested; the tested chip is based on a 1553B protocol, and the model number of the tested chip is 61580, 65170 and 63825.

The working principle is as follows:

the NI case is electrically connected with the test motherboard, and the NI case transmits and controls signals of the test motherboard;

2. the NI board card circuit and the relay control circuit are connected with the daughter board interface circuit; the relay control circuit comprises an expansion chip for expanding a channel, and the relay control circuit controls and switches an external relay to complete different test contents and reduce the waste of resources;

3. the digital channels of the NI board card circuit are all subjected to equal length processing in the PCB, so that the problem that signal testing or testing item testing is unstable due to different signal transmission time caused by the length between signal lines of high-speed signals is avoided.

The utility model relates to a bus board level agreement verification circuit, including test mother board, daughter board interface circuit, the test mother board includes NI integrated circuit board circuit and relay control circuit, NI machine case with the test mother board electric connection, the NI machine case carries out transmission control with the signal of test mother board; the NI board card circuit and the relay control circuit are connected with the daughter board interface circuit; the relay control circuit comprises an expansion chip for expanding a channel, and the relay control circuit controls and switches an external relay to complete different test contents and reduce the waste of resources; the digital channels of the NI board card circuit are all subjected to equal length processing in the PCB, so that the problem that signal testing or testing item testing is unstable due to different signal transmission time caused by the length between signal lines of high-speed signals is avoided.

The above description is for the detailed description of the preferred possible embodiments of the present invention, but the embodiments are not intended to limit the scope of the present invention, and all equivalent changes or modifications accomplished under the technical spirit suggested by the present invention should fall within the scope of the present invention.

Claims

1. A bus board level protocol validation circuit, comprising: the test motherboard comprises an NI board card circuit and a relay control circuit, an NI case is electrically connected with the test motherboard, and the NI case transmits and controls signals of the test motherboard.

2. The bus board level protocol authentication circuit of claim 1, wherein: the NI board card circuit is characterized by further comprising a daughter board interface circuit, wherein the daughter board interface circuit comprises a connector, and the NI board card circuit is connected with the daughter board interface circuit.

3. The bus board level protocol validation circuit of claim 2, wherein the daughter board interface circuit is coupled to the chip under test via a test daughter board.

4. The bus board level protocol validation circuit of claim 2, wherein the digital channels of the NI board circuit are all processed with equal length in the PCB, so as to avoid unstable signal test or test item test caused by different signal transmission time due to the length between signal lines of high-speed signals.

5. The bus board level protocol authentication circuit of claim 2, wherein: the relay control circuit is connected with the daughter board interface circuit and comprises an expansion chip used for expanding a channel, and the relay control circuit controls and switches an external relay to complete different test contents and reduce resource waste.

6. The bus board level protocol authentication circuit of claim 2, wherein: the daughter board interface circuit is connected with a source test instrument, and the model of the source test instrument is PXIe-4139.

7. The bus board level protocol authentication circuit of claim 2, wherein: the daughter board interface circuit comprises an oscilloscope interface circuit, the oscilloscope is connected with the oscilloscope interface circuit through an SMA cable, and the SMA cable adopts a high-speed cable to avoid the test signal distortion phenomenon caused by cable attenuation.

8. The bus board level protocol authentication circuit of claim 7, wherein: the oscilloscope interface circuit comprises a jump cap, and the oscilloscope can be switched in according to the requirement.

9. The bus board level protocol authentication circuit of claim 1, wherein: the NI board card circuit comprises two digital board cards; the type of the digital board card is PXIe-6571.

10. The bus board level protocol authentication circuit of claim 2, wherein the connector model is TFM-150-12-L-D-A.