CN214753706U - Semiconductor packaging structure - Google Patents
Semiconductor packaging structure Download PDFInfo
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- CN214753706U CN214753706U CN202121046088.2U CN202121046088U CN214753706U CN 214753706 U CN214753706 U CN 214753706U CN 202121046088 U CN202121046088 U CN 202121046088U CN 214753706 U CN214753706 U CN 214753706U
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- enclose
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Abstract
The utility model discloses a semiconductor packaging structure, packaging structure include the base, be equipped with on the base and enclose the plywood, enclose and be equipped with the blotter in closing the inboard, enclose and be equipped with the lead wire on one side of the board, be equipped with the preforming on the lead wire, be equipped with the upper cover on the base, be equipped with the indent in the upper cover, be equipped with heat dissipation silicone grease in the indent, cover on and be equipped with the fin. The utility model discloses packaging structure is provided with blotter and supporting pad, and the blotter prevents that the chip from causing the skew because of vibrations when using, encloses to close board and indent and effectively protected the chip, prevents that the dust from getting into and the chip drops from top to bottom, is equipped with the shock pad and prevents the hard joint, plays good buffering effect, and heat dissipation silicone grease contacts chip upper portion and carries out heat-conduction, and the fin radiating effect is good.
Description
Technical Field
The utility model relates to a semiconductor package technical field specifically is a semiconductor packaging structure.
Background
In the semiconductor production process, I C chips are protected and external electrical connection is provided to prevent damage of external force or environmental factors in the transportation and placement processes, besides, the integrated circuit assembly also needs to be combined with passive components such as resistors and capacitors into a system to play a given function, and the electronic package is used for establishing the protection and organization structure of the integrated circuit assembly, and the conventional package structure is inconvenient to disassemble and assemble and poor in heat dissipation effect. In view of this situation, a semiconductor package structure is proposed.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a semiconductor package structure can effectively solve above-mentioned problem, the utility model discloses package structure is provided with blotter and supporting pad, and the blotter prevents that the chip from causing the skew because of vibrations when using, encloses to close board and indent and has effectively protected the chip, prevents that the dust from getting into and the chip drops from top to bottom, is equipped with the shock pad and prevents the hard joint, plays good buffering effect, and heat dissipation silicone grease contacts chip upper portion and carries out heat-conduction, and the fin radiating effect is good.
The purpose of the utility model can be realized by the following technical scheme:
the utility model provides a semiconductor packaging structure, packaging structure includes the base, be equipped with on the base and enclose the plywood, enclose and be equipped with the blotter in closing the inboard, enclose and close board one side and be equipped with the lead wire, be equipped with the preforming on the lead wire, be equipped with the upper cover on the base, be equipped with the indent in the upper cover, be equipped with heat dissipation silicone grease in the indent, cover on and be equipped with the fin.
Furthermore, first holes distributed in an array mode are formed in the base, shock absorption pads are arranged below the first holes, limiting blocks are arranged on two sides of the enclosing plate, an installation groove is formed in the enclosing plate, a first groove is formed in one side of the installation groove, a second groove is formed in one side of the shock absorption pads, and contacts distributed in an array mode are arranged on the installation groove;
furthermore, the side face of the mounting groove is provided with a lead, one end of the pressing sheet is provided with a pin strip, the pin strip is connected with the PCB, the pressing sheet presses the lead, and two ends of the pressing sheet are fixed on the base.
Further, be equipped with the chip in the blotter, the chip is placed in the mounting groove, and chip bottom stitch and contact.
Further, the upper cover is provided with symmetrically distributed supporting pads, a third groove is formed between the supporting pads, the radiating fins are fixed in the third groove, a pressing block is arranged on one side of the pressing groove, limiting grooves are formed in two ends of the pressing groove, the upper cover is further provided with second holes distributed in an array mode, and fixing screws are arranged in the second holes.
The utility model has the advantages that:
the utility model discloses packaging structure is provided with blotter and supporting pad, and the blotter prevents that the chip from causing the skew because of vibrations when using, encloses to close board and indent and effectively protected the chip, prevents that the dust from getting into and the chip drops from top to bottom, is equipped with the shock pad and prevents the hard joint, plays good buffering effect, and heat dissipation silicone grease contacts chip upper portion and carries out heat-conduction, and the fin radiating effect is good.
Drawings
The present invention will be further described with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an explosion structure of the packaging structure of the present invention;
FIG. 2 is a schematic view of the structure of the package structure of the present invention;
FIG. 3 is a schematic cross-sectional view of the package structure of the present invention;
FIG. 4 is a schematic view of the base structure of the present invention;
FIG. 5 is a schematic view of the structure of the upper cover of the present invention;
fig. 6 is a schematic view of the structure of the upper cover of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "open hole", "upper", "lower", "thickness", "top", "middle", "length", "inner", "around", and the like, indicate positional or positional relationships, are merely for convenience in describing the present invention and to simplify the description, and do not indicate or imply that the components or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention.
Referring to fig. 1 to 6, a semiconductor package structure includes a base 1, a surrounding plate 13 is disposed on the base 1, a buffer 14 is disposed in the surrounding plate 13, a lead 16 is disposed on one side of the surrounding plate 13, a pressing sheet 17 is disposed on the lead 16, an upper cover 2 is disposed on the base 1, a pressing groove 28 is disposed in the upper cover 2, a heat dissipation silicone grease 29 is disposed in the pressing groove 28, and a heat sink 24 is disposed on the upper cover 2.
The base 1 is provided with first holes 11 distributed in an array manner, a shock pad 18 is arranged below the first holes 11, two sides of the enclosing plate 13 are provided with limit blocks 12, an installation groove 131 is arranged in the enclosing plate 13, a first open groove 132 is arranged on one side of the installation groove 131, a second open groove 141 is arranged on one side of the buffer pad 14, and contacts 135 distributed in an array manner are arranged on the installation groove 131;
the side of the mounting groove 131 is provided with a lead 16, one end of the pressing sheet 17 is provided with a pin strip 161, the pin strip 161 is connected with the PCB, the pressing sheet 17 presses the lead 16, and two ends of the pressing sheet 17 are fixed on the base 1.
The chip 3 is arranged in the buffer pad 14, the chip 3 is placed in the mounting groove 131, and pins at the bottom of the chip 3 are in contact with the contacts 135.
Be equipped with symmetric distribution's supporting pad 21 on the upper cover 2, be equipped with third open slot 22 between the supporting pad 21, fin 24 is fixed in third open slot 22, and indent 28 one side is equipped with briquetting 23, and indent 28 both ends all are equipped with spacing groove 27, still are equipped with array distribution's second trompil 25 on the upper cover 2, are equipped with set screw 26 in the second trompil 25, and set screw 26 passes second trompil 25, first trompil 11 is fixed on the PCB board.
During the use, place chip 3 in mounting groove 131, chip 3 bottom stitch and contact 135 welding, place blotter 14 between chip 3 and mounting groove 131, blotter 14 plays the cushioning effect, be connected pin strip 161 and PCB board, fixed preforming 17, preforming 17 pushes down lead 16 and prevents that lead 16 from raising the line, cover upper cover 2 on base 1, stopper 12 is installed in spacing groove 27, briquetting 23 pushes down preforming 17, indent 28 lid is on enclosing board 13, heat-conduction is carried out on heat dissipation silicone grease 29 contact chip upper portion, the fin 24 heat dissipation, the supporting pad 21 height is higher than fin 24, the shrouding pushes down fin 24 when preventing to pack, reduce the radiating effect, shock pad 18 and PCB board contact are placed, fixed screw 26 fixes base 1, upper cover 2 on the PCB board.
In the description herein, references to the description of "one embodiment," "an example," "a specific example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the above embodiments, and that the foregoing embodiments and descriptions are provided only to illustrate the principles of the present invention without departing from the spirit and scope of the present invention.
Claims (5)
1. The utility model provides a semiconductor packaging structure, packaging structure includes base (1), its characterized in that, be equipped with on base (1) and enclose plywood (13), enclose and be equipped with blotter (14) in plywood (13), enclose plywood (13) one side and be equipped with lead wire (16), be equipped with preforming (17) on lead wire (16), be equipped with upper cover (2) on base (1), be equipped with indent (28) in upper cover (2), be equipped with heat dissipation silicone grease (29) in indent (28), be equipped with fin (24) on upper cover (2).
2. The semiconductor package structure according to claim 1, wherein the base (1) is provided with first openings (11) distributed in an array manner, a shock absorbing pad (18) is disposed below the first openings (11), two sides of the enclosing plate (13) are provided with the limiting blocks (12), an installation groove (131) is disposed in the enclosing plate (13), one side of the installation groove (131) is provided with a first slot (132), one side of the shock absorbing pad (14) is provided with a second slot (141), and the installation groove (131) is provided with contacts (135) distributed in an array manner.
3. The semiconductor package structure of claim 2, wherein a lead (16) is disposed on a side surface of the mounting groove (131), a lead bar (161) is disposed at one end of the pressing plate (17), the lead bar (161) is connected to the PCB, the pressing plate (17) presses the lead (16), and both ends of the pressing plate (17) are fixed to the base (1).
4. The semiconductor package structure of claim 1, wherein the cushion pad (14) is provided with a chip (3), the chip (3) is placed in the mounting groove (131), and pins at the bottom of the chip (3) are in contact with the contacts (135).
5. The semiconductor package structure according to claim 1, wherein the top cover (2) is provided with symmetrically distributed support pads (21), third slots (22) are formed between the support pads (21), the heat sink (24) is fixed in the third slots (22), a pressing block (23) is arranged on one side of the pressing groove (28), two ends of the pressing groove (28) are provided with limit grooves (27), the top cover (2) is further provided with second holes (25) distributed in an array, and fixing screws (26) are arranged in the second holes (25).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121046088.2U CN214753706U (en) | 2021-05-14 | 2021-05-14 | Semiconductor packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121046088.2U CN214753706U (en) | 2021-05-14 | 2021-05-14 | Semiconductor packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214753706U true CN214753706U (en) | 2021-11-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121046088.2U Active CN214753706U (en) | 2021-05-14 | 2021-05-14 | Semiconductor packaging structure |
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| CN (1) | CN214753706U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117174602A (en) * | 2022-03-03 | 2023-12-05 | 王广云 | Semiconductor packaging structure and process |
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2021
- 2021-05-14 CN CN202121046088.2U patent/CN214753706U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117174602A (en) * | 2022-03-03 | 2023-12-05 | 王广云 | Semiconductor packaging structure and process |
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