JPH06275775A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06275775A
JPH06275775A JP5081102A JP8110293A JPH06275775A JP H06275775 A JPH06275775 A JP H06275775A JP 5081102 A JP5081102 A JP 5081102A JP 8110293 A JP8110293 A JP 8110293A JP H06275775 A JPH06275775 A JP H06275775A
Authority
JP
Japan
Prior art keywords
unit
semiconductor device
semiconductor
semiconductor element
module plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5081102A
Other languages
Japanese (ja)
Other versions
JP2842753B2 (en
Inventor
Katsumasa Hashimoto
克正 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5081102A priority Critical patent/JP2842753B2/en
Publication of JPH06275775A publication Critical patent/JPH06275775A/en
Application granted granted Critical
Publication of JP2842753B2 publication Critical patent/JP2842753B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To acquire a semiconductor device which enables adoption to a space mount device by raising package density of a semiconductor element and by improving-resistant properties and heat resistance. CONSTITUTION:The title device is constituted of a unit 20 wherein a semiconductor element 1 is mounted on plate-like module plate and connection patterns 13, 14 connected to the semiconductor element are provided to a front and rear thereof and an anisotropic conductive buffer member 21 which electrically connects the connection patterns 13, 14 mutually. Since a plurality of units 20 are laminated and a lamination structure is realized by inserting the anisotropic conductive buffer member 21 between the units 20, package density of the semiconductor element 1 is improved and vibration-resistant properties are improved by absorbing vibration into the buffer member 21. Heat of the semiconductor element 1 is dissipated through the module plate and heat resistance is improved.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を積層して高
密度大容量化したマルチチップ半導体装置に関し、特に
耐振動性と耐熱性が要求される宇宙搭載機器に適用され
る半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-chip semiconductor device in which semiconductor elements are stacked to have a high density and a large capacity, and more particularly to a semiconductor device applied to space-mounted equipment which requires vibration resistance and heat resistance.

【0002】[0002]

【従来の技術】近年、半導体装置の高密度大容量化を図
るために、複数の半導体素子を厚さ方向に積層した半導
体装置が提案されている。例えば、特開平2−1981
48号公報に記載されたものは、図5に示すように、半
導体素子31をTAB(テープ・オートメイテッド・ボ
ンディング)テープ32に搭載してTAB装置30を形
成するとともに、このTAB装置30と略厚さ寸法が等
しい厚さで方形枠状に形成したコネクタ33内にTAB
装置30を搭載する。そして、このTAB装置30を搭
載した複数個のコネクタ33を積層し、かつ上下のコネ
クタ33の周辺部の表裏面に設けた導電体34を相互的
に接続することで、各半導体素子31間での電気接続を
行い、所要の回路を構築する構成とされている。このよ
うな構成を例えば、マザーボード22に搭載し、接続用
パターン23に導電体34を接続することにより、複数
の半導体素子を実装して半導体装置を構成するマザーボ
ードにおける半導体素子の占有面積を低減し、半導体装
置の高密度化、大容量化を実現することができる。ま
た、コネクタを用いることにより、積層する半導体素子
の相互干渉を防止し、かつ半導体素子間の電気接続を任
意に行うことが可能となる。
2. Description of the Related Art Recently, in order to increase the density and capacity of a semiconductor device, a semiconductor device in which a plurality of semiconductor elements are stacked in the thickness direction has been proposed. For example, Japanese Patent Laid-Open No. 2-1981
As disclosed in Japanese Patent Laid-Open No. 48, as shown in FIG. 5, a semiconductor element 31 is mounted on a TAB (Tape Automated Bonding) tape 32 to form a TAB device 30. The TAB is formed in the rectangular frame-shaped connector 33 having the same thickness.
The device 30 is mounted. Then, by stacking a plurality of connectors 33 on which the TAB device 30 is mounted and interconnecting conductors 34 provided on the front and back surfaces of the peripheral portions of the upper and lower connectors 33, the semiconductor elements 31 are connected to each other. The electrical connection is made to build a required circuit. By mounting such a configuration on the mother board 22 and connecting the conductor 34 to the connection pattern 23, the area occupied by the semiconductor elements on the mother board on which a plurality of semiconductor elements are mounted and which constitutes a semiconductor device is reduced. Therefore, high density and large capacity of the semiconductor device can be realized. Further, by using the connector, it is possible to prevent mutual interference of the semiconductor elements to be stacked and to arbitrarily make electrical connection between the semiconductor elements.

【0003】[0003]

【発明が解決しようとする課題】図5に示した半導体装
置では、TAB装置30を搭載した複数のコネクタ33
を積層するとともに、その周辺部の導電体34を接続し
て電気接続を行っているために、積層した複数のコネク
タ33が一体的に構成されることになり、半導体装置の
全体が剛体構造となる。このため、このような半導体装
置を宇宙搭載機器に用いた場合には、機器に加えられる
衝撃がそのままコネクタ33に伝達され、コネクタを相
互に電気接続する導電体34の部分を破損してしまうお
それがある。また、衝撃に伴う振動がコネクタ33を介
してTAB装置30内に伝達され、半導体素子31を損
傷させ、或いは半導体素子31とTABテープ32との
接続部分を損傷させるおそれもある。また、前記半導体
装置では、コネクタ33を枠状に形成し、その枠内にT
AB装置30を搭載しているため、半導体装置の全体高
さを小さくできるものの、積層される半導体素子31が
相互に対向配置されることになり、各半導体素子31で
発生された熱が相互に影響を及ぼし合い、かつその熱が
コネクタ33の内部に籠もって放熱効果が低くなり、半
導体素子の耐熱性を劣化させるおそれもある。本発明の
目的は、耐振動性を改善し、かつ耐熱性を改善して宇宙
搭載機器への採用を可能にした半導体装置を提供するこ
とにある。
In the semiconductor device shown in FIG. 5, a plurality of connectors 33 equipped with the TAB device 30 are mounted.
Since a plurality of stacked connectors 33 are stacked and the conductors 34 on the periphery thereof are connected for electrical connection, the plurality of stacked connectors 33 are integrally configured, and the entire semiconductor device has a rigid structure. Become. For this reason, when such a semiconductor device is used in space-borne equipment, the impact applied to the equipment may be transmitted to the connector 33 as it is, and the conductor 34 that electrically connects the connectors to each other may be damaged. There is. Further, the vibration due to the impact may be transmitted to the inside of the TAB device 30 via the connector 33 to damage the semiconductor element 31 or the connecting portion between the semiconductor element 31 and the TAB tape 32. Further, in the semiconductor device, the connector 33 is formed in a frame shape, and the T
Since the AB device 30 is mounted, the overall height of the semiconductor device can be reduced, but the stacked semiconductor elements 31 are arranged so as to face each other, and the heat generated in each semiconductor element 31 is mutually generated. There is a risk that the heat will be exerted on each other and the heat will be trapped inside the connector 33, reducing the heat dissipation effect and deteriorating the heat resistance of the semiconductor element. An object of the present invention is to provide a semiconductor device which has improved vibration resistance and improved heat resistance and can be used in space-mounted equipment.

【0004】[0004]

【課題を解決するための手段】本発明は、板状をしたモ
ジュールプレートに半導体素子を搭載し、その表裏面に
半導体素子に接続された接続用パターンを有する単位ユ
ニットと、複数の単位ユニット間に介挿されて各単位ユ
ニットの接続用パターンを相互に電気接続する異方性導
電性の緩衝部材とで構成される。ここで、モジュールプ
レートは矩形の板状に形成され、その周辺部の表裏面に
はスルーホールにより相互に接続された接続用パターン
を有し、かつ中央部には凹部を有し、半導体素子はテー
プに支持されたリードに搭載され、かつモジュールプレ
ートの凹部に内装された状態でリードをその接続用パタ
ーンに接続する。また、異方性導電性の緩衝部材は、異
方性導電性樹脂又は異方性導電性ゴムで構成され、単位
ユニット間での衝撃、振動を吸収する。
According to the present invention, a semiconductor device is mounted on a plate-shaped module plate, and a unit unit having connection patterns connected to the semiconductor device on the front and back surfaces thereof, and a plurality of unit units. And a cushioning member of anisotropic conductivity that is interposed between the unit units and electrically connects the connection patterns of the unit units to each other. Here, the module plate is formed in a rectangular plate shape, has a connecting pattern interconnected by through holes on the front and back surfaces of its peripheral portion, and has a concave portion in the central portion, The lead is connected to the connecting pattern while being mounted on the lead supported by the tape and installed in the recess of the module plate. The anisotropic conductive buffer member is made of anisotropic conductive resin or anisotropic conductive rubber, and absorbs shock and vibration between unit units.

【0005】[0005]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例にかかる単位ユニットの1
つを示す部分分解斜視図であり、図2はその組立状態の
平面図と断面図である。これらの図において、ここで
は、実装される半導体素子として例えばベアチップ構成
のメモリデバイスが用いられており、この半導体素子1
はTABテープ2に搭載されてTAB装置10として構
成されている。TABテープ2はポリイミド樹脂からな
るフィルムキャリア3に所要パターンのリード4が形成
されており、このリードのインナーリード部に半導体素
子1が接続される。前記リード4はCuで形成され、そ
の表面にNi/Auメッキが施される。或いはCuに半
田メッキを施してある。また、半導体素子1はバンプ5
或いはフリップチップ法によりリード4に接続される。
そして、前記半導体素子1のTABテープ2側の部分は
保護樹脂6により被覆され、かつこの保護樹脂6の周辺
(ここでは対向する二辺)に前記リード4のアウターリ
ード部を突出させている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows a unit unit 1 according to an embodiment of the present invention.
FIG. 2 is a partially exploded perspective view showing one, and FIG. 2 is a plan view and a sectional view of the assembled state. In these figures, here, for example, a memory device having a bare chip configuration is used as a semiconductor element to be mounted.
Is mounted on the TAB tape 2 and configured as a TAB device 10. The TAB tape 2 has a lead 4 having a required pattern formed on a film carrier 3 made of a polyimide resin, and the semiconductor element 1 is connected to an inner lead portion of the lead. The lead 4 is made of Cu, and its surface is plated with Ni / Au. Alternatively, Cu is plated with solder. In addition, the semiconductor element 1 has bumps 5
Alternatively, it is connected to the lead 4 by the flip chip method.
The portion of the semiconductor element 1 on the TAB tape 2 side is covered with a protective resin 6, and the outer lead portions of the leads 4 are projected around the protective resin 6 (here, two opposite sides).

【0006】また、前記TAB装置10はモジュールプ
レート11に搭載される。モジュールプレート11は前
記TAB装置10よりも若干厚い絶縁性の板材を前記T
AB装置10よりも一回り大きな矩形に形成し、その周
辺部を残した中央部分に凹部12を形成する。また、周
辺部の対向二辺には、その表裏面にそれぞれ導体膜から
なる接続用パターン13,14を形成している。これら
表裏面の各接続用パターン13,14は、モジュールプ
レート11の厚さ方向に形成したスルーホール15によ
り選択的に電気接続が行われる。また、周辺部の表面の
2箇所には、後述するように複数個のモジュールプレー
ト11を重ねる際の位置決めに利用される位置決めマー
ク16が設けられる。なお、モジュールプレート11の
素材は耐熱性が高く、しかも可及的に熱伝導性の良いも
のが使用される。
The TAB device 10 is mounted on the module plate 11. The module plate 11 is made of an insulating plate material that is slightly thicker than the TAB device 10.
The rectangular shape is formed to be one size larger than the AB device 10, and the concave portion 12 is formed in the central portion except the peripheral portion. Further, connection patterns 13 and 14 made of a conductor film are formed on the front and back surfaces of the opposing two sides of the peripheral portion, respectively. The connection patterns 13 and 14 on the front and back surfaces are selectively electrically connected by the through holes 15 formed in the thickness direction of the module plate 11. Positioning marks 16 used for positioning when stacking a plurality of module plates 11 are provided at two locations on the surface of the peripheral portion, as described later. The module plate 11 is made of a material having high heat resistance and as good thermal conductivity as possible.

【0007】そして、前記TAB装置10をモジュール
プレート11に搭載する際には、TAB装置10をモジ
ュールプレート11の凹部12内に位置させた上で、熱
伝導性の高い接着剤17により半導体素子1の背面を凹
部12の内面に接続する。また、TABテープ2の対向
二辺に配列されているリード4のアウターリード部を半
田等によりモジュールプレート11の表面側の接続用パ
ターン13に接続する。これにより、TAB装置10と
モジュールプレート11からなる単位ユニット20が構
成される。
When mounting the TAB device 10 on the module plate 11, the TAB device 10 is placed in the recess 12 of the module plate 11, and the semiconductor element 1 is bonded by the adhesive 17 having high thermal conductivity. Is connected to the inner surface of the recess 12. Further, the outer lead portions of the leads 4 arranged on the two opposite sides of the TAB tape 2 are connected to the connection pattern 13 on the front surface side of the module plate 11 by soldering or the like. As a result, the unit unit 20 including the TAB device 10 and the module plate 11 is configured.

【0008】図3は前記した単位ユニット20を複数個
積層して構成した半導体装置の部分分解斜視図であり、
図4はその組立状態の断面図である。これらの図に示す
ように、半導体装置は、複数個の単位ユニット20を、
それぞれの間に矩形枠状をした緩衝部材21を介挿させ
た状態で重ねている。この緩衝部材20は比較的に厚い
異方性導電性樹脂、或いは異方性導電性ゴムで形成さ
れ、横方向には絶縁状態を保ったまま上下方向にのみ電
気を導通させる構成とされている。例えば、シリコン樹
脂を矩形枠状に形成し、このシリコン樹脂に縦縞状にカ
ーボンを混合させて複数の導電部を配列形成した、所謂
ゼブラコネクタを利用することもできる。
FIG. 3 is a partially exploded perspective view of a semiconductor device formed by stacking a plurality of the unit units 20 described above.
FIG. 4 is a sectional view of the assembled state. As shown in these figures, the semiconductor device includes a plurality of unit units 20.
The cushioning members 21 each having a rectangular frame shape are stacked between each other. The buffer member 20 is made of a relatively thick anisotropic conductive resin or anisotropic conductive rubber, and is configured to conduct electricity only in the vertical direction while maintaining an insulating state in the lateral direction. . For example, it is possible to use a so-called zebra connector in which a silicon resin is formed in a rectangular frame shape, and carbon is mixed into the silicon resin in a vertical stripe shape to form a plurality of conductive portions in an array.

【0009】これらの緩衝部材21を複数の単位ユニッ
ト20間に介挿した上で、モジュールプレート11の接
続用パターン13,14が存在しない辺領域において接
着剤により上下のモジュールプレート11と緩衝部材2
1とを相互に接着し、機械的な接続を行うとともに、モ
ジュールプレート11の接続用パターン13,14と緩
衝部材21との当接により、緩衝部材21を挟む上下の
単位ユニット20間の電気的な接続を行っている。ま
た、このように組み立てられた半導体装置は、最下段に
配設した単位ユニット20をマザーボード22に接着
し、接続用パターン14をマザーボード22の接続用パ
ターン23に電気接続を行っている。
These cushioning members 21 are inserted between a plurality of unit units 20, and then the upper and lower module plates 11 and the cushioning members 2 are bonded by an adhesive in the side regions of the module plate 11 where the connection patterns 13 and 14 do not exist.
1 and 1 are bonded to each other for mechanical connection, and the contact between the connection patterns 13 and 14 of the module plate 11 and the buffer member 21 causes electrical connection between the upper and lower unit units 20 sandwiching the buffer member 21. Making a good connection. Further, in the semiconductor device assembled in this manner, the unit unit 20 arranged at the bottom is adhered to the motherboard 22, and the connection pattern 14 is electrically connected to the connection pattern 23 of the motherboard 22.

【0010】この構成の半導体装置によれば、複数個の
半導体素子を積層した構成であるため、マザーボート2
2上に占める半導体素子の1つ当たりの占有面積を低減
し、半導体装置の高密度化、大容量化が可能となる。ま
た、各半導体素子1はTAB装置10として構成した上
でモジュールプレート11に搭載して単位ユニット化し
ているため、任意の単位ユニット20を任意の数だけ用
いて積層することで、必要な規模の半導体装置を容易に
構成することができる。
According to the semiconductor device having this structure, since the plurality of semiconductor elements are laminated, the mother boat 2
It is possible to reduce the occupied area per semiconductor element occupying on the upper surface of the semiconductor device 2 and increase the density and capacity of the semiconductor device. Further, since each semiconductor element 1 is configured as the TAB device 10 and mounted on the module plate 11 to be a unit unit, by stacking using any number of arbitrary unit units 20, a desired scale can be obtained. The semiconductor device can be easily configured.

【0011】更に、複数の単位ユニット20を積層する
場合に、モジュールプレート11間に緩衝部材21を介
挿しているため、例えば半導体装置に外部衝撃やこれに
伴う振動が加えられた場合でも、この衝撃や振動を緩衝
部材21の変形により吸収し、モジュールプレート11
及びTAB装置10内の半導体素子1にまで伝達される
ことを緩和させる。これにより、モジュールプレート1
1やTAB装置10における接続部の損傷や半導体素子
自体の損傷を防止し、耐振動性を改善することができ
る。
Further, when a plurality of unit units 20 are stacked, since the buffer member 21 is inserted between the module plates 11, even if an external impact or a vibration associated therewith is applied to the semiconductor device, for example, this The shock and vibration are absorbed by the deformation of the buffer member 21, and the module plate 11
And the transmission to the semiconductor element 1 in the TAB device 10 is alleviated. As a result, the module plate 1
1 and the damage of the connection part in the TAB device 10 and the semiconductor element itself can be prevented, and the vibration resistance can be improved.

【0012】また、各単位ユニット20では、モジュー
ルプレート11の凹部12内に半導体素子1を配設して
いるため、単位ユニット20を積層した場合でも、上下
の半導体素子が直接対向配置されることがなく、その間
には必ずモジュールプレート11の底部が存在されるこ
とになる。このため、各半導体素子1で発生した熱が直
接相互に影響し合うことはなく、また半導体素子1で発
生した熱はモジュールプレート11を介してその側面か
ら放熱されることになり、半導体素子が加熱されて損傷
を受けることを防止し、半導体装置の耐熱性を改善する
ことができる。これにより、この半導体装置を宇宙搭載
機器に用いた場合でも、高寿命で高信頼性の機器を構成
することが可能となる。
Further, in each unit unit 20, the semiconductor element 1 is arranged in the recess 12 of the module plate 11. Therefore, even when the unit units 20 are stacked, the upper and lower semiconductor elements should be directly opposed to each other. And the bottom of the module plate 11 is always present between them. Therefore, the heat generated in each semiconductor element 1 does not directly affect each other, and the heat generated in the semiconductor element 1 is radiated from the side surface through the module plate 11, so that the semiconductor elements are It is possible to prevent the semiconductor device from being damaged by being heated and improve the heat resistance of the semiconductor device. As a result, even when this semiconductor device is used in space-borne equipment, it becomes possible to construct equipment with a long life and high reliability.

【0013】なお、複数個の単位ユニットと緩衝部材と
を積層してこれらを固定する構成として、マザーボード
と最上の単位ユニットとの間を挟さみ込むクランパを用
いてもよい。このクランパにより、各単位ユニットを機
械的に接続し、かつ上下の単位ユニットと緩衝部材とを
押圧させて電気的に接続する。このクランパを用いれ
ば、接着により一体化する場合に比較して単位ユニット
の交換が容易になり、メンテナンスに有利となる。
A clamper for sandwiching the mother board and the uppermost unit unit may be used as a structure in which a plurality of unit units and the cushioning member are laminated and fixed to each other. With this clamper, the unit units are mechanically connected, and the upper and lower unit units and the cushioning member are pressed to be electrically connected. The use of this clamper facilitates replacement of the unit units, which is advantageous for maintenance, as compared with the case where they are integrated by adhesion.

【0014】[0014]

【発明の効果】以上説明したように本発明は、モジュー
ルプレートに半導体素子を搭載した構成の単位ユニット
を複数ユニット積層し、かつ各単位ユニット間にはそれ
ぞれの接続用パターンを相互に電気接続する異方性導電
性の緩衝部材を介挿した構成としているので、半導体素
子を積層構造に実装して実装密度を高める一方、単位ユ
ニットに加えられる衝撃や振動を緩衝部材によって吸収
し、半導体素子に衝撃や振動が加えられるのを防止し、
半導体装置の耐振動性を改善することができる。また、
単位ユニットを構成するモジュールプレートに凹部を設
け、この凹部内に半導体素子を内装しているため、単位
ユニットを積層した場合でも各半導体素子が直接対向さ
れずに半導体素子相互間の熱の影響が回避されるととも
に、半導体素子で発生した熱をモジュールプレートを通
して放熱することができ、半導体装置の耐熱性を改善す
ることができる。
As described above, according to the present invention, a plurality of unit units each having a semiconductor element mounted on a module plate are laminated, and respective connection patterns are electrically connected to each other. Since the configuration is such that an anisotropic conductive cushioning member is inserted, the semiconductor elements are mounted in a laminated structure to increase the packaging density, while shocks and vibrations applied to the unit units are absorbed by the cushioning member, and Prevents shock and vibration from being applied,
Vibration resistance of the semiconductor device can be improved. Also,
Since the module plate that constitutes the unit unit is provided with a concave portion and the semiconductor element is provided inside this concave portion, even when the unit units are stacked, the semiconductor elements are not directly opposed to each other and the influence of heat between the semiconductor elements is not exerted. In addition to being avoided, the heat generated in the semiconductor element can be radiated through the module plate, and the heat resistance of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置にかかる単位ユニットの部
分分解斜視図である。
FIG. 1 is a partially exploded perspective view of a unit unit according to a semiconductor device of the present invention.

【図2】図1の単位ユニットの平面図と断面図である。FIG. 2 is a plan view and a cross-sectional view of the unit unit shown in FIG.

【図3】複数個の単位ユニットで構成される半導体装置
の部分分解斜視図である。
FIG. 3 is a partially exploded perspective view of a semiconductor device including a plurality of unit units.

【図4】図3の半導体装置の組立状態の断面図である。4 is a sectional view of the semiconductor device of FIG. 3 in an assembled state.

【図5】従来の積層構造の半導体装置の一例を示す断面
図である。
FIG. 5 is a sectional view showing an example of a conventional semiconductor device having a laminated structure.

【符号の説明】[Explanation of symbols]

1 半導体素子 2 TABテープ 4 リード 10 TAB装置 11 モジュールプレート 12 凹部 13,14 接続用パターン 20 単位ユニット 21 緩衝部材(異方性導電性樹脂又はゴム) 22 マザーボード 23 接続用パターン DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 TAB tape 4 Lead 10 TAB device 11 Module plate 12 Recesses 13 and 14 Connection pattern 20 Unit unit 21 Buffer member (anisotropic conductive resin or rubber) 22 Motherboard 23 Connection pattern

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 板状をしたモジュールプレートに半導体
素子を搭載し、その表裏面に前記半導体素子に接続され
た接続用パターンを有する単位ユニットと、複数の単位
ユニット間に介挿されて前記接続用パターンを相互に電
気接続する異方性導電性の緩衝部材とを備えることを特
徴とする半導体装置。
1. A unit unit having a semiconductor element mounted on a plate-shaped module plate, the unit unit having a connection pattern connected to the semiconductor unit on the front and back surfaces thereof, and the unit unit having a plurality of unit units interposed therebetween. A semiconductor device, comprising: an anisotropic conductive cushioning member electrically connecting the working patterns to each other.
【請求項2】 モジュールプレートは矩形の板状に形成
され、その周辺部の表裏面にはスルーホールにより相互
に接続された接続用パターンを有し、かつ中央部には凹
部を有し、半導体素子はテープに支持されたリードに搭
載され、かつ前記凹部に内装された状態でリードを前記
接続用パターンに接続してなる請求項1の半導体装置。
2. The semiconductor device according to claim 1, wherein the module plate is formed in the shape of a rectangular plate, and the peripheral surfaces of the module plate have connection patterns connected to each other by through holes, and the central portion has a recess. 2. The semiconductor device according to claim 1, wherein the element is mounted on a lead supported by a tape, and the lead is connected to the connection pattern in a state of being installed in the recess.
【請求項3】 異方性導電性の緩衝部材は、異方性導電
性樹脂又は異方性導電性ゴムで構成され、単位ユニット
間での衝撃、振動を吸収する請求項1又は2の半導体装
置。
3. The semiconductor according to claim 1, wherein the anisotropic conductive cushioning member is made of anisotropic conductive resin or anisotropic conductive rubber and absorbs shock and vibration between unit units. apparatus.
JP5081102A 1993-03-17 1993-03-17 Semiconductor device Expired - Lifetime JP2842753B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5081102A JP2842753B2 (en) 1993-03-17 1993-03-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5081102A JP2842753B2 (en) 1993-03-17 1993-03-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06275775A true JPH06275775A (en) 1994-09-30
JP2842753B2 JP2842753B2 (en) 1999-01-06

Family

ID=13737028

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5081102A Expired - Lifetime JP2842753B2 (en) 1993-03-17 1993-03-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2842753B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025648A (en) * 1997-04-17 2000-02-15 Nec Corporation Shock resistant semiconductor device and method for producing same
JP2001267492A (en) * 2000-03-14 2001-09-28 Ibiden Co Ltd Manufacturing method for semiconductor module
US7165322B1 (en) 1999-03-10 2007-01-23 Micron Technology, Inc. Process of forming socket contacts
JP2008073818A (en) * 2006-09-22 2008-04-03 Murata Mfg Co Ltd Electronic component and composite electronic component

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6361150U (en) * 1986-10-13 1988-04-22
JPH0232547A (en) * 1988-07-22 1990-02-02 Matsushita Electric Ind Co Ltd Semiconductor packaging device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5766877A (en) * 1980-10-04 1982-04-23 Daichiku Co Ltd Stapler

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6361150U (en) * 1986-10-13 1988-04-22
JPH0232547A (en) * 1988-07-22 1990-02-02 Matsushita Electric Ind Co Ltd Semiconductor packaging device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6025648A (en) * 1997-04-17 2000-02-15 Nec Corporation Shock resistant semiconductor device and method for producing same
US6287892B1 (en) 1997-04-17 2001-09-11 Nec Corporation Shock-resistant semiconductor device and method for producing same
US7165322B1 (en) 1999-03-10 2007-01-23 Micron Technology, Inc. Process of forming socket contacts
US7183194B2 (en) 1999-03-10 2007-02-27 Micron Technology, Inc. Method of forming socket contacts
JP2001267492A (en) * 2000-03-14 2001-09-28 Ibiden Co Ltd Manufacturing method for semiconductor module
JP2008073818A (en) * 2006-09-22 2008-04-03 Murata Mfg Co Ltd Electronic component and composite electronic component

Also Published As

Publication number Publication date
JP2842753B2 (en) 1999-01-06

Similar Documents

Publication Publication Date Title
US7667312B2 (en) Semiconductor device including a heat-transmitting and electromagnetic-noise-blocking substance and method of manufacturing the same
US6121676A (en) Stacked microelectronic assembly and method therefor
EP0634890B1 (en) Packaging structure for microwave circuit
US6756663B2 (en) Semiconductor device including wiring board with three dimensional wiring pattern
US6774473B1 (en) Semiconductor chip module
US6210993B1 (en) High density semiconductor package and method of fabrication
US8338963B2 (en) Multiple die face-down stacking for two or more die
US6919626B2 (en) High density integrated circuit module
KR100924547B1 (en) Semiconductor package module
US8941999B2 (en) Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
US5435733A (en) Connector assembly for microelectronic multi-chip-module
JP2003133518A (en) Semiconductor module
US6740970B2 (en) Semiconductor device with stack of semiconductor chips
US8827730B2 (en) Socket and semiconductor device provided with socket
US20030137808A1 (en) Electronic module having canopy-type carriers
JP4218434B2 (en) Electronic equipment
US20060138630A1 (en) Stacked ball grid array packages
JP2001189412A (en) Semiconductor device and mounting method of semiconductor
JP2002217514A (en) Multichip semiconductor device
JP3968703B2 (en) Leadless package and semiconductor device
JP2001085603A (en) Semiconductor device
JP2842753B2 (en) Semiconductor device
JP3764214B2 (en) Printed circuit board and electronic apparatus equipped with the same
US20070159204A1 (en) Semiconductor device and electronic component module using the same
JP2003078109A (en) Laminated memory device