CN214753703U

CN214753703U - Packaging structure of memory chip

Info

Publication number: CN214753703U
Application number: CN202121460317.5U
Authority: CN
Inventors: 黄志雄; 李华峰; 潘承辽
Original assignee: Guangxi Georgia Industrial Co ltd
Current assignee: Guangxi Georgia Industrial Co ltd
Priority date: 2021-06-29
Filing date: 2021-06-29
Publication date: 2021-11-16
Anticipated expiration: 2031-06-29

Abstract

The utility model discloses a packaging structure of storage chip, its structure includes storage chip main part, sealing device and draws electric installation, the storage chip main part outside is provided with sealing device, sealing device both ends symmetry is provided with draws electric installation around, draw electric installation inboard and storage chip main part fixed connection, the utility model discloses have following beneficial effect, through setting up sealing device in the storage chip main part outside, form the space that has shielding ability through the conductive coating between inner shell layer and the shell layer to improve the beneficial effect of information secrecy ability greatly, the preparation is simple and convenient; and through set up the reinforcement strip in pin portion inboard department, and the fixed embedding shell layer outside of reinforcement strip to this avoids shaking power in shell layer department between inner connecting strip and pin portion, strengthens stable ability, has reached and has set up the beneficial effect of atress support component in order to improve pin intensity additional.

Description

Packaging structure of memory chip

Technical Field

The utility model belongs to the technical field of the chip package, in particular to packaging structure of memory chip.

Background

Packaging, which is a process of assembling an integrated circuit into a chip final product, in short, an integrated circuit bare chip produced by a foundry is placed on a substrate which plays a bearing role, pins are led out, and then the integrated circuit bare chip is fixedly packaged into a whole;

the memory chip is a specific application of the concept of an embedded system chip in the memory industry;

the memory chip is also required to be packaged during manufacturing, but the information confidentiality of the novel memory chip package in the prior art is poor, and the pin strength is low, so that the memory chip package is easy to damage.

SUMMERY OF THE UTILITY MODEL

Technical problem to be solved

In order to overcome the defects of the prior art, a packaging structure of a memory chip is provided so as to solve the problems that the information confidentiality of the memory chip packaging is poor, and the pin strength is low and easy to damage; and the stress supporting component is additionally arranged to improve the strength of the pin.

(II) technical scheme

The utility model discloses a following technical scheme realizes: the utility model provides a storage chip's packaging structure, include storage chip main part, sealing device and draw electric installation, the storage chip main part outside is provided with the sealing device, the both ends symmetry is provided with around the sealing device and draws electric installation, draw electric installation inboard and storage chip main part fixed connection.

Further, the sealing device comprises an inner shell layer, a conductive coating and an outer shell layer, wherein the conductive coating is arranged on the outer side of the inner shell layer, the outer shell layer is arranged on the outer side of the conductive coating, and a storage chip main body is arranged on the inner side of the inner shell layer.

Further, draw electric installation and include inner connecting strip, pin portion and reinforcement strip, the inner connecting strip outside and pin portion integrated into one piece, the inboard middle part integrated into one piece of pin portion has the reinforcement strip, the inner connecting strip runs through inner shell layer and outer shell layer inside and outside both sides simultaneously to the inner connecting strip all with inner shell layer and outer shell layer interference fit, the inner connecting strip inboard and memory chip main part tin soldering, consolidate the inboard fixed outer shell layer outside that imbeds of strip surface.

Furthermore, the inner connecting strips are provided with two groups and are symmetrically arranged at the front end and the rear end of the memory chip main body.

Further, the outer surface of the inner connecting bar is not in contact with the conductive coating.

Furthermore, the material of the electricity leading device is hard conductive material.

(III) advantageous effects

Compared with the prior art, the utility model, following beneficial effect has:

1) the problem that the information confidentiality of the storage chip package is poor is solved, the sealing device is arranged on the outer side of the storage chip main body, and a space with shielding capacity is formed through the conductive coating between the inner shell layer and the outer shell layer, so that the beneficial effect of the information confidentiality is greatly improved, and the manufacturing is simple and convenient.

2) The problem of low and easy damage of pin intensity is solved, through set up the reinforcement strip in the inboard department of pin portion, and the fixed embedding shell layer outside of reinforcement strip to this avoids shaking power in shell layer department between inner connecting strip and the pin portion, strengthens stable ability, has reached and has added the beneficial effect who establishes the atress supporting component in order to improve pin intensity.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

fig. 1 is a schematic structural view of the present invention;

FIG. 2 is a schematic view of the internal structure of the present invention;

in the figure: the memory chip comprises a memory chip body-1, a sealing device-2, a power-on device-3, an inner shell layer-21, a conductive coating-22, an outer shell layer-23, an inner connecting strip-31, a pin part-32 and a reinforcing strip-33.

Detailed Description

Referring to fig. 1 and 2, the present invention provides a package structure of a memory chip: the storage chip comprises a storage chip main body 1, a sealing device 2 and an electric leading device 3, wherein the sealing device 2 is arranged on the outer side of the storage chip main body 1, the electric leading device 3 is symmetrically arranged at the front end and the rear end of the sealing device 2, and the inner side of the electric leading device 3 is fixedly connected with the storage chip main body 1.

The sealing device 2 comprises an inner shell layer 21, a conductive coating 22 and an outer shell layer 23, wherein the conductive coating 22 is arranged on the outer side of the inner shell layer 21, the outer shell layer 23 is arranged on the outer side of the conductive coating 22, the memory chip main body 1 is arranged on the inner side of the inner shell layer 21, and the sealing device is simple and convenient to manufacture by adopting a shielding mode to greatly improve the beneficial effect of information confidentiality.

Wherein, it includes inner connecting strip 31, pin portion 32 and reinforcement strip 33 to draw electric installation 3, the inner connecting strip 31 outside and pin portion 32 integrated into one piece, the inboard middle part integrated into one piece of pin portion 32 has reinforcement strip 33, inner connecting strip 31 runs through inner shell layer 21 and the outer both sides of outer shell layer 23 simultaneously to inner connecting strip 31 all with inner shell layer 21 and outer shell layer 23 interference fit, the inboard and memory chip main part 1 tin welding of inner connecting strip 31, the fixed outer shell layer 23 outside of embedding of reinforcement strip 33 surface is according to the above-mentioned stable ability of strengthening to reached and added the beneficial effect of establishing the atress supporting component in order to improve pin intensity.

The inner connecting strips 31 are arranged in two groups and symmetrically arranged at the front end and the rear end of the memory chip main body 1, and the positions are reasonably arranged according to the above, so that the memory chip is convenient to manufacture.

Wherein, the outer surface of the inner connecting bar 31 is not contacted with the conductive coating 22, and the materials are reasonably arranged according to the above to prevent the electricity from being disturbed.

The material of the electricity leading device 3 is hard conductive material.

The working principle is as follows: firstly, taking out the memory chip main body 1 and placing the memory chip main body at a position needing to be processed;

then, the inner connecting strips 31 are symmetrically soldered to the front end and the rear end of the memory chip main body 1, the memory chip main body 1 is preliminarily sealed by the inner shell layer 21, the conductive coating 22 is arranged on the outer side of the inner shell layer 21, the outer surface of the inner connecting strips 31 is not in contact with the conductive coating 22, the outer shell layer 23 is arranged on the outer side of the conductive coating 22, the protection of the conductive coating 22 is improved, the pin parts 32 are externally leaked from the outer shell layer 23, and the reinforcing strips 33 are embedded into the outer side of the outer shell layer 23;

then, the sealing device 2 is arranged on the outer side of the memory chip main body 1, and a space with shielding capability is formed by the conductive coating 22 between the inner shell layer 21 and the outer shell layer 23, so that the beneficial effect of information confidentiality is greatly improved, and the manufacturing is simple and convenient;

finally, the reinforcing strip 33 is arranged on the inner side of the pin part 32, and the reinforcing strip 33 is fixedly embedded into the outer side of the outer shell layer 23, so that shaking force between the inner connecting strip 31 and the pin part 32 at the outer shell layer 23 is avoided, the stability is enhanced, and the beneficial effect of additionally arranging a stress supporting component to improve the strength of the pin is achieved.

The basic principles and the main features of the invention and the advantages of the invention have been shown and described above, it will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, but that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. A packaging structure of a memory chip is characterized in that: including memory chip main part (1), sealing device (2) and draw electric installation (3), the memory chip main part (1) outside is provided with sealing device (2), both ends symmetry is provided with around sealing device (2) and draws electric installation (3), draw electric installation (3) inboard and memory chip main part (1) fixed connection.

2. The package structure of a memory chip as claimed in claim 1, wherein: the sealing device (2) comprises an inner shell layer (21), a conductive coating (22) and an outer shell layer (23), wherein the conductive coating (22) is arranged on the outer side of the inner shell layer (21), the outer shell layer (23) is arranged on the outer side of the conductive coating (22), and a storage chip main body (1) is arranged on the inner side of the inner shell layer (21).

3. The package structure of a memory chip as claimed in claim 1, wherein: draw electric installation (3) including inscribe strip (31), pin portion (32) and reinforcement strip (33), inscribe strip (31) outside and pin portion (32) integrated into one piece, pin portion (32) inboard middle part integrated into one piece has reinforcement strip (33), inscribe strip (31) run through inner shell layer (21) and outer shell layer (23) inside and outside both sides simultaneously to inscribe strip (31) all with inner shell layer (21) and outer shell layer (23) interference fit, inscribe strip (31) inboard and memory chip main part (1) tin welding, reinforcement strip (33) the inboard fixed outer shell layer (23) outside of embedding of surface.

4. The package structure of a memory chip as claimed in claim 3, wherein: the inner connecting strips (31) are arranged in two groups and symmetrically arranged at the front end and the rear end of the memory chip main body (1).

5. The package structure of a memory chip as claimed in claim 3, wherein: the outer surface of the inner connecting bar (31) is not contacted with the conductive coating (22).