CN214669453U - Data conversion device verification circuit - Google Patents
Data conversion device verification circuit Download PDFInfo
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- CN214669453U CN214669453U CN202120709080.3U CN202120709080U CN214669453U CN 214669453 U CN214669453 U CN 214669453U CN 202120709080 U CN202120709080 U CN 202120709080U CN 214669453 U CN214669453 U CN 214669453U
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Abstract
A data conversion device verification circuit comprises a main control board and a test sub-board; the main control board is connected with the test sub-board through a connector set, the test sub-board is connected with a tested chip, FPGA single-ended signals and FPGA differential signals of the main control board are transmitted to the test sub-board, for different tested chips, only the test sub-board needs to be replaced, and test contents can be completed without replacing the main control board sealed in the case; the upper computer is connected with the main control board through a communication circuit; the communication circuit comprises a serial port circuit and an Ethernet communication circuit which are connected with the main control board; the signal transmission can be carried out through the serial port circuit or the Ethernet communication circuit; the image circuit, the voltage detection circuit and the crystal oscillator circuit respectively realize the functions of processing image data, detecting voltage data and converting energy, and ensure the accuracy of the test.
Description
Technical Field
The utility model belongs to the technical field of the data converter technique and specifically relates to a data conversion device verification circuitry.
Background
With the improvement of digital signal processing technology and digital circuit working speed and the continuous improvement of the requirements for system sensitivity and the like, the high requirements are provided for the indexes of high-speed and high-precision ADC and DAC; for example, in the application fields of mobile communication, image acquisition and the like, on one hand, an ADC is required to have a relatively high sampling rate to acquire a high-bandwidth input signal, and on the other hand, a relatively high number of bits is required to distinguish slight changes, so that the accuracy of the ADC/DAC under the high-speed sampling condition is a very critical problem; need change when testing different chips and survey test panel, survey test panel and install the difficult change in quick-witted incasement portion, therefore need utility model one kind only need change the test daughter board, need not change and seal at quick-witted incasement portion the circuit of test content can be accomplished to the main control board.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to overcome prior art not enough, provide a data conversion device verification circuit.
The utility model provides a its technical problem take following technical scheme to realize:
a data conversion device verification circuit comprises a main control board and a test sub-board; the main control board is connected with the test sub-board through the connector set, the test sub-board is connected with the tested chip, FPGA single-ended signals and FPGA differential signals of the main control board are transmitted to the test sub-board, the tested chip only needs to be replaced for different purposes, and the main control board sealed inside the case does not need to be replaced so as to complete test contents.
Preferably, the system also comprises an upper computer, and the upper computer is connected with the main control board through a communication circuit.
Preferably, the communication circuit comprises a serial port circuit connected with the main control board.
Preferably, the communication circuit includes an ethernet communication circuit connected to the main control board.
Preferably, the image processing device further comprises an image circuit connected with the output end of the main control board for processing image data.
Preferably, the device further comprises a voltage detection circuit connected with the main control board and used for detecting voltage data.
Preferably, the main control board is an FPGA chip for generating test pattern stimulus.
Preferably, the connector group comprises 3 connecting chips, and two ends of each connecting chip are respectively connected with the main control board and the test daughter board.
Preferably, the system further comprises a crystal oscillator circuit connected with the main control board, wherein the crystal oscillator circuit comprises an oscillator for energy conversion.
The utility model has the advantages that:
1. the utility model relates to a data conversion device verification circuit, which comprises a main control board and a test daughter board; the main control board is connected with the test sub-board through the connector set, the test sub-board is connected with the tested chip, FPGA single-ended signals and FPGA differential signals of the main control board are transmitted to the test sub-board, the tested chip only needs to be replaced for different purposes, and the main control board sealed inside the case does not need to be replaced so as to complete test contents.
2. The utility model comprises an upper computer, which is connected with the main control board through a communication circuit; the communication circuit comprises a serial port circuit and an Ethernet communication circuit which are connected with the main control board; the signal transmission can be carried out through the serial port circuit or the Ethernet communication circuit.
3. The utility model discloses a respectively with image circuit, voltage detection circuit and the crystal oscillator circuit that the main control board output is connected realize handling image data, detecting voltage data and energy conversion's effect respectively, guarantee the accuracy of test.
Drawings
Fig. 1 is a connection block diagram of the present invention;
fig. 2 is a circuit connection diagram of the main control board of the present invention;
FIG. 3 is a diagram of the image circuit connection of the present invention;
fig. 4 is a circuit diagram of the connector assembly of the present invention;
FIG. 5 is a circuit diagram of the test daughter board of the present invention;
FIG. 6 is a circuit diagram of the tested chip of the present invention;
FIG. 7 is a circuit diagram of the crystal oscillator of the present invention;
fig. 8 is a connection diagram of the voltage detection circuit of the present invention;
fig. 9 is a serial port circuit connection diagram of the present invention;
fig. 10 is a connection diagram of the ethernet communication circuit of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When a component is referred to as being "disposed on" another component, it can be directly on the other component or intervening components may also be present. The terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1-10, the verification circuit for a data conversion device of the present invention includes a main control board and a test daughter board; the main control board is connected with the test sub-board through the connector set, the test sub-board is connected with the tested chip, FPGA single-ended signals and FPGA differential signals of the main control board are transmitted to the test sub-board, the tested chip only needs to be replaced for different purposes, and the main control board sealed inside the case does not need to be replaced so as to complete test contents.
Further, as shown in fig. 4-6, the connector set includes 3 connection chips, a connection chip RED1, a connection chip RED2, and a connection chip RED 3; b0_ FPGA pins of the main control board are connected with B0_ FPGA pins of the connector group to control the connector group to switch channels, digital channels, differential channels and 204B connecting channels; the connector group is connected with the test daughter board, and the test daughter board is connected with the test chip; the model of the tested chip is AD 9736; specifically, the B0_ FPGA pins of the connector set are respectively connected to the B0_ FPGA pins of the test daughter board, and the DB pins of the test daughter board are respectively connected to the DB pins of the tested chip for testing.
Further, as shown in fig. 2 and 3, the image processing device further includes an image circuit connected to the output end of the main control board to process image data; the image circuit comprises an image chip, wherein the model of the image chip is W25Q 64; specifically, the main control board is an FPGA chip and is used for generating test pattern stimulus, a B0_ DONE pin of the main control board is an open-drain output, and an LED is connected to display whether the main control board is successfully loaded; a B0_ FCS _ B pin of the master control board is connected to the image circuit select input; the B0_ PROG _ B pin of the main control board is a program input pin and allows the program state of the FPGA chip to be reset; the B0_ INIT _ B pin of the main control board is at a low level, which indicates that the FPGA chip is initializing (clearing) the configuration memory, the B0_ INIT _ B pin of the main control board starts to be driven from power-on reset or program reset, and the low level is effective;
the B0_ MOSI pin of the main control board is connected to the B0_ MOSI pin of the image circuit, after the main control board sends commands and addresses to the image circuit, the B0_ MOSI pin of the image circuit is high-impedance, and the B0_ DIN pin of the image circuit is a serial data input pin for receiving serial data from a data source and is connected with the B0_ DIN pin of the main control board.
Further, as shown in fig. 9 and 10, the system further comprises an upper computer, wherein the upper computer is connected with the main control board through a communication circuit; specifically, the communication circuit comprises a serial port circuit and an Ethernet communication circuit; the serial port circuit comprises a serial port chip, and the model of the serial port chip is MAX 13236; the Ethernet communication circuit comprises an Ethernet communication chip; the type of the Ethernet communication chip is RTL 8211; specifically, the FPGA _ IO _ TIN pin and the FPGA _ IO _ ROUT pin of the main control board are respectively connected to the FPGA _ IO _ TIN pin and the FPGA _ IO _ ROUT pin of the serial port circuit MAX 13236; the Ethernet communication circuit RTL8211 is connected with the output end of the main control board, and signals are transmitted through the serial port circuit or the Ethernet communication circuit.
Further, as shown in fig. 8, the apparatus further includes a voltage detection circuit connected to the main control board for detecting voltage data; specifically, the voltage detection circuit comprises a voltage detection chip, and the model of the voltage detection chip is MAX 6306; the P3V3_ CRTL _ MAIN pin of the MAIN control board is connected with the P3V3_ CRTL _ MAIN pin of the voltage detection circuit.
Further, as shown in fig. 7, the electronic device further includes a crystal oscillator circuit connected to the main control board, where the crystal oscillator circuit includes an oscillator for performing energy conversion, and the model of the oscillator is SIT8008 BC; the P3V3_ CRTL _ MAIN pin of the MAIN control board is connected with the P3V3_ CRTL _ MAIN pin of the crystal oscillator circuit.
The working principle is as follows:
1. the main control board is connected with the test sub-board through a connector set, the test sub-board is connected with a tested chip, FPGA single-ended signals and FPGA differential signals of the main control board are transmitted to the test sub-board, for different tested chips, only the test sub-board needs to be replaced, and test contents can be completed without replacing the main control board sealed in the case;
2. the upper computer is connected with the main control board through a communication circuit; the communication circuit comprises a serial port circuit and an Ethernet communication circuit which are connected with the main control board; the signal transmission can be carried out through the serial port circuit or the Ethernet communication circuit;
3. the image circuit connected with the output end of the main control board processes image data;
4. the voltage detection circuit connected with the main control board is used for detecting voltage data;
5. and the crystal oscillator circuit is connected with the main control board and comprises an oscillator for energy conversion.
The utility model relates to a data conversion device verification circuit, which comprises a main control board and a test daughter board; the main control board is connected with the test sub-board through a connector set, the test sub-board is connected with a tested chip, FPGA single-ended signals and FPGA differential signals of the main control board are transmitted to the test sub-board, for different tested chips, only the test sub-board needs to be replaced, and test contents can be completed without replacing the main control board sealed in the case; the upper computer is connected with the main control board through a communication circuit; the communication circuit comprises a serial port circuit and an Ethernet communication circuit which are connected with the main control board; the signal transmission can be carried out through the serial port circuit or the Ethernet communication circuit; the image circuit, the voltage detection circuit and the crystal oscillator circuit respectively realize the functions of processing image data, detecting voltage data and converting energy, and ensure the accuracy of the test.
The above description is for the detailed description of the preferred possible embodiments of the present invention, but the embodiments are not intended to limit the scope of the present invention, and all equivalent changes or modifications accomplished under the technical spirit suggested by the present invention should fall within the scope of the present invention.
Claims (9)
1. A data conversion device verification circuit, characterized by: the test system comprises a main control board and a test sub-board; the main control board is connected with the test sub-board through the connector set, the test sub-board is connected with the tested chip, FPGA single-ended signals and FPGA differential signals of the main control board are transmitted to the test sub-board, the tested chip only needs to be replaced for different purposes, and the main control board sealed inside the case does not need to be replaced so as to complete test contents.
2. The data conversion device verification circuit of claim 1, wherein: the intelligent control system is characterized by further comprising an upper computer, wherein the upper computer is connected with the main control board through a communication circuit.
3. The data conversion device verification circuit of claim 2, wherein: the communication circuit comprises a serial port circuit connected with the main control board.
4. The data conversion device verification circuit of claim 2, wherein: the communication circuit comprises an Ethernet communication circuit connected with the main control board.
5. The data conversion device verification circuit of claim 1, wherein: the image processing device also comprises an image circuit connected with the output end of the main control board for processing image data.
6. The data conversion device verification circuit of claim 1, wherein: the voltage detection circuit is connected with the main control board and is used for detecting voltage data.
7. The data conversion device verification circuit of claim 1, wherein: the main control board is an FPGA chip and is used for generating test pattern excitation.
8. The data conversion device verification circuit of claim 1, wherein: the connector group comprises 3 connecting chips, and two ends of each connecting chip are respectively connected with the main control board and the test daughter board.
9. The data conversion device verification circuit of claim 1, wherein: the crystal oscillator circuit is connected with the main control board and comprises an oscillator for energy conversion.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202120364684 | 2021-02-06 | ||
| CN2021203646849 | 2021-02-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN214669453U true CN214669453U (en) | 2021-11-09 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202120709080.3U Active CN214669453U (en) | 2021-02-06 | 2021-04-07 | Data conversion device verification circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN214669453U (en) |
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2021
- 2021-04-07 CN CN202120709080.3U patent/CN214669453U/en active Active
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